VPX 322xE
ADVANCE INFORMATION
MICRONAS INTERMETALL
2
Contents
Page
Section
Title
6
1.
Introduction
7
1.1.
System Architecture
8
2.
Functional Description
8
2.1.
Analog Front-End
8
2.1.1.
Input Selector
8
2.1.2.
Clamping
8
2.1.3.
Automatic Gain Control
8
2.1.4.
Analog-to-Digital Converters
8
2.1.5.
ADC Range
8
2.1.6.
Digitally Controlled Clock Oscillator
10
2.2.
Adaptive Comb Filter (VPX 3226E only)
11
2.3.
Color Decoder
11
2.3.1.
IF-Compensation
11
2.3.2.
Demodulator
12
2.3.3.
Chrominance Filter
12
2.3.4.
Frequency Demodulator
12
2.3.5.
Burst Detection / Saturation Control
12
2.3.6.
Color Killer Operation
13
2.3.7.
Automatic Standard Recognition
13
2.3.8.
PAL Compensation/1H Comb Filter
14
2.3.9.
Luminance Notch
14
2.4.
Video Sync Processing
15
2.5.
Macrovision Detection
15
2.6.
Component Processing
16
2.6.1.
Horizontal Resizer
17
2.6.2.
Skew Correction
17
2.6.3.
Peaking and Coring
17
2.6.4.
YC
b
C
r
Color Space
17
2.6.5.
Video Adjustments
18
2.7.
Video Output Interface
18
2.7.1.
Output Formats
18
2.7.1.1.
YC
b
C
r
4:2:2 with Separate Syncs/ITU-R601
19
2.7.1.2.
Embedded Reference Headers/ITU-R656
21
2.7.1.3.
Embedded Timing Codes (BStream)
21
2.7.2.
Bus Shuffler
21
2.7.3.
Output Multiplexer
21
2.7.4.
Output Ports
22
2.8.
Video Data Transfer
22
2.8.1.
Single and Double Clock Mode
22
2.8.2.
Clock Gating
23
2.8.3.
Half Clock Mode
24
2.9.
Video Reference Signals
24
2.9.1.
HREF
24
2.9.2.
VREF
24
2.9.3.
Odd/Even Information (FIELD)
26
2.9.4.
VACT
VPX 322xE
ADVANCE INFORMATION
MICRONAS INTERMETALL
3
Contents, continued
Page
Section
Title
27
2.10.
Operational Modes
27
2.10.1.
Open Mode
27
2.10.2.
Scan Mode
29
2.11.
Windowing the Video Field
30
2.12.
Temporal Decimation
31
2.13.
Data Slicer
31
2.13.1.
Slicer Features
31
2.13.2.
Data Broadcast Systems
32
2.13.3.
Slicer Functions
32
2.13.3.1.
Input
32
2.13.3.2.
Automatic Adaptation
32
2.13.3.3.
Standard Selection
32
2.13.3.4.
Output
34
2.14.
VBI Data Acquisition
34
2.14.1.
Raw VBI Data
35
2.14.2.
Sliced VBI Data
36
2.15.
Control Interface
36
2.15.1.
Overview
36
2.15.2.
I
2
C-Bus Interface
36
2.15.3.
Reset and I
2
C Device Address Selection
36
2.15.4.
Protocol Description
37
2.15.5.
FP Control and Status Registers
38
2.16.
Initialization of the VPX
38
2.16.1.
Power-on-Reset
38
2.16.2.
Software Reset
38
2.16.3.
Low Power Mode
39
2.17.
JTAG Boundary-Scan, Test Access Port (TAP)
39
2.17.1.
General Description
39
2.17.2.
TAP Architecture
39
2.17.2.1.
TAP Controller
39
2.17.2.2.
Instruction Register
39
2.17.2.3.
Boundary Scan Register
40
2.17.2.4.
Bypass Register
40
2.17.2.5.
Device Identification Register
40
2.17.2.6.
Master Mode Data Register
40
2.17.3.
Exception to IEEE 1149.1
40
2.17.4.
IEEE 1149.11990 Spec Adherence
40
2.17.4.1.
Instruction Register
40
2.17.4.2.
Public Instructions
41
2.17.4.3.
Self-Test Operation
41
2.17.4.4.
Test Data Registers
41
2.17.4.5.
Boundary-Scan Register
41
2.17.4.6.
Device Identification Register
41
2.17.4.7.
Performance
45
2.18.
Enable/Disable of Output Signals
VPX 322xE
ADVANCE INFORMATION
MICRONAS INTERMETALL
4
Contents, continued
Page
Section
Title
46
3.
Specifications
46
3.1.
Outline Dimensions
47
3.2.
Pin Connections and Short Descriptions
49
3.3.
Pin Descriptions
50
3.4.
Pin Configuration
51
3.5.
Pin Circuits
53
4.
Electrical Characteristics
53
4.1.
Absolute Maximum Ratings
54
4.2.
Recommended Operating Conditions
54
4.2.1.
Recommended Analog Video Input Conditions
55
4.2.2.
Recommended I
2
C Conditions for Low Power Mode
55
4.2.3.
Recommended Digital Inputs Levels of RES, OE, TCK, TMS, TDI
56
4.2.4.
Recommended Crystal Characteristics
57
4.3.
Characteristics
57
4.3.1.
Current Consumption
57
4.3.2.
Characteristics, Reset
57
4.3.3.
XTAL Input Characteristics
58
4.3.4.
Characteristics, Analog Front-End and ADCs
59
4.3.5.
Characteristics, Control Bus Interface
59
4.3.6.
Characteristics, JTAG Interface (Test Access Port TAP)
60
4.3.7.
Characteristics, Digital Inputs/Outputs
60
4.3.8.
Clock Signals PIXCLK, LLC, and LLC2
61
4.3.9.
Digital Video Interface
61
4.3.10.
Characteristics, TTL Output Driver
62
4.3.10.1.
TTL Output Driver Description
63
5.
Timing Diagrams
63
5.1.
Power-up Sequence
63
5.2.
Default Wake-up Selection
64
5.3.
Control Bus Timing Diagram
65
5.4.
Output Enable by Pin OE
66
5.5.
Timing of the Test Access Port TAP
66
5.6.
Timing of all Pins connected to the Boundary-Scan-Register-Chain
67
5.7.
Timing Diagram of the Digital Video Interface
67
5.7.1.
Characteristics, Clock Signals
68
6.
Control and Status Registers
68
6.1.
Overview
71
6.1.1.
Description of I
2
C Control and Status Registers
75
6.1.2.
Description of FP Control and Status Registers
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