3236 Scott Boulevard
Santa Clara, California 95054
Phone: (408) 986-5060
Fax: (408) 986-5095
CHP0230-PM
Features
InGaP HBT Technology
6mm Square, 50 Ohm Power Module Package
Single Positive Supply
35% Linear Power Added Efficiency
50% Analog Power Added Efficiency
+28.5 dBm Output Power (CDMA Mode)
30 dB Gain at Operating Output Power
On-Board Power Down Mode
Applications
Cellular Multi-Mode Handsets
Cellular Infrastructure
Wireless Local Loop Subscriber Units
CDMA Handsets
CDMA2K 1X Handsets
Description
The CHP0230-PM is a 50 ohm matched, single sup-
ply, linear power amplifier module intended for use in cellular
handsets and wireless local loop subscriber units. The highly
integrated amplifier meets the requirements of CDMA and
CDMA2K 1X systems. It is a member of Celeritek's new
TrueTriangleTM family of 3V power amplifier modules.
The CHP0230-PM is packaged in a low-cost, space
efficient, 6mm square, matched module that provides excellent
electrical stability and low thermal resistance. The module
operates from a fixed positive voltage and requires no external
matching which significantly reduces space, cost and enhances
ease of use.
The 6x6 mm package is self contained, incorporating
50 ohm input and output matching networks optimized for
output power, linearity and efficiency.
Celeritek's InGaP HBT technology offers a thermally
robust and reliable PAM (power amplifier module) solution.
824 to 849 MHz
28.5 dBm, Cellular
InGaP HBT Amplifier Module
Product Specifications
July 2002
(1 of 4)
Functional Block Diagram
Application Information
The CHP0230-PM is a two-stage amplifier that requires a
single regulated positive supply along with the unregulated bat-
tery voltage for proper operation. Vref is a regulated 2.95 refer-
ence voltage for the bias control circuitry. It can also be used as
a power down mode select. Vcc is an unregulated supply volt-
age directly from the battery. Vcc should be applied prior to
Vref and before RF input power. The CHP0230-PM can be
operated over a range of supply voltages and bias points by
adjustment of Vref. It is important that the maximum power
dissipation of the package be observed at all times and that the
maximum voltage across the device is not exceeded.
Circuit Design Considerations
Biasing The positive Vcc supply voltages are applied to pins
1 and 6. Most bypass decoupling is provided on-board. Vref is
applied to pin 3.
The recommended DC bypass capacitance is shown in the
schematic diagram on Page 4.
Inadequate bypass capacitance and inductance around the
DC supply lines can compromise the adjacent channel power
ratio (ACPR), reduce power gain and/or create oscillations.
Continued on Page 2
TM
Absolute Maximum Ratings
Parameter
Rating
Parameter
Rating
Parameter
Rating
Collector Voltage (+Vcc)
+6.0 V*
Reference Voltage (Vref)
+3.1 V
Operating Temperature
-40C to +100C
Collector Current (Icc)
1.2 A
Power Dissipation
5 W
Storage Temperature
-65C to +150C
RF Input Power
7 dBm
Soldering Temperature
260C for 5 Sec.
Recommended Operating Conditions
Parameter
Typ
Units
Parameter
Typ
Units
Collector Voltage (+Vcc)
3.2 to 4.1
Volts
Operating Temperature (PC Board)
-20 to +70
C
Reference Voltage (Vref)
+2.95 (1.2%)
Volts
(Fixed and regulated)
* RF Off.
Vcc 1
RF IN 2
Vref 3
6 Vcc
5 RF OUT
4 N/C
Ground connection is
on backside
BIAS
3236 Scott Boulevard, Santa Clara, California 95054
Phone: (408) 986-5060
Fax: (408) 986-5095
CHP0230-PM
Product Specifications - July 2002
(2 of 4)
Parameter
Condition
Min
Typ
Max
Units
Frequency Range
824
849
MHz
Gain
@ Digital power output
29
30
33
dB
Gain Ripple*
824-849 MHz
1.5
dB
Gain Variation
Over supply voltage
2
dB/V
Over temperature
0.03
dB/C
Power Output
CDMA mode
+28.5
dBm
Analog
+31.0
dBm
Harmonics
2nd @ Po = +31.5 dBm
-30
dBc
3rd @ Po = +31.5 dBm
-30
dBc
Noise Power in Receive Band
30 kHz bandwidth
-90
dBm
Linearity (ACPR)
CDMA mode @ +28.5 dBm Pout, 885 kHz offset
-52
-47
dBc/30KHz
CDMA mode @ +28.5 dBm Pout, 1.9 MHz offset
-59
-56
dBc/30KHz
CDMA2K 1X mode** @ +27.8 dBm Pout, 885 kHz offset
-49
-47
dBc/30KHz
CDMA2K 1X mode** @ +27.8 dBm Pout, 1.9 MHz offset
-58
-56
dBc/30KHz
Noise Figure
4.0
5.0
dB
Input Return Loss
-10
dB
Icc (Vcc = 3.6 V)
Pout = +12.0 dBm - CDMA mode
105
112
mA
Pout = +28.5 dBm - CDMA mode
515
560
mA
Pout = +31.5 dBm - Analog mode
750
815
mA
Quiescent Current (Iq)
No RF
60
mA
Vref Supply Current (Iref)
2.0
5.0
mA
Vref Supply Voltage (Vref)
Fixed and regulated (1.2% tolerance)
2.95
V
Leakage Current
Vref = 0 V, Vcc = 3.6 V
10
A
Electrical Characteristics
Unless otherwise specified, the following specifications are guaranteed at room temperature with collector voltage (+Vcc) = 3.6 V.
* Specifications guaranteed over the temperature range of -20C to +70C. ** Modulation HPSK in 1.2288 MHz, RC3 PAR = 4.7 @ 1% CCDF.
Modulation When biased as specified, the CHP0230-PM will
achieve the required adjacent channel response for the digital
system specified. Celeritek tests 100% of each product under
digital modulation to ensure correlation to customer applica-
tions.
Thermal
1. The ground pad on the backside of the CHP0230-PM must
be soldered to the ground plane.
2. All leads of the package must be soldered to the appropriate
electrical connection.
Continued from Page 1
TM
3236 Scott Boulevard
Santa Clara, California 95054
Phone: (408) 986-5060
Fax: (408) 986-5095
CHP0230-PM
Product Specifications - July 2002
(3 of 4)
TM
Product Consistency Distribution
Note: Unless otherwise specified, the following data was taken at 836 MHz.
10000
8000
4000
2000
0
0.68
0.7
0.8
0.78
0.74
Amps
0.82
-3sp
MEAN
+3sp
USL
Current (Analog)
@ 3.6 V, Pout = 31.5 dBm
6000
0.72
0.76
7000
1000
0
0.48
0.54
0.52
Amps
0.58
-3sp
MEAN
+3sp
USL
Current (CDMA)
@ 3.6 V, Pout = 28.5 dBm
3000
5000
0.5
0.56
6000
4000
2000
1000
0
26
27
30
29
dB
32
-3sp
MEAN
+3sp
USL
Gain (Analog)
@ 3.6 V, Pout = 31.5 dBm
3000
5000
28
3000
500
0
28.5
31.5
31
30.5
dB
32.5
-3sp
MEAN
+3sp
Gain (CDMA)
@ 3.6 V, Pout = 28.5 dBm
1000
2000
29
29.5
32
8000
6000
2000
0
-56
-50
-52
dBc
-48
-3sp
MEAN
+3sp
USL
Linearity (ACPR)
@ 3.6 V, Pout = 28.5 dBm (885 MHz)
4000
-52
6000
2000
0
-64
-58
-59
-60
dBc
-56
-3sp
MEAN
+3sp
Linearity (ACPR)
@ 3.6 V, Pout = 28.5 dBm (1.98 MHz)
4000
5000
-63
-62
-57
2000
6000
4000
7000
LSL
31
33
USL
LSL
1500
2500
30
-46
3000
1000
-61
3236 Scott Boulevard, Santa Clara, California 95054
Phone: (408) 986-5060
Fax: (408) 986-5095
CHP0230-PM
Product Specifications - July 2002
(4 of 4)
Celeritek reserves the right to make changes without further notice to any products herein. Celeritek makes no warranty, representation or guarantee regarding the
suitability of its products for any particular purpose, nor does Celeritek assume any liability arising out of the application or use of any product or circuit, and specifically
disclaims any and all liability, including without limitation consequential or incidental damages. "Typical" parameters can and do vary in different applications. All operating
parameters, including "Typicals" must be validated for each customer application by customer's technical experts. Celeritek does not convey any license under its patent
rights nor the rights of others. Celeritek products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body,
or other applications intended to support or sustain life, or for any other application in which the failure of the Celeritek product could create a situation where personal
injury or death may occur. Should Buyer purchase or use Celeritek products for any such unintended or unauthorized application, Buyer shall indemnify and hold Celeritek
and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out
of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that Celeritek was negligent
regarding the design or manufacture of the part. Celeritek is a registered trademark of Celeritek, Inc. Celeritek, Inc. is an Equal Opportunity/Affirmative Action Employer.
TM
Ordering Information
The CHP0230-PM is available in a surface mount 50 ohm matched module and devices are available in tube or tape and reel.
Part Number for Ordering
Package
CHP0230-PM-0000
PM6 surface mount power package in tube
CHP0230-PM-000T
PM6 surface mount power package in tape and reel
PB-CHP0230-PM
Evaluation Board with SMA connectors for CHP0230-PM
Physical Dimensions
Recommended Application Circuit
Note: This schematic represents the topology of the application cir-
cuit recommended by Celeritek.
Evaluation Board Schematic
Board substrate:
ER = 4.60
Thickness = 0.031 in.
RF OUT
50
Vcc
N/C
Vref
RF IN
CHP0230-PM
50
220 pF
3.3 F
10 F
1
2
3
4
5
6
PCB Footprint (Minimum Pad Dimensions)
0.015 (0.38) DIA.
VIA HOLE X21
0.032 (0.80)
MIN. X6
0.240
(6.10)
0.060 (1.50) MIN.
0.295 (7.50)
0.100 (2.55)
0.054 (1.36) X4
DIMENSIONS IN INCHES (mm)
DRAWING NOT TO SCALE
0.015 (0.40)
RADIUS
X12
T1
T1 line is important to ensure best bypassing. Optimum performance
is achieved through an electrical length of 20min. at 835 MHz.
PDF 
ZIP