3236 Scott Boulevard
Santa Clara, California 95054
Phone: (408) 986-5060
Fax: (408) 986-5095
CPM1530-PM
Features
t Operation as Low as 3.2V
t 35% Linear Power Added Efficiency
t +28 dBm Output Power (IS-98 CDMA Mode)
t 30 dB Gain at Operating Output Power
t Tested Under Digital Modulation
t New 50 Ohm Power Module Package
t PHEMT Material Technology
t Fixed Gate Bias
Applications
t PCS Handsets
t PCS Base Stations
t Wireless Local Loop Subscriber Units
t cdmaOne Handsets
Description
The CPM1530-PM is a 50 ohm, matched, linear
power amplifier module intended for use in PCS handsets and
wireless local loop subscriber units. The amplifier meets the
requirements of PCS-1900 or IS-98 (CDMA) systems. It is a
member of Celeritek's new
True
v
TriangleTM
family of 3V
power amplifier modules.
The CPM1530-PM is packaged in a low-cost, space
efficient, matched module that provides excellent electrical
stability and low thermal resistance. The part requires no
external matching and a fixed negative voltage significantly
reducing space and cost and enhancing ease of use.
This device is unconditionally stable under all source
and load impedances.
1.85 to 1.91 GHz
3.2V, 28 dBm, PCS
50 Ohm Linear Power Module
Advanced Product Information
August 1999
(1 of 4)
RF IN 1
Vdd1 2
Vdd2/3 3
6 Vgg
4 RF OUT
5 GND
GND
12
GND
11
GND
10
7
GND
8
GND
9
GND
Backside is Ground
Functional Block Diagram
Absolute Maximum Ratings
Parameter
Rating
Parameter
Rating
Parameter
Rating
Drain Voltage (+Vd)
+5.5 V*
Power Dissipation
5 W
Operating Temperature
-40C to +90C
Drain Current (Id)
1.8 A
Thermal Resistance
20C/W
Channel Temperature
150C
RF Input Power
3 dBm*
Storage Temperature
-65C to +150C
Soldering Temperature
260C for 5 Sec.
DC Gate Voltage (-Vg)
-3.0 V*
Recommended Operating Conditions
Parameter
Typ
Units
Parameter
Typ
Units
Drain Voltage (+Vd)
3.2 to 4.1
Volts
Operating Temperature (PC Board)
-30 to +80
C
Gate Voltage (Vgg) (Fixed and regulated) -2.5
Volts
* Max (+Vd) and (-Vg) under linear operation. Max potential difference across the device at 1dB gain compression point (2Vd + |-Vg|) not to exceed the minimum breakdown voltage (Vbr) of +12V.
Application Information
The CPM1530-PM is a three stage amplifier that requires
positive and negative supply voltages for proper operation. It
is essential when turning on the device that the negative sup-
ply be applied before the positive supply. When turning the
device off, the positive supply should be removed before the
negative supply is removed.
The CPM1530-PM can be operated over a range of sup-
ply voltages and bias points. It is important that the maximum
power dissipation of the package be observed at all times and
that the maximum voltage across the device is not exceeded.
Circuit Design Considerations
Biasing A negative gate voltage is necessary to set the bias
currents of the three FET stages in the CPM1530-PM. This is
accomplished via a fixed -2.5 V to pin 6. The positive supply
voltages are applied to pins 2 and 3. Bypass decoupling is pro-
vided on-board.
The recommended DC by-pass capacitance and low-pass
in-line inductance are shown in the evaluation board on Page 4.
Inadequate by-pass capacitance and inductance around the
DC supply lines can compromise the adjacent channel power
ratio (ACPR), reduce power gain and/or create oscillations.
Supply Ramping To obtain power ramping, gate supply con-
trol is recommended.
Mode Switching If further efficiency is required at lower
power levels, then an adjustment of the fixed Vgg can be made.
Continued on Page 2
3236 Scott Boulevard, Santa Clara, California 95054
Phone: (408) 986-5060
Fax: (408) 986-5095
CPM1530-PM
Advanced Product Information - August 1999
(2 of 4)
Parameter
Condition
Min
Typ
Max
Units
Frequency Range
1.85
1.91
GHz
Gain
@ Digital power output
28
30
dB
Gain Ripple*
1850-1910 MHz
1.5
dB
Gain Variation
Over supply voltage
2
dB/V
Over temperature
0.03
dB/C
Power Output
Meets IS-98 CDMA mask
+28
dBm
Harmonics
2nd @ Digital power output, no output trapping, Po=+28.0 dBm
-30
dBc
3rd @ Digital power output, no output trapping, Po=+28.0 dBm
-40
dBc
Noise Power in Receive Band
30 kHz bandwidth
-94
dBm
Linearity (ACPR)
CDMA modulation @ +28.0 dBm Pout, 1.25 MHz offset
-45
dBc/30KHz
Spurious Signal
VSWR = 3:1 in-band, VSWR = 10:1 out-of-band
-80
dBc
Noise Figure
3.0
dB
Input Return Loss
10
dB
Efficiency (Vdd = 3.2 V)
Pout = +16.0 dBm - CDMA
5
7
%
Pout = +28.0 dBm - CDMA
32
35
%
Positive Supply Current (Id)
Pout IS-98 CDMA (27 dBm)
470
mA
Quiescent Current (Iq)
No RF CDMA mode
130
mA
Negative Supply Current (-Ig)
Includes internal resistor divider
1.1
2.0
mA
Negative Supply Voltage (-Vgg) Fixed and regulated
-2.5
V
Electrical Characteristics
Unless otherwise specified, the following specifications are guaranteed at room temperature with drain voltage (+Vd) = 3.7 V.
* Specifications guaranteed over the temperature range of -20C to +80C
Modulation When biased as specified, the CPM1530-PM
will achieve the required adjacent channel response for the
digital PCS system specified. Celeritek tests each product
under digital modulation to ensure correlation to customer
applications.
Thermal
1. The ground pad on the backside of the CPM1530-PM must
be soldered to the ground plane.
2. All 12 leads of the package must be soldered to the appro-
priate electrical connection.
Continued from Page 1
3236 Scott Boulevard
Santa Clara, California 95054
Phone: (408) 986-5060
Fax: (408) 986-5095
CPM1530-PM
Advanced Product Information - August 1999
(3 of 4)
6
4
5
12
11
10
RF IN
CPM1530-PM
RF OUT
1
2
3
7
8
9
10 F
0.1 F
0.1 F
0.1 F
Vdd
Vgg
Ordering Information
The CPM1530-PM is available in a surface mount 50 ohm matched module and devices are available in tube or tape and reel.
Part Number for Ordering
Package
CPM1530-PM-00S0
PM-12 CDMA surface mount power package in tube
CPM1530-PM-00ST
PM-12 CDMA surface mount power package in tape and reel
PB-CPM1530-PM-00S0
Evaluation Board with SMA connectors for CPM1530-PM-00S0 tested CDMA
Physical Dimensions
Recommended Application Circuit
Note: This schematic represents the topology of the application circuit recommended by Celeritek.
Evaluation Board Schematic
Board substrate:
ER = 4.60
Thickness = 0.031 in.
3236 Scott Boulevard, Santa Clara, California 95054
Phone: (408) 986-5060
Fax: (408) 986-5095
CPM1530-PM
Advanced Product Information - August 1999
(4 of 4)
Celeritek reserves the right to make changes without further notice to any products herein. Celeritek makes no warranty, representation or guarantee regarding the
suitability of its products for any particular purpose, nor does Celeritek assume any liability arising out of the application or use of any product or circuit, and specifically
disclaims any and all liability, including without limitation consequential or incidental damages. "Typical" parameters can and do vary in different applications. All operating
parameters, including "Typicals" must be validated for each customer application by customer's technical experts. Celeritek does not convey any license under its patent
rights nor the rights of others. Celeritek products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body,
or other applications intended to support or sustain life, or for any other application in which the failure of the Celeritek product could create a situation where personal
injury or death may occur. Should Buyer purchase or use Celeritek products for any such unintended or unauthorized application, Buyer shall indemnify and hold Celeritek
and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out
of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that Celeritek was negligent
regarding the design or manufacture of the part. Celeritek is a registered trademark of Celeritek, Inc. Celeritek, Inc. is an Equal Opportunity/Affirmative Action Employer.
Notes
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