N8471BL1
product bulletin
October 26, 1998
Bt8471
Referenced Literature:
N8474DSB
Product Affected:
Bt8471
Please see the attached pages for brief technical overview of the Bt8471
Multichannel Synchronous Communications Controller (MUSYCC
TM
) device.
N8471BL1
N8471BL1
PCI Bus
Local Bus
Ser
ial Data Bus
Host
Interface
Device
Configuration
Registers
PCI
Interface
PCI
Configuration
Space
(Function 0)
PCI
Configuration
Space
(Function 1)
Serial Interface - Channel Group 0
Boundary Scan and Test Access
Expansion Bus Interface
DMA
Controller
Tx/Rx - DMAC
Bit Level
Processor
Tx/Rx -BLP
Interrupt
Controller
Port
Interface
Tx/Rx
Bt8471
Multichannel Synchronous Communications Controller
(MUSYCC
TM
)
Product Description
The Bt8471 is the newest member of the family of advanced Multichannel
Synchronous Communications Controllers (MUSYCC
TM
) which include the
Bt8474/2 (64/128 channel HDLC controller). Bt8471 formats and deformats
up to 32 HDLC channels in a single CMOS integrated circuit. MUSYCC operates
at Layer 2 of the Open Systems Interconnection (OSI) protocol reference
model and provides a comprehensive, high-density solution for processing of
HDLC channels for inter-networking applications such as Frame Relay, ISDN
D-channel signaling, X.25, Signaling System 7 (SS7), DXI, ISLP and LAN/WAN
data transport. Under minimal host supervision, MUSYCC manages a linked
list of channel data buffers in host memory by performing Direct Memory
Access (DMA) of up to 32 channels (Bt8471), 64 channels (Bt8472), and 128
channels (Bt8474).
Bt8471 interfaces to a serial data stream, such as T1/E1 signals, and then
transfers data across the popular 32-bit Peripheral Component Interface (PCI)
bus to system memory at a rate of up to 33 MHz. Bt8471's serial interface can
be operated up to 8.192 MHz. Logical channels can be mapped as any
combination of DS0 timeslots to support ISDN hyperchannels (Nx64 Kb/s) or
as any number of bits in a DS0 for subchanneling applications (Nx8 Kb/s).
Bt8471 also includes a 32-bit expansion port for bridging the PCI bus to local
microprocessors or peripherals. A JTAG port enables boundary-scan testing to
replace bed-of-nails board testing.
All specifications for the Bt8471 are identical to the Bt8472 unless
otherwise stated in this document.
Distinguishing Features
32-channel HDLC controller
OSI Layer 2 protocol support
General purpose HDLC (ISO 3309)
X.25 (LAPB)
Frame relay (LAPF/ANSI T1.618)
ISDN D-channel (LAPD/Q.921)
SS7 support
1 serial interface that supports:
T1/E1 data streams
DC to 8.192 Mb/s TDM bus
Configurable logical channels
Standard DS0 (56, 64 Kbps)
Hyperchannel (Nx64)
Subchannel (Nx8)
Per-channel protocol mode selection
16-bit FCS mode
32-bit FCS mode
SS7 mode (16-bit FCS)
Transparent mode (unformatted
data)
Per-channel DMA buffer management
Linked list data structures
Variable size transmit/receive FIFO
Per-channel message length check
Select no length checking
Select from two 14-bit registers to
compare message length
Maximum length: 16,384 bytes
Direct PCI bus interface
32-bit, 33 MHz operation
Bus master and slave operation
PCI Version 2.1
Local expansion bus interface (EBUS)
32-bit multiplexed address/data bus
Low power, 5 volt CMOS operation
JTAG boundary scan access port
160-pin PQFP surface-mount package
Applications
ISDN basic-rate or primary-rate
interfaces
ISDN D-channel controller
Routers
Cellular base station switch controller
CSU/DSU
Protocol converter
Packet data switch
Frame relay switches/Frame Relay
Access Devices (FRAD)
DXI network interface
Distributed packet-based
communications systems
Access multiplexer/concentrator
Functional Block Diagram
N8471BL1
Copyright 1998 Rockwell Semiconductor Systems, Inc. All rights reserved.
Print date: October 1998
Rockwell Semiconductor Systems, Inc. reserves the right to make changes to its products or specifications to improve
performance, reliability, or manufacturability. Information furnished is believed to be accurate and reliable. However, no
responsibility is assumed for its use; nor for any infringement of patents or other rights of third parties which may result from its
use. No license is granted by its implication or otherwise under any patent or intellectual property rights of Rockwell
Semiconductor Systems, Inc.
Rockwell Semiconductor Systems, Inc. products are not designed or intended for use in life support appliances, devices, or
systems where malfunction of a Rockwell Semiconductor Systems, Inc. product can reasonably be expected to result in personal
injury or death. Rockwell Semiconductor Systems, Inc. customers using or selling Rockwell Semiconductor Systems, Inc.
products for use in such applications do so at their own risk and agree to fully indemnify Rockwell Semiconductor Systems, Inc.
for any damages resulting from such improper use or sale.
Bt is a registered trademark of Rockwell Semiconductor Systems, Inc.
Product names or services listed in this publication are for identification purposes only, and may be trademarks or registered
trademarks of their respective companies. All other marks mentioned herein are the property of their respective holders.
Specifications are subject to change without notice.
PRINTED IN THE UNITED STATES OF AMERICA
Ordering Information
Model Number
Version
Package
Temperature Range
28471-16
32-Channel
160-Pin Plastic Quad Flat Pack (PQFP)
0 C to +70 C
28471-17
32-Channel
160-Pin Plastic Quad Flat Pack (PQFP)
40 C to +85 C
N8471BL1
1
Product Definition
The Bt8471 is identical to the Bt8472, except the Bt8471 has these features:
32-channel HDLC controller
1 serial interface
Pins 12, 13, 15, 16 and 99-101 labeled NC
Figure 1 displays the pinout diagram of the Bt8471. Figure 2 displays the
logic diagram. Table 1 details Register 0, Address 00h, with the Device ID and
Vendor ID bits.
Figure 1. Bt8471 Pinout Configuration
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
120
119
118
117
116
115
114
113
112
111
110
109
108
107
106
105
104
103
102
101
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
Bt8471
V
DDo
AD
[7
]
CB
E[0]
*
AD
[8
]
AD
[9
]
AD
[
1
0
]
AD
[
1
1
]
AD
[
1
2
]
AD
[
1
3
]
AD
[
1
4
]
VS
So
AD
[
1
5
]
CB
E[1]
*
PA
R
S
E
RR*
P
E
RR*
ST
OP*
DE
VS
EL*
TRD
Y
*
IRD
Y
*
VS
So
V
DDo
F
R
AM
E*
CB
E[2]
*
AD
[
1
6
]
AD
[
1
7
]
AD
[
1
8
]
AD
[
1
9
]
AD
[
2
0
]
AD
[
2
1
]
VS
So
AD
[
2
2
]
AD
[
2
3
]
ID
S
E
L
CB
E[3]
*
AD
[
2
4
]
AD
[
2
5
]
AD
[
2
6
]
AD
[
2
7
]
VS
So
VSSo
NC
VDDc
NC
VSSc
NC
NC
NC
NC
NC
NC
NC
NC
VDDi
NC
NC
ROOF[0]
RCLK[0]
RSYNC[0]
RDAT[0]
TCK
TRST*
TMS
TDO
TDI
INTB*
INTA*
VDDc
PCLK
VSSc
PRST*
VDDo
VSSo
GNT*
REQ*
AD[31]
AD[30]
AD[29]
AD[28]
VDDo
VS
So
EA
D[
9]
EA
D[
10]
EA
D[
11]
EA
D[
12]
EA
D[
13]
EA
D[
14]
EA
D[
15]
EA
D[
16]
VS
So
EA
D[
17]
EA
D[
18]
EA
D[
19]
EA
D[
20]
EA
D[
21]
EA
D[
22]
EA
D[
23]
EA
D[
24]
EA
D[
25]
VDDo
VS
So
EA
D[
26]
EA
D[
27]
EA
D[
28]
EA
D[
29]
EA
D[
30]
EA
D[
31]
ECLK
W
R*(R/W
R
*)
RD* (
D
S*)
ALE
*
(AS
*)
EI
NT
*
HOLD (
B
R*)
HLD
A (B
G*)
BG
A
C
K
*
EB
E[
3]*
EB
E[
2]*
EB
E[
1]*
EB
E[
0]*
VDDo
VDDo
EAD[8]
EAD[7]
EAD[6]
EAD[5]
EAD[4]
EAD[3]
EAD[2]
EAD[1]
EAD[0]
VSSc
NC
VDDc
NC
NC
NC
VSSi
NC
NC
NC
NC
NC
VSSc
TCLK[0]
VDDc
TSYNC[0]
TDAT[0]
TM[0]
TM[1]
TM[2]
VSSo
VDDo
AD[0]
AD[1]
AD[2]
AD[3]
AD[4]
AD[5]
AD[6]
VSSo
2
N8471BL1
Figure 2. Bt8471 Logic Diagram
BGACK*
HLDA (BG*)
HOLD (BR*)
EINT*
ALE* (AS*)
WR* (R/WR*)
ROOF[0]
RCLK[0]
RSYNC[0]
RDAT[0]
TCK
TRST*
TMS
TDO
TDI
PCLK
PRST*
GNT*
IDSEL
FRAME*
IRDY*
TRDY*
DEVSEL*
STOP*
PERR*
PAR
ECLK
EBE[3:0]*
EAD[31:0]
TCLK[0]
TSYNC[0]
TDAT[0]
TM[0]
TM[1]
TM[2]
CBE[3:0]*
Expansion Bus
Interface
Receive Serial
Channel Group
0
Boundary Scan
Test Signal
Host (PCI)
Interface
Transmit Serial
Channel Group
0
Scan Chain
Test Access
Bus Grant Acknowledge
Hold Acknowledge
Hold Request
Expansion Bus Interrupt
Address Latch Enable
Write Strobe/Read
Out Of Frame
Clock
Synchronization
Data
JTAG Clock
JTAG Reset
JTAG Mode Select
JTAG Data Out
JTAG Data In
Clock
Reset
Grant
Initialization Device Select
Frame
Initiator Ready
Target Ready
Device Select
Stop
Parity Error
Parity
Clock
Expansion Bus Byte Enable
Clock
Synchronization
Data
Scan Enable
Scan Mode Bit 1
Scan Mode Bit 2
Command and Byte Enables
Expansion Bus Address/Data
I/O
I
O
I
O
O
I
I
I
I
I
I
I
O
I
I
I
I
I
I/O
I/O
I/O
I/O
I/O
I/O
I/O
O
O
I/O
I
I
O
I
I
I
O
155
154
153
152
151
149
17
18
19
20
21
22
23
24
25
29
31
34
47
58
61
62
63
64
65
67
95
94
93
92
91
148
(1)
RD* (DS*)
Read Strobe O 150
(2)
Serial Interface
INTA*
PCI Interrupt A
O
27
INTB*
PCI Interrupt B
O
26
REQ*
Request
O
35
SERR*
System Error
O
66
AD[31:0]
Address and Data Bus I/O
(3)
(4)
97
N8471BL1
3
Table 1. Register 0, Address 00h
Bit
Field
Name
Reset
Value
Type
Description
31:16
Device ID
(1)
8472h
RO
This unique device identification is assigned by the
manufacturer. This field always returns the value 8472h for the
Bt8471.
15:0
Vendor ID
(1)
109Eh
RO
The unique vendor identification assigned to the manufacturer.
This field always returns the value 109Eh.
(1) Registers shared between Function 0 and 1.
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