Document Outline

• CN8236
• Table of Contents
• List of Figures
• List of Tables
• 1.0 CN8236 Product Overview
  • 1.1 Introduction
  • 1.2 Service-Specific Performance Accelerators
  • 1.3 Designer Toolkit
• 2.0 Architecture Overview
  • 2.1 Introduction
  • 2.2 High Performance Host Architecture with Buffer Isolation
    • 2.2.1 Multiple ATM Clients
    • 2.2.2 CN8236 Queue Structure
    • 2.2.3 Buffer Isolation Utilizing Descriptor-Based Buffer Chaining
    • 2.2.4 Status Queue Relation to Buffers and Descriptors
    • 2.2.5 Write-only Control/Status
    • 2.2.6 Scatter/Gather DMA
    • 2.2.7 Interrupts
  • 2.3 Automated Segmentation Engine
  • 2.4 Automated Reassembly Engine
  • 2.5 Advanced xBR Traffic Management
    • 2.5.1 CBR Traffic
    • 2.5.2 VBR Traffic
    • 2.5.3 ABR Traffic
    • 2.5.4 UBR Traffic
    • 2.5.5 GFR Traffic
    • 2.5.6 xBR Cell Scheduler
    • 2.5.7 ABR Flow Control Manager
  • 2.6 Burst FIFO Buffers
  • 2.7 Implementation of OAM-PM Protocols
  • 2.8 Standards-Based I/O
  • 2.9 Electrical/Mechanical
  • 2.10 Logic Diagram and Pin Descriptions
• 3.0 Host Interface
  • 3.1 Overview
  • 3.2 Multiple Client Architecture
    • 3.2.1 Logical Clients
    • 3.2.2 Resource Allocation
    • 3.2.3 Resource Isolation
    • 3.2.4 Peer-to-Peer Transfers
    • 3.2.5 Local Processor Clients
  • 3.3 Write-only Control and Status
    • 3.3.1 Write-only Control Queues
      • 3.3.1.1 Control Variables
      • 3.3.1.2 Queue Management
      • 3.3.1.3 Underflow Conditions
    • 3.3.2 Write-only Status Queues
      • 3.3.2.1 Control Variables
      • 3.3.2.2 Queue Management
      • 3.3.2.3 Overflow Conditions
      • 3.3.2.4 Status Queue Interrupt Delay
• 4.0 Segmentation Coprocessor
  • 4.1 Overview
  • 4.2 Segmentation Functional Description
    • 4.2.1 Segmentation VCCs
      • 4.2.1.1 Segmentation VCC Table
      • 4.2.1.2 VCC Identification
    • 4.2.2 Submitting Segmentation Data
      • 4.2.2.1 User Data Format
      • 4.2.2.2 Buffer Descriptors
      • 4.2.2.3 Host Linked Segmentation Buffer Descriptors
      • 4.2.2.4 Transmit Queues
      • 4.2.2.5 Partial PDUs
      • 4.2.2.6 Virtual Paths
    • 4.2.3 CPCS-PDU Processing
      • 4.2.3.1 AAL5
      • 4.2.3.2 AAL3/4
      • 4.2.3.3 AAL0
    • 4.2.4 ATM PHY Layer Interface
      • 4.2.4.1 Head-of-Line Flushing (HoLF)
    • 4.2.5 Status Reporting
    • 4.2.6 Virtual FIFO Buffers
  • 4.3 Segmentation Control and Data Structures
    • 4.3.1 Segmentation VCC Table Entry
    • 4.3.2 Data Buffers
    • 4.3.3 Segmentation Buffer Descriptors
    • 4.3.4 Transmit Queues
      • 4.3.4.1 Entry Format
      • 4.3.4.2 Transmit Queue Management
    • 4.3.5 Routing Tags
    • 4.3.6 Segmentation Status Queues
      • 4.3.6.1 Entry Format
      • 4.3.6.2 Status Queue Management
      • 4.3.6.3 Status Queue Overflow
    • 4.3.7 Segmentation Internal SRAM Memory Map
• 5.0 Reassembly Coprocessor
  • 5.1 Overview
  • 5.2 Reassembly Functional Description
    • 5.2.1 Reassembly VCCs
      • 5.2.1.1 Relation to Segmentation VCCs
    • 5.2.2 Channel Lookup
      • 5.2.2.1 Programmable Block Size for VCC Table/ VCI Index Table
      • 5.2.2.2 Setup
      • 5.2.2.3 Operation
      • 5.2.2.4 AAL3/4 Lookup
      • 5.2.2.5 Variable VPI/PORT_ID Lookup (Multi-phy Support)
  • 5.3 CPCS-PDU Processing
    • 5.3.1 AAL5 Processing
      • 5.3.1.1 AAL5 COM Processing
      • 5.3.1.2 AAL5 EOM Processing
      • 5.3.1.3 AAL5 Error Conditions
    • 5.3.2 AAL3/4 Processing
      • 5.3.2.1 AAL3/4 Per-Cell Processing
      • 5.3.2.2 AAL3/4 Additional BOM/SSM Processing
      • 5.3.2.3 AAL3/4 Additional COM Processing
      • 5.3.2.4 AAL3/4 Additional EOM/SSM Processing
      • 5.3.2.5 AAL3/4 MIB Counters
    • 5.3.3 AAL0 Processing
      • 5.3.3.1 Termination Methods
      • 5.3.3.2 AAL0 Error Conditions
    • 5.3.4 ATM Header Processing
    • 5.3.5 BOM Synchronization Signal
      • 5.3.5.1 Prepend Index
  • 5.4 Buffer Management
    • 5.4.1 Host vs. Local Reassembly
    • 5.4.2 Scatter Method
    • 5.4.3 Free Buffer Queues
    • 5.4.4 Linked Data Buffers
    • 5.4.5 Initialization of Buffer Structures
      • 5.4.5.1 Buffer Descriptors
      • 5.4.5.2 Free Buffer Queue Base Table
      • 5.4.5.3 Free Buffer Queue Entries
      • 5.4.5.4 Other Initialization
    • 5.4.6 Buffer Allocation
    • 5.4.7 Error Conditions
    • 5.4.8 Early Packet Discard
      • 5.4.8.1 General Description
      • 5.4.8.2 Frame Relay Packet Discard
      • 5.4.8.3 CLP Packet Discard
      • 5.4.8.4 LANE-LECID Packet Discard�Echo Suppression on Multicast Data Frames
      • 5.4.8.5 DMA FIFO Buffer Full
      • 5.4.8.6 AAL3/4 Early Packet Discard Processing
      • 5.4.8.7 Error Conditions
    • 5.4.9 Hardware PDU Time-Out
      • 5.4.9.1 Reassembly Time-Out Process
      • 5.4.9.2 Halting Time-Out Processing
      • 5.4.9.3 Timer Reset
      • 5.4.9.4 Reassembly Time-Out Condition
      • 5.4.9.5 Time-Out Period Calculation
    • 5.4.10 Virtual FIFO Buffer Mode
      • 5.4.10.1 Setup
      • 5.4.10.2 Operation
      • 5.4.10.3 Errors
    • 5.4.11 Firewall Functions
      • 5.4.11.1 Setup
      • 5.4.11.2 Operation
      • 5.4.11.3 Credit Return
  • 5.5 Global Statistics
  • 5.6 Status Queue Operation
    • 5.6.1 Structure
      • 5.6.1.1 Setup
      • 5.6.1.2 Operation
      • 5.6.1.3 Errors
      • 5.6.1.4 Host Detection of Status Queue Entries
    • 5.6.2 Status Queue Overflow or Full Condition
  • 5.7 Reassembly Control and Data Structures
    • 5.7.1 Channel Lookup Structures
    • 5.7.2 Reassembly VCC Table
      • 5.7.2.1 AAL5, AAL0 and AAL3/4 VCC Table Entries
      • 5.7.2.2 AAL3/4 Head VCC Table Entry
    • 5.7.3 Reassembly Buffer Descriptor Structure
    • 5.7.4 Free Buffer Queues
    • 5.7.5 Reassembly Status Queues
    • 5.7.6 LECID Table
    • 5.7.7 Global Time-Out Table
    • 5.7.8 Reassembly Internal SRAM Memory Map
• 6.0 Traffic Management
  • 6.1 Overview
    • 6.1.1 xBR Cell Scheduler
    • 6.1.2 ABR Flow Control Manager
  • 6.2 xBR Cell Scheduler Functional Description
    • 6.2.1 Scheduling Priority
      • 6.2.1.1 16 Priority Levels + CBR
      • 6.2.1.2 VCC Priority Assignment
    • 6.2.2 Dynamic Schedule Table
      • 6.2.2.1 Overview
      • 6.2.2.2 Schedule Table Slots
      • 6.2.2.3 Schedule Slot Formats without USE_SCH_CTRL Asserted
      • 6.2.2.4 Schedule Slot Formats with USE_SCH_CTRL Asserted
      • 6.2.2.5 Some Scheduling Scenarios
    • 6.2.3 CBR Traffic
      • 6.2.3.1 CBR Rate Selection
      • 6.2.3.2 Available Rates
      • 6.2.3.3 CBR Cell Delay Variation (CDV)
      • 6.2.3.4 CBR Channel Management
    • 6.2.4 VBR Traffic
      • 6.2.4.1 Mapping CN8236 VBR Service Categories to TM 4.1 VBR Service Categories
      • 6.2.4.2 Rate-Shaping vs. Policing
      • 6.2.4.3 Single Leaky Bucket
      • 6.2.4.4 Dual Leaky Bucket
      • 6.2.4.5 CLP-Based Buckets
      • 6.2.4.6 Rate Selection
      • 6.2.4.7 Real-Time VBR and CDV
    • 6.2.5 UBR Traffic
    • 6.2.6 xBR Tunnels (Pipes)
    • 6.2.7 Guaranteed Frame Rate
    • 6.2.8 PCR Control for Priority Queues
  • 6.3 ABR Flow Control Manager
    • 6.3.1 A Brief Overview of TM 4.1
    • 6.3.2 Internal ABR Feedback Control Loop
      • 6.3.2.1 Source Flow Control Feedback
      • 6.3.2.2 Destination Behavior
      • 6.3.2.3 Out-of-Rate Cells
    • 6.3.3 Source and Destination Behaviors
    • 6.3.4 ABR VCC Parameters
    • 6.3.5 ABR Templates
    • 6.3.6 Cell Type Decisions
      • 6.3.6.1 In-rate Cell Streams
      • 6.3.6.2 ABR Cell Decisions
    • 6.3.7 Rate Decisions and Updates
      • 6.3.7.1 ABR Traffic Shaping
      • 6.3.7.2 Rate Adjustment Overview
      • 6.3.7.3 Backward RM Cell Flow Control
      • 6.3.7.4 Forward RM Cell Transmission Decisions
      • 6.3.7.5 ACR Change Notification
      • 6.3.7.6 Rate Adjustment in Turnaround RM Cells
      • 6.3.7.7 Optional Rate Adjustment Due to Use-It-or-Lose-It Behavior
    • 6.3.8 Boundary Conditions and Out-of-Rate RM Cells
      • 6.3.8.1 Calculated Rate Boundaries
      • 6.3.8.2 Out-of-Rate Forward RM Cell Generation
      • 6.3.8.3 Out-of-Rate Backward RM Cells
  • 6.4 GFC Flow Control Manager
    • 6.4.1 A Brief Overview of GFC
    • 6.4.2 The CN8236�s Implementation of GFC
      • 6.4.2.1 Configuring the Link for GFC Operation
  • 6.5 Traffic Management Control and Status Structures
    • 6.5.1 Schedule Table
    • 6.5.2 CBR-Specific Structures
      • 6.5.2.1 CBR Traffic
      • 6.5.2.2 Tunnel Traffic
      • 6.5.2.3 SCH_STATE Fields For CBR
    • 6.5.3 VBR-Specific Structure
      • 6.5.3.1 VBR SCH_STATE
      • 6.5.3.2 VBR1 or VBR2 Schedule State Table
      • 6.5.3.3 Bucket Table for VBR2 and VBRC
    • 6.5.4 GFR-Specific Structures
      • 6.5.4.1 GFR Schedule State Table
      • 6.5.4.2 GFR MCR Limit Bucket Table
    • 6.5.5 ABR-Specific Structures
      • 6.5.5.1 ABR Schedule State Table
    • 6.5.6 ABR Instruction Tables
    • 6.5.7 RS_QUEUE
    • 6.5.8 Scheduler Internal SRAM Registers
• 7.0 OAM Functions
  • 7.1 OAM Overview
    • 7.1.1 OAM Functions Supported
    • 7.1.2 OAM Flows Supported
      • 7.1.2.1 F4 OAM Flow
      • 7.1.2.2 F5 OAM Flow
      • 7.1.2.3 Performance Monitoring (PM)
    • 7.1.3 OAM Cell Format
    • 7.1.4 Local vs. Host Processing of OAM
  • 7.2 Segmentation of OAM Cells
    • 7.2.1 Key OAM-Related Fields for OAM Segmentation
      • 7.2.1.1 Segmentation Buffer Descriptors
      • 7.2.1.2 Low Latency Transmission
      • 7.2.1.3 Segmentation Status Queue
      • 7.2.1.4 F4 Flow
    • 7.2.2 Error Condition During OAM Segmentation
  • 7.3 Reassembly of OAM Cells
    • 7.3.1 Key OAM-Related Fields for OAM Reassembly
      • 7.3.1.1 Reassembly VCC State Table
      • 7.3.1.2 Reassembly Status Queue
      • 7.3.1.3 F4 Flow
    • 7.3.2 OAM Reassembly Operation
    • 7.3.3 Error Conditions During OAM Reassembly
  • 7.4 PM Processing
    • 7.4.1 Initializing PM Operation
    • 7.4.2 Setting Up Channels for PM Operation
    • 7.4.3 PM Operation
      • 7.4.3.1 Generation of Forward Monitoring PM Cells
      • 7.4.3.2 Reassembly of Forward Monitoring PM Cells
      • 7.4.3.3 Reassembly of Backward Reporting PM Cells
      • 7.4.3.4 Turnaround and Segmentation of Backward Reporting PM Cells
      • 7.4.3.5 Turnaround of Backward Reporting PM Cells ONLY
    • 7.4.4 Error Conditions During PM Processing
    • 7.4.5 PASS_OAM Function
  • 7.5 OAM Control and Status Structures
    • 7.5.1 SEG_PM Structure
    • 7.5.2 RSM_PM Table
• 8.0 DMA Coprocessor
  • 8.1 Overview
  • 8.2 DMA Read
  • 8.3 DMA Write
  • 8.4 Misaligned Transfers
  • 8.5 Control Word Transfers
• 9.0 Local Memory Interface
  • 9.1 Overview
  • 9.2 Memory Bank Characteristics
  • 9.3 Memory Size Analysis
• 10.0 Local Processor Interface
  • 10.1 Overview
  • 10.2 Interface Pin Descriptions
  • 10.3 Bus Cycle Descriptions
    • 10.3.1 Single Read Cycle, Zero Wait State Example
    • 10.3.2 Single Read Cycle, Wait States Inserted By Memory Arbitration
    • 10.3.3 Double Read Burst With Processor Wait States
    • 10.3.4 Single Write With One-Wait-State Memory
    • 10.3.5 Quad Write Burst, No Wait States
  • 10.4 Processor Interface Signals
  • 10.5 Local Processor Operating Mode
  • 10.6 Standalone Operation
    • 10.6.1 Microprocessor Interface for Multiple Physical Devices
  • 10.7 System Clocking
  • 10.8 Real-Time Clock Alarm
  • 10.9 CN8236 Reset
• 11.0 PCI Bus Interface
  • 11.1 Overview
  • 11.2 Unimplemented PCI Bus Interface Functions
  • 11.3 PCI Configuration Space
  • 11.4 PCI Bus Master Logic
  • 11.5 Burst FIFO Buffers
  • 11.6 PCI Bus Slave Logic
  • 11.7 Byte Swapping of Control Structures
  • 11.8 Power Management
  • 11.9 Interface Module to Serial EEPROM
    • 11.9.1 EEPROM Format
    • 11.9.2 Loading the EEPROM Data at Reset
    • 11.9.3 Accessing the EEPROM
    • 11.9.4 Using the Subsystem ID Without an EEPROM
  • 11.10 PCI Host Address Map
• 12.0 ATM UTOPIA Interface
  • 12.1 Overview of ATM UTOPIA Interface
  • 12.2 ATM UTOPIA Interface Logic
  • 12.3 ATM Physical I/O Pins
    • 12.3.1 UTOPIA Interface
  • 12.4 UTOPIA Level 2 Interface
    • 12.4.1 Cell Tagging
    • 12.4.2 UTOPIA Configuration Control
    • 12.4.3 UTOPIA Level 2 Multi-Port Operation
  • 12.5 UTOPIA Level 1 Mode Cell Handshake Timing
  • 12.6 UTOPIA Level 1 Mode Octet Handshake Timing
  • 12.7 Slave Level 1 UTOPIA Mode
  • 12.8 Loopback Mode
  • 12.9 Receive Cell Synchronization Logic
  • 12.10 Transmit Cell Synchronization Logic
• 13.0 AALx Interworking
  • 13.1 AALx RSM Operation
  • 13.2 AALx SEG Operation
    • 13.2.1 AALx Network Centric Operation�(EXTERNAL_SCH = 0)
    • 13.2.2 AALx Voice Centric Operation�(EXTERNAL_SCH = 1)
• 14.0 CN8236 Registers
  • 14.1 Control and Status Registers
  • 14.2 System Registers
  • 14.3 Segmentation Registers
  • 14.4 Scheduler Registers
  • 14.5 Reassembly Registers
  • 14.6 Counters and Status Registers
  • 14.7 PCI Bus Interface Registers
• 15.0 SAR Initialization�Example Tables
  • 15.1 Segmentation Initialization
    • 15.1.1 Segmentation Control Registers
    • 15.1.2 Segmentation Internal Memory Control Structures
    • 15.1.3 Segmentation SAR Shared Memory Control Structures
  • 15.2 Scheduler Initialization
    • 15.2.1 Scheduler Control Registers
    • 15.2.2 Scheduler Internal Memory Control Structures
    • 15.2.3 Scheduler SAR Shared Memory Control Structures
  • 15.3 Reassembly Initialization
    • 15.3.1 Reassembly Control Registers
    • 15.3.2 Reassembly Internal Memory Control Structures
    • 15.3.3 Reassembly SAR Shared Memory Control Structures
  • 15.4 General Initialization
    • 15.4.1 General Control Registers
• 16.0 Electrical and Mechanical Specifications
  • 16.1 Timing
    • 16.1.1 PCI Bus Interface Timing
    • 16.1.2 ATM Physical Interface Timing�UTOPIA and Slave UTOPIA
    • 16.1.3 System Clock Timing
    • 16.1.4 CN8236 Memory Interface Timing
    • 16.1.5 PHY Interface Timing (Standalone Mode)
    • 16.1.6 Local Processor Interface Timing
  • 16.2 Absolute Maximum Ratings
  • 16.3 DC Characteristics
  • 16.4 Mechanical Specifications
• Appendix A: Boundary Scan
  • A.1 Instruction Register
  • A.2 BYPASS Register
  • A.3 Boundary Scan Register
  • A.4 Boundary Scan Register Cells
  • A.5 Electrical Characteristics
  • A.6 Boundary Scan Description Language (BSDL) File
• Appendix B: List of Acronyms