Document Outline

• Table of Contents
• List of Figures
• List of Tables
• 1.0 System Description
  • Figure 11. System Block Diagram
  • Figure 12. Detailed System Block Diagram
  • Figure 13. MUSYCC Application Example�Frame Relay Switch
  • 1.1 Pin Descriptions
    • Figure 14. Bt8474 Pinout Configuration
    • Figure 15. Bt8474 Logic Diagram
    • Figure 16. Bt8472 Pinout Configuration
    • Figure 17. Bt8472 Logic Diagram
    • Table 11. I/O Pin Types
    • Table 12. Bt8474/8472 Hardware Signal Definitions (1 of 6)
• 2.0 Host Interface
  • Figure 21. Host Interface Functional Block Diagram
  • 2.1 PCI Interface
    • 2.1.1 PCI Initialization
    • 2.1.2 PCI Bus Operations
    • 2.1.3 PCI Configuration Space
      • Figure 22. Address Lines During Configuration Cycle
      • Table 21. Function 0 Configuration Space
      • Table 22. Function 1 Configuration Space
  • 2.2 PCI Configuration Registers
    • 2.2.1 Function 0 Network Controller�PCI Master and Slave
      • Table 23. Register 0, Address 00h
      • Table 24. Register 1, Address 04h (1 of 2)
      • Table 25. Register 2, Address 08h
      • Table 26. Register 3, Address 0Ch
      • Table 27. Register 4, Address 10h
      • Table 28. Registers 5�14, Addresses 14h�38h
      • Table 29. Register 15, Address 3Ch
    • 2.2.2 Function 1 Expansion Bus Bridge, PCI Slave
      • Table 210. Register 0, Address 00h
      • Table 211. Register 1, Address 04h (1 of 2)
      • Table 212. Register 2, Address 08h
      • Table 213. Register 3, Address 0Ch
      • Table 214. Register 4, Address 10h
      • Table 215. Registers 5 through 14�Addresses 14h through 38h
      • Table 216. Register 15, Address 3Ch
    • 2.2.3 PCI Reset
    • 2.2.4 Host Interface
    • 2.2.5 PCI Bus Parity
    • 2.2.6 PCI Throughput and Latency Considerations
      • 2.2.6.1 PCI Bus Latency
        • Table 217. PCI Latency Example 
• 3.0 Expansion Bus (EBUS)
  • Figure 31. EBUS Functional Block Diagram with Local MPU
  • Figure 32. EBUS Functional Block Diagram without Local MPU
  • 3.1 Operation
    • 3.1.1 Initialization
    • 3.1.2 Address and Data
      • Figure 33. EBUS Address/Data Line Structure
    • 3.1.3 Clock
    • 3.1.4 Interrupt
    • 3.1.5 Address Duration
    • 3.1.6 Data Duration
    • 3.1.7 Bus Access Interval
    • 3.1.8 PCI to EBUS Interaction
    • 3.1.9 Microprocessor Interface
      • Table 31. Intel Protocol Signals
      • Table 32. Motorola Protocol Signal
    • 3.1.10 Arbitration
    • 3.1.11 Connection
      • Figure 34. EBUS Connection, Non-multiplexed Address/Data, 4 Framers, No MPU
      • Figure 35. EBUS Connection, Non-multiplexed Address/Data, 16 Framers, No MPU
      • Figure 36. EBUS Connection, Multiplexed Address/Data, 4 Framers, No MPU
• 4.0 Serial Interface
  • Figure 41. Serial Interface Functional Block Diagram, Channel Group 0
  • 4.1 Serial Port Interface
  • 4.2 Bit Level Processor
  • 4.3 Direct Memory Access Controller
  • 4.4 Interrupt Controller
  • 4.5 Channelized Port Mode
    • Table 41. Channelized Serial Port Modes
    • 4.5.1 Hyperchannels (Nx64)
    • 4.5.2 Subchannels (Nx8)
    • 4.5.3 Frame Synchronization Flywheel
      • Figure 42. Transmit and Receive T1 Mode
      • Figure 43. Transmit and Receive E1 (also 2xE1, 4xE1) Mode
      • Figure 44. Transmit and Receive Nx64 Mode
    • 4.5.4 Change Of Frame Alignment
    • 4.5.5 Out Of Frame
  • 4.6 Serial Port Mapping
    • Figure 45. Serial Port Mapping Options
  • 4.7 Tx and Rx FIFO Buffer Allocation and Management
    • Table 42. Internal Buffer Memory Layout
    • Figure 46. Receive Data Flow
    • Figure 47. Transmit Data Flow
    • 4.7.1 Example Channel BUFFLOC and BUFFLEN Specification
      • Table 43. Example of 32-Channel w/Subchanneling Buffer Allocation (Receive or Transmit)
      • Table 44. Example of 32-Channel w/o Subchanneling Buffer Allocation (Receive or Transmit)
      • Table 45. Example of 16-Channel w/o Subchanneling Buffer Allocation (Receive or Transmit)
    • 4.7.2 Receiving Bit Stream
    • 4.7.3 Transmitting Bit Stream
      • 4.7.3.1 Transmit Data Bit Output Value Determination
        • Figure 48. Transmit Data Bit Output Value Determination
• 5.0 Memory Organization
  • 5.1 Memory Architecture
    • Figure 51. Shared Memory Model Per Channel Group
    • 5.1.1 Register Map Access and Shared Memory Access
      • Table 51. MUSYCC Register Map
      • Table 52. Group Structure Memory Map
    • 5.1.2 Memory Access Illustration
      • Table 53. MUSYCC PCI Function Memory Allocation
      • Table 54. Shared Memory Allocation�Group Descriptors
      • Table 55. Host Assigns Group Base Pointers
  • 5.2 Descriptors
    • 5.2.1 Host Interface Level Descriptors
      • 5.2.1.1 Global Configuration Descriptor
        • Table 56. Global Configuration Descriptor (1 of 2)
      • 5.2.1.2 Dual Address Cycle Base Pointer
        • Table 57. Dual Address Cycle Base Pointer
    • 5.2.2 Channel Group Level Descriptors
      • 5.2.2.1 Group Base Pointer
        • Table 58. Group Base Pointer
      • 5.2.2.2 Service Request
        • Table 59. Service Request Descriptor (1 of 2)
      • 5.2.2.3 Group Configuration Descriptor
        • Table 510. Group Configuration Descriptor (1 of 3)
      • 5.2.2.4 Memory Protection Descriptor
        • Table 511. Memory Protection Descriptor
      • 5.2.2.5 Port Configuration Descriptor
        • Table 512. Port Configuration Descriptor
      • 5.2.2.6 Message Length Descriptor
        • Table 513. Message Length Descriptor
      • 5.2.2.7 Time Slot Map
        • Table 514. Transmit or Receive Time Slot Map
        • Table 515. Time Slot Descriptor
      • 5.2.2.8 Subchannel Map
        • Table 516. Transmit or Receive Subchannel Map
        • Table 517. Subchannel Descriptor
    • 5.2.3 Channel Level Descriptors
      • 5.2.3.1 Channel Configuration Descriptor
        • Table 518. Channel Configuration Descriptor (1 of 3)
    • 5.2.4 Message Level Descriptor
      • Table 519. Message Descriptor
      • 5.2.4.1 Using Message Descriptors
      • 5.2.4.2 Head Pointer
        • Table 520. Head Pointer
      • 5.2.4.3 Message Pointer
        • Table 521. Message Pointer
      • 5.2.4.4 Message Descriptor
      • 5.2.4.5 Buffer Descriptor
        • Table 522. Transmit Buffer Descriptor (1 of 2)
        • Table 523. Receive Buffer Descriptor
      • 5.2.4.6 Buffer Status Descriptor
        • Table 524. Transmit Buffer Status Descriptor
        • Table 525. Receive Buffer Status Descriptor
      • 5.2.4.7 Next Message Pointer
        • Table 526. Next Descriptor Pointer
      • 5.2.4.8 Data Buffer Pointer
        • Table 527. Data Buffer Pointer
      • 5.2.4.9 Message Descriptor Handling
    • 5.2.5 Interrupt Level Descriptors
      • 5.2.5.1 Interrupt Queue Descriptor
        • Table 528. Interrupt Queue Descriptor
        • Table 529. Interrupt Queue Pointer
        • Table 530. Interrupt Queue Length
      • 5.2.5.2 Interrupt Descriptor
        • Table 531. Interrupt Descriptor (1 of 5)
      • 5.2.5.3 Interrupt Status Descriptor
        • Table 532. Interrupt Status Descriptor
    • 5.2.6 Interrupt Handling
      • 5.2.6.1 Initialization
      • 5.2.6.2 Interrupt Descriptor Generation
      • 5.2.6.3 INTA* Signal Line
      • 5.2.6.4 INTB* Signal Line
        • Figure 52. Interrupt Notification To Host
• 6.0 Basic Operation
  • 6.1 Reset
    • 6.1.1 Hard PCI Reset
    • 6.1.2 Soft Chip Reset
    • 6.1.3 Soft Group Reset
    • 6.1.4 Example of Initialization Sequence
  • 6.2 Configuration
    • 6.2.1 PCI Configuration
    • 6.2.2 Global Configuration
    • 6.2.3 Interrupt Queue Configuration
    • 6.2.4 Channel Group(s) Configuration
    • 6.2.5 Service Request Mechanism
    • 6.2.6 MUSYCC Internal Memory
      • 6.2.6.1 Read Operation� Slave Reads
      • 6.2.6.2 Write Operation� Slave Writes
  • 6.3 Channel Operation
    • 6.3.1 Group Structure
    • 6.3.2 Group Base Pointer
      • Table 61. Components of Group Base Pointer
    • 6.3.3 Global Configuration Descriptor
      • Table 62. Components of Global Configuration Descriptor
    • 6.3.4 Interrupt Queue Descriptor
      • Table 63. Components of Interrupt Queue Descriptor
    • 6.3.5 Group Configuration Descriptor
      • Table 64. Components of Group Configuration Descriptor
    • 6.3.6 Memory Protection Descriptor
      • Table 65. Components of Memory Protection Descriptor
    • 6.3.7 Port Configuration Descriptor
      • Table 66. Components of Port Configuration Descriptor
    • 6.3.8 Message Length Descriptor
      • Table 67. Components of Message Length Descriptor
    • 6.3.9 Transmit Time Slot Map�Channel 0
      • Table 68. Components of Transmit Time Slot Map � Channel 0
    • 6.3.10 Transmit Subchannel Map
      • Table 69. Components of Transmit Subchannel Map
    • 6.3.11 Transmit Channel Configuration Descriptor
      • Table 610. Components of Channel Configuration Descriptor
    • 6.3.12 Receive Time Slot Map
    • 6.3.13 Receive Subchannel Map
    • 6.3.14 Receive Channel Configuration Descriptor
    • 6.3.15 Message Lists
    • 6.3.16 Channel Activation
      • 6.3.16.1 Transmit Channel Activation
      • 6.3.16.2 Receive Channel Activation
    • 6.3.17 Channel Deactivation
      • 6.3.17.1 Transmit Channel Deactivation
      • 6.3.17.2 Receive Channel Deactivation
    • 6.3.18 Channel Jump
    • 6.3.19 Frame Alignment
    • 6.3.20 Descriptor Polling
      • Table 611. Polling Frequency Using a Time Slot Counter Method
    • 6.3.21 Repeat Message Transmission
  • 6.4 Protocol Support
    • 6.4.1 Frame Check Sequence
    • 6.4.2 Opening/Closing Flags
    • 6.4.3 Abort Codes
    • 6.4.4 Zero-Bit Insertion/Deletion
    • 6.4.5 Message Configuration Bits
      • 6.4.5.1 Idle Code
      • 6.4.5.2 Inter-message Pad Fill
      • 6.4.5.3 Repeat Message Transmission
    • 6.4.6 Message Configuration Bits Copy Enable/Disable
      • Table 612. Memory Map for Message Configuration Descriptor Table
      • Table 613. Message Configuration Descriptor (1 of 2)
    • 6.4.7 Bit-Level Operation
      • 6.4.7.1 Transmit
      • 6.4.7.2 Receive
    • 6.4.8 HDLC Mode
      • 6.4.8.1 Transmit Events
      • 6.4.8.2 Receive Events
      • 6.4.8.3 Transmit Errors
      • 6.4.8.4 Receive Errors
    • 6.4.9 Transparent Mode
      • 6.4.9.1 Transmit Events
      • 6.4.9.2 Receive Events
      • 6.4.9.3 Transmit Errors
      • 6.4.9.4 Receive Errors
  • 6.5 Self-Servicing Buffers
• 7.0 Electrical and Mechanical Specifications
  • 7.1 Electrical and Environmental Specifications
    • 7.1.1 Absolute Maximum Ratings
      • Table 71. Absolute Maximum Ratings
    • 7.1.2 Recommended Operating Conditions
      • Table 72. Recommended 5 V Operating Conditions
    • 7.1.3 Electrical Characteristics
      • Table 73. Electrical Characteristics for 5 V Operation
  • 7.2 Timing and Switching Specifications
    • 7.2.1 Overview
    • 7.2.2 Host Interface (PCI) Timing and Switching Characteristic
      • Table 74. PCI Interface DC Specifications 
      • Table 75. PCI Clock (PCLK) Waveform Parameters, 5 V Clock
      • Figure 71. PCI Clock (PCLK) Waveform, 5 V Clock
      • Table 76. PCI Reset Parameters
      • Figure 72. PCI Reset Timing
      • Table 77. PCI Input/Output Timing Parameters
      • Table 78. PCI Input/Output Measure Conditions
      • Figure 73. PCI Output Timing Waveform
      • Figure 74. PCI Input Timing Waveform
      • Figure 75. PCI Read Multiple Operation
      • Figure 76. PCI Write Multiple Operation
      • Figure 77. PCI Write Single Operation
    • 7.2.3 Expansion Bus (EBUS) Timing and Switching Characteristic
      • Figure 78. ECLK to PCLK Relationship
      • Table 79. EBUS Reset Parameters
      • Figure 79. EBUS Reset Timing
      • Table 710. EBUS Input/Output Timing Parameters
      • Table 711. EBUS Input/Output Measure Conditions
      • Figure 710. EBUS Output Timing Waveform
      • Figure 711. EBUS Input Timing Waveform
    • 7.2.4 EBUS Arbitration Timing
      • Figure 712. EBUS Write/Read Transactions, Intel-Style
      • Figure 713. EBUS Write/Read Transactions, Motorola-Style
    • 7.2.5 Serial Interface Timing and Switching Characteristics
      • Table 712. Serial Interface Clock (RCLK, TCLK) Parameters
      • Figure 714. Serial Interface Clock (RCLK,TCLK) Waveform
      • Table 713. Serial Interface Input/Output Timing Parameters
      • Table 714. Serial Interface Input/Output Measure Conditions
      • Figure 715. Serial Interface Data Input Waveform
      • Figure 716. Serial Interface Data Delay Output Waveform
    • 7.2.6 Test and Diagnostic Interface Timing
      • Table 715. Test and Diagnostic Interface Timing Requirements
      • Table 716. Test and Diagnostic Interface Switching Characteristics
      • Figure 717. JTAG Interface Timing
    • 7.2.7 Package Thermal Specification
      • Table 717. MUSYCC 160-Pin PQFP Package Thermal Resistance Characteristics
    • 7.2.8 Mechanical Specifications
      • Figure 718. 160-Pin PQFP Package Mechanical Drawing
  • 7.3 Revision History
    • Table 718. Bt8474/2 Datasheet Revisions
• 8.0 Terms, Definitions, and Conventions
  • 8.1 Applicable Specifications
  • 8.2 Numeric Notation
    • Table 81. Number Representation
  • 8.3 Bit Stream Transmission Convention
    • Table 82. Digitized Voice Transmission Convention
    • Table 83. Digital Data Transmission Convention
    • Table 84. MUSYCC Byte Transmission Convention
  • 8.4 Bit Stream Storage Convention
    • Table 85. Little-Endian Storage Convention (Intel-style)
    • Table 86. Big-Endian Storage Convention (Motorola-style)
  • 8.5 Acronyms
  • 8.6 Definitions
• Sales Offices