2001, 2002,
Mindspeed TechnologiesTM, a Conexant business
All Rights Reserved.
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omissions in these materials. Mindspeed may make changes to specifications and product descriptions at any time, without notice. Mindspeed
makes no commitment to update the information and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future
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For additional disclaimer information, please consult Mindspeed Technologies Legal Information posted at
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which is
incorporated by reference.
28229-DSH-001-B
Mindspeed Technologies
TM
Ordering Information
Revision History
Model Number
Manufacturing Part
Number
Product
Revision
Package
Operating Temperature
CX28224
28224-14
D
256-pin, 17 mm BGA
40
C to 85
C
CX28225
28225-14
D
256-pin, 17 mm BGA
40
C to 85
C
CX28229
28229-14
D
256-pin, 17 mm BGA
40
C to 85
C
Revision
Level
Date
Description
A
Preliminary
July 2001
Preliminary A version. Note that this document was
also released as a preliminary version under the
document numbers 101265P1 and 101265P2.
B
Preliminary
September 2001
Preliminary B version.
C
Preliminary
September 2001
Removed all references to PLCP and updated some of
the bit descriptions.
D
Preliminary
April 2002
Restructured and enhanced document to include more
IMA related information.
E
Preliminary
May 2002
Updated Ordering Information and a few register
descriptions to reflect the CX28229-13 part.
F
Preliminary
September 2002
Updated to reflect the -14 part. Section 8, Electrical
and Mechanical Specifications, improved and noted
with change bars.
A
Released
January 2003
Revised document number to reflect new numbering
system: new document number is 28229-DSH-001-B.
Removed Prelimary document designations. Replaced
hysteresis references with TTL levels in
Table 8-16
.
28229-DSH-001-B
Mindspeed Technologies
TM
iii
CX28224/5/9
Inverse Multiplexing for ATM (IMA) Family
The CX2822x family of devices provides system designers with a complete integrated
IMA solution for up to 32 ports. All devices include a Transmission Convergence
block to perform cell delineation, on-board RAM to meet ATM forum requirements
for differential delay compensation and a dual mode (UTOPIA or Serial) PHY layer
interface.
Source code for all required software functions is available from Mindspeed. Since
all processing intensive functions are performed in hardware, they require only
minimal overhead from the system processor.
The TC block is capable of bit level cell delineation, which allows for direct connection
DSL serial data streams without a frame sync pulse. Individual ports can be operated
in a 'pass thru' mode without the IMA overhead.
The CX28229 provides direct connection to 8 serial links or can be expanded to a 32
port IMA using the PHY side UTOPIA bus and external TC devices such as the
RS8228. In addition, an external memory bus allows the differential delay memory to
access up to 2 Mbytes of external RAM.
Functional Block Diagram
PHY layer
UTOPIA
2 interface
IMA
Engine
Line interface 0
Line interface 1
Line interface 2
Line interface 3
Line interface 4
Line interface 5
Line interface 6
Line interface 7
cell processor
cell processor
cell processor
cell processor
cell processor
cell processor
cell processor
cell processor
Contr
o
l
Regis
t
er
s
IMA clocks
IMA_Sy
s
C
lk
IMA_RefClk
TC Status
Registers
TC Control
Registers
Micro interface
TC
Counters
TX
FIFO
RX
FIFO
ATM layer
UTOPIA
2 interface
TX
FIFO
RX
FIFO
Micro
Clocks
Mic
r
oClk
8 KHz
I
n
O
neSec
IO
Status
Regis
t
er
s
JTAG
ATM
LAYER UTOPIA INTERFACE PINS
Ph
y SID
E
IN
TER
F
AC
E PIN
S
Internal
256Kx8
SRAM
External Memory Interface
extmemsel pin
Differential Delay
memory interface
Ph
yIn
t
FcSe
l Pin
Phy
I
ntF
c
Sel pin tied high
Phy
I
ntF
c
Sel pin
tied low
TC
BL
O
C
K U
T
O
P
IA IN
TER
F
AC
E
AT
Mmux
[7,6] =
10 an
d
Phy
I
ntF
c
Sel pin
=
high
AT
Mmux
[7,6] =
01
AT
Mmux
[
7,6] =
10
low
high
AT
Mmux
[7,6] =
01 an
d
Phy
I
ntF
c
Sel pin
=
Low
1
0
Cl
oc
k
inter
f
ac
e
OneSec
Rx Block
Tx Block
IMA Block
TC Block
CX28229
TxTRL[0]
TxTRL[1]
Distinguishing Features
!
Complete IMA solution in a single package
"
2 port, CX28224, 17mm BGA
"
4 port, CX28225, 17mm BGA
"
8/32 port, CX28229, 17mm BGA
!
Field tested software available
!
Supports up to 32 ports using external TC
PHYs
!
Up to 16 IMA groups
!
Supports the IMA standard requirements
for 25 ms differential delay with 256K
Internal memory
!
Memory expandable to 2 M bytes via
external bus (CX28229 only)
!
UTOPIA level 2 interfaces
!
Glueless interface to Mindspeed Framers
!
Octet or Bit level cell delineation
!
Variable link data rates (64K3.072 Mb/s)
28229-DSH-001-B
Mindspeed Technologies
TM
iv
IMA Features
!
Field proven design
!
All software available
!
Supports variable link data rates (64K
3.072 Mb/s)
!
Internal memory
!
Connects directly to the Mindspeed
SARs for inexpensive CPE solutions
!
CX28224 2 ports
!
CX28225 4 ports
!
CX28229 32 ports
"
Memory expandable to 2 M bytes via
external bus
"
Up to 16 independent groups (using
external PHYs):
Each group can have up to 8 links.
!
Supports IMA versions 1.0 and 1.1
!
Fractional T1/E1
Cell Delineation Section
!
Supports ATM cell interface for:
"
Circuit-based physical layer
"
Cell-based physical layer
!
Performs single-bit HEC correction and
single- or multiple-bit detection
!
Inserts headers and generates HEC
!
Direct connection to external
Mindspeed components for:
"
T1/E1
"
xDSL
"
General purpose mode
!
Byte-level or bit-level cell delineation
Control and Status
Microprocessor Interface
!
Asynchronous SRAM-like interface
mode
!
Synchronous, glueless Bt8233/RS8234
SAR interface mode
!
8-bit data bus
!
Open-drain interrupt output
!
Open-drain ready output
!
833 MHz operation
!
All control registers are read/write
UTOPIA Interfaces
!
UTOPIA Level 2 Interface to ATM Layer:
"
8/16 bit operation
"
50 MHz
!
PHY-side UTOPIA Interface:
"
8-bit UTOPIA Level 2
"
Supports 32 ports via dual CLAV
and Enable lines
Counters/Status Register Section
!
Summary interrupt indications
!
Configuration of interrupt enables
!
One-second counter latching
!
Counters for:
"
LOCD events
"
Corrected HEC errors
"
Uncorrected HEC errors
"
Transmitted cells
"
Matching received cells
"
Non-matching received cells
28229-DSH-001-B
Mindspeed Technologies
TM
v
Contents
Figures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xi
Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xiii
1
Introduction to IMA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1
1.1
Introduction To Inverse Multiplexing for ATM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-2
1.1.1 IMA Framing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-4
1.1.2 IMA Control Protocol Cells . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-5
1.1.3 Link State Machine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-8
1.1.4 Transmit Clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-8
1.1.5 Differential Delay. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-9
1.2
Software Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-10
1.2.1 Software Subsystems . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-12
1.2.2 Configuration (CF) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-12
1.2.3 Diagnostics (DG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-12
1.2.4 Failure Monitoring (FM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-12
1.2.5 Performance Monitoring (PM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-13
1.2.6 Group State Machine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-13
2
CX2822x Hardware Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1
2.1
Logic Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1
2.2
Pin Diagram and Definitions (UTOPIA-to-UTOPIA Configuration) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3
2.3
Pin Diagram and Definitions (UTOPIA-to-Serial Configuration) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-18
2.4
Stand Alone Cell Delineation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-34
2.5
Source Loopback (UTOPIA-to-Serial Configuration Only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-35
2.6
Far-End Line Loopback (Serial Configuration Only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-36
2.7
Application Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-37
2.8
Reference Designs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-37
3
IMA Clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1
3.1
Common Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-4
3.1.1 T1/E1 Using Internal Serial Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-4
3.1.1.1 Using IMA_SysClk as the Transmit Clock. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-4
3.1.1.2 Using IMA_RefClk as the Transmit Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-6
3.1.2 DSL/T1/E1 Using UTOPIA-to-UTOPIA Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-8
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