Document Outline

• Contents
  • Figures
• Tables
• 1.0 Pin Descriptions
  • Figure 1-1. CX28380 Pinout Diagram
  • Figure 1-2. CX28380 Logic Diagram (Host Mode)
  • Figure 1-3. CX28380 Logic Diagram (Hardware Mode)
  • Table 1-1. Hardware Signal Definitions (1 of 6)
• 2.0 Circuit Description
  • 2.1 Overview
    • Figure 2-1. Detailed Block Diagram
  • 2.2 Configuration and Control
    • 2.2.1 Hardware Mode
    • 2.2.2 Host Mode
    • 2.2.3 Host Serial Control Interface
      • Figure 2-2. Host Serial Port Signals
    • 2.2.4 Reset
      • 2.2.4.1 Power-on Reset
      • 2.2.4.2 Hard Reset
      • 2.2.4.3 Soft Reset
  • 2.3 Receiver
    • 2.3.1 Receive Termination
      • Figure 2-3. Receiver Termination Network
      • Figure 2-4. Receiver Signals
    • 2.3.2 Data Recovery
      • 2.3.2.1 Raw Receive Mode
        • Figure 2-5. Raw Mode Receiver Signals
      • 2.3.2.2 Sensitivity
        • Table 2-1. Line Compatible Modes
      • 2.3.2.3 Bridge Mode
      • 2.3.2.4 Loss of Signal Detectors
    • 2.3.3 Clock Recovery
      • 2.3.3.1 Phase Lock Loop
      • 2.3.3.2 Jitter Tolerance
    • 2.3.4 Receive Jitter Attenuator
    • 2.3.5 RZCS Decoder
    • 2.3.6 Receive Digital Interface
      • 2.3.6.1 Bipolar Mode
      • 2.3.6.2 Unipolar Mode
  • 2.4 Transmitter
    • Figure 2-6. Transmitter Signals
    • 2.4.1 Transmit Digital Interface
      • 2.4.1.1 Bipolar Mode
      • 2.4.1.2 Unipolar Mode
    • 2.4.2 TZCS Encoder
    • 2.4.3 Transmit Jitter Attenuator
    • 2.4.4 All 1s AIS Generator
      • Table 2-2. Transmitter Operating Modes
    • 2.4.5 Pulse Shaper
      • Table 2-3. Transmit Pulse Configurations
      • Figure 2-7. Transmit Pulse Shape
    • 2.4.6 Driver
      • 2.4.6.1 Transmit Termination Options
        • Figure 2-8. Transmit Termination Components
        • Table 2-4. Transmit Termination Option A
        • Table 2-5. Transmit Termination Option B
        • Table 2-6. Transmit Termination Option C
        • Table 2-7. Transmit Termination Option D
        • Table 2-8. Transmit Termination Option E
      • 2.4.6.2 Output Disable
    • 2.4.7 Transmitter Output Monitoring
      • 2.4.7.1 Short Circuit Detect
      • 2.4.7.2 Driver Performance Monitor
  • 2.5 Loopbacks
    • Table 2-9. Loopback Control Pins
    • 2.5.1 Local Analog Loopback
    • 2.5.2 Local Digital Loopback
    • 2.5.3 Remote Line Loopback
  • 2.6 Jitter Attenuator
    • Figure 2-9. Receiver Input Jitter Tolerance
    • Figure 2-10. Typical JAT Transfer Characteristics with Various JAT Sizes
  • 2.7 Clock Rate Adapter
    • Figure 2-11. CLAD Block Diagram
    • 2.7.1 Inputs
    • 2.7.2 Outputs
      • Table 2-10. CLAD Outputs and Frequencies
    • 2.7.3 Configuration Options
      • Table 2-11. CLAD Reference Frequencies and Configuration Examples (1 of 2)
      • Table 2-12. Sample Alternate Configuration
  • 2.8 Test Access Port (JTAG)
    • 2.8.1 Instructions
      • Table 2-13. JTAG Instructions
    • 2.8.2 Device Identification Register
      • Table 2-14. Device Identification JTAG Register
• 3.0 Registers
  • 3.1 Address Map
    • Table 3-1. Address Map
  • 3.2 Global Control and Status Registers
    • 00�Device Identification (DID)
    • 01�Global Configuration (GCR)
    • 02�CLAD Configuration (CLAD_CR)
    • 03�CLAD Frequency Select (CSEL)
    • 04�CLAD Phase Detector Scale Factor (CPHASE)
    • 05�CLAD Test (CTEST)
    • 06�CLAD Status (CSTAT)
    • 07�(FREG)
    • 08�(TESTA1)
    • 09�(TESTA2)
    • 0A�(FUSE_CH1)
    • 0B�(FUSE_CH2)
    • 0C�(FUSE_CH3)
    • 0D�(FUSE_CH4)
    • 0E�(FUSE_RES)
    • 0F�(TESTD)
  • 3.3 Per Channel Registers
    • 10, 20, 30, 40�Jitter Attenuator Configuration (JAT_CR)
    • 11, 21, 31, 41�Receiver Configuration (RLIU_CR)
    • 12, 22, 32, 42�Transmitter Configuration (TLIU_CR)
    • 13, 23, 33, 43�LIU Control (LIU_CTL)
    • 15, 25, 35, 45�Alarm Status (ALARM)
    • 16, 26, 36, 46�Interrupt Status Register (ISR)
    • 17, 27, 37, 47�Interrupt Enable Register (IER)
  • 3.4 Transmitter Shape Registers
    • 18 - 1F�Transmit PULSE Shape CONFIGURATION (SHAPE1)[0�7]
    • 28 - 2F�Transmit PULSE Shape CONFIGURATION (SHAPE2)[0�7]
    • 38 - 3F�Transmit PULSE Shape CONFIGURATION (SHAPE3)[0�7]
    • 48 - 4F�Transmit PULSE Shape CONFIGURATION (SHAPE4)[0�7]
    • 50�(TESTA3)
    • 51�(TESTA4)
• 4.0 Electrical/Mechanical Specifications
  • 4.1 Absolute Maximum Ratings
    • Table 4-1. Absolute Maximum Ratings
  • 4.2 Recommended Operating Conditions
    • Table 4-2. Recommended Operating Conditions
    • Table 4-3. Power Dissipation 
    • Table 4-4. Thermal Data
  • 4.3 DC Characteristics
    • Table 4-5. DC Characteristics 
  • 4.4 Performance Characteristics
    • Table 4-6. Performance Characteristics 
  • 4.5 AC Characteristics
    • Table 4-7. XOE Timing Parameters
    • Figure 4-1. XOE Timing Diagram
    • Table 4-8. JATERR Timing Diagram
    • Figure 4-2. JATERR Timing Diagram
    • Table 4-9. RESET Timing Parameters
    • Figure 4-3. RESET Timing Diagram 1
    • Figure 4-4. RESET Timing Diagram 2
    • Table 4-10. RLOS Timing Parameters
    • Figure 4-5. RLOS Timing Diagram
    • Table 4-11. CLAD Timing Parameters
    • Figure 4-6. CLAD Timing Diagram
    • Table 4-12. Receiver Signals Timing Parameters
    • Figure 4-7. Receiver Signals Timing Diagram
    • Table 4-13. Transmitter Signals Timing Parameters
    • Figure 4-8. Transmitter Signals Timing Diagram
    • Table 4-14. Host Serial Port Timing Parameters 
    • Figure 4-9. Host Serial Port Timing Diagram
    • Figure 4-10. Host Serial Port Write Timing
    • Figure 4-11. Host Serial Port Read Timing
    • Figure 4-12. Host Serial Port Read/Write Cycle Early Termination
    • Table 4-15. JTAG Interface Timing Parameters
    • Figure 4-13. JTAG Interface Timing Diagram
  • 4.6 Packaging
    • Figure 4-14. 128-Pin MQFP Mechanical Drawing
• Appendix A: Applicable Standards
  • Table A-1. Applicable Standards (1 of 2)
• Appendix B: External Component Specifications
  • Table B-1. Transformer Specifications
  • Table B-2. REFCKI (10 MHz) Crystal Oscillator Specifications
• Appendix C: Application
  • Figure C-1. Minimum Hardware Configuration
  • Table C-1. CX28380-16P/CX28380-17P Typical Register Settings for T1
  • Table C-2. CX28380-16P/CX28380-17P Typical Register settings for E1-120
  • Table C-3. CX28380 Device Identification For Different Device Revisions
• Appendix D: Acronym List