2001, 2002,
Mindspeed TechnologiesTM, a Conexant business
All Rights Reserved.
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500052D
Mindspeed Technologies
TM
Ordering Information
Revision History
Model Number
Package
Operating Temperature
CX28500EBG
35 mm TBGA
4085
C
Revision
Level
Date
Description
A
--
July 2001
Created.
B
--
February 2002
Updated to Revision B.
C
--
July 2002
Updated to Revision C.
D
--
November 2002
Updated to Revision D.
500052D
Mindspeed Technologies
TM
iii
CX28500
Multichannel Synchronous Communications Controller
The CX28500 is an advanced Multichannel Synchronous Communications Controller.
It formats and deformats up to 1024 High-level Data Link Control (HDLC) channels in
a CMOS integrated circuit. CX28500 operates at Layer 2 of the Open Systems
Interconnection (OSI) protocol reference model. It provides a comprehensive, high-
density solution for processing of HDLC channels for internetworking applications
such as Frame Relay, Integrated Services Digital Network (ISDN), D-channel
signaling, X.25, Signaling System 7 (SS7), Data Exchange Interface (DXI), Inter
System Link Protocol (ISLP), and LAN/WAN data transport. Under minimal Host
supervision, CX28500 manages table-like data structures of channel data buffers in
Host memory by performing Direct Memory Access (DMA) of up to 1024 channels.
CX28500 interfaces to 32 independent serial data streams, such as T1/E1 signals. It
then transfers data across the popular 32-bit or 64-bit Peripheral Component
Interface (PCI) bus to system memory at a rate up to 66 MHz. The CX28500 has an
aggregate data throughput of 390 Mbps. Each serial interface can be operated up to
13.0 MHz. Six Serial Interfaces can be operated at rates up to 52 MHz. Logical
channels can be mapped as any combination of Digital Signal Level 0 (DS0) time slots
to support ISDN hyperchannels (N x 64 Kbps). Additionally, logical channels can
operate in subchanneling mode (N x 8 Kbps) by mapping a combination of DS0 time
slots and/or the individual bits of a DS0 time slot (8 bits). For example, a 56 Kbps
channel can be achieved by mapping 7 bits out of 8 possible bits in a time slot (7 x 8
Kbps = 56 Kbps). CX28500 also includes a 32-bit expansion port for bridging the PCI
bus to local microprocessors or peripherals. A Joint Test Action Group (JTAG) port
enables boundary-scan testing to replace bed-of-nails board testing.
Functional Block Diagram
HOST
Interface
(PCI)
Device
Configuration
Registers
PCI
Interface
PCI
Configuration
Space
(Function 0)
RxDMA
and
TxDMA
Serial
Interface
Unit
(SIU)
Rx Line
Processor
RSLP
Tx Line
Processor
TSLP
TSBUS
or
PCM
Highway
EXP BUS
JTAG
Test
Access
31
0
PCI B
U
S
Local BUS
Ph
ysical Interf
ace
500052_020
Distinguishing Features
1024-channel HDLC controller
OSI Layer 2 protocol support
General purpose HDLC (ISO 3309)
X.25 (LAPB)
Frame relay (LAPF/ANSI T1.618)
ISDN D-channel (LAPD/Q.921)
ISLP support
32 Independent serial interfaces, which
support:
Mixed Data Rates (combination of T1/
E1/T3/E3, etc.) as long as they do not
exceed each port's respective
bandwidth limitation and the overall
device bandwidth of 390 Mbps per
direction
32 T1/E1 data streams
6 HSSI interfaces (52 Mbps)
DC to 13.0 Mbps serial interfaces
32 x 8.192 MHz TDM busses
Configurable logical channels
Standard DS0 (56, 64 Kbps)
Subchanneling (N x 8 Kbps)
Hyperchannel (N x 64 Kbps)
Unchannelized mode
Per-channel protocol mode selection
Non-FCS mode
16-bit FCS mode
32-bit FCS mode
Transparent mode (unformatted data)
Hardware Flow Control (CTS)
Selectable Endian configuration on data
Per-channel DMA buffer management
Table-like data structures
Variable size transmit/receive FIFO
Per-channel message length check
Select no length checking
Select from three 14-bit registers to
compare message length
Direct PCI bus interface
32/64-bit, 33/66 MHz operation
Bus master and slave operation
PCI Version 2.1
Host back-to-back transaction over the
PCI
HSSI interfaces (52 Mbps)
Local expansion bus interface (EBUS)
32-bit multiplexed address/data bus
TSBUS
Support of 64-bit ECC host memory
Low power, 3.3 V CMOS operation
JTAG boundary scan access port
35 mm x 35 mm 580-pin BGA
500052D
Mindspeed Technologies
TM
v
Contents
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . v
Figures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xiii
Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xv
1
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1
1.1
CX28500's Operational Modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-2
1.2
CX28500 Serial Port Throughput Limits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-3
1.3
CX28500's Bus Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-6
1.3.1 PCI--Peripheral Components Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-6
1.3.2 EBUS--Local Expansion Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-6
1.3.3 TSBUS--Time Slot Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-6
1.4
CX28500 Layering Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-7
1.5
CX28500's Applications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-8
1.6
CX28500 Applications Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-9
1.6.1 T1/T3 WAN Access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-9
1.6.2 T3/E3 Frame Relay Switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-10
1.6.3 128 Port DSL Access Concentrator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-12
1.6.4 SONET/SDH Mapper . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-13
1.6.5 Line Card SONET/ATM SAR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-14
1.7
Feature Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-15
1.8
System Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-18
1.9
Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-20
1.10
Receive Data Path . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-21
1.11
Transmit Data Path . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-22
1.12
Pin Configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-23
1.13
CX28500 Hardware Signals Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-30
2
Internal Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1
2.1
Serial Interface Unit (SIU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2
2.2
Serial Line Processor (SLP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3
2.3
Direct Memory Access Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-4
2.3.1 General Feature List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-4
2.4
Interrupt Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-5
3
Host Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1
3.1
PCI Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-2
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