Document Outline

• OptiPHYTM - M622 STS-12/4x STS-3 SONET/SDH Multiplexer
• Functional Block Diagram
• List of Figures
• List of Tables
• 1.0 Product Description
  • 1.1 CX29610 Features
    • 1.1.1 General System Features
    • 1.1.2 Transmitter Features
    • 1.1.3 Receiver Features
      • 1.1.3.1 Alarm/Error Detection and Performance Monitoring Features
        • Table 11. Reported Path RDI
    • 1.1.4 Diagnostic Features
  • 1.2 Definitions
    • Table 12. Level Hierarchies within SONET and SDH
  • 1.3 Conventions
  • 1.4 Terminology
    • Table 13. SONET/SDH Terminology
  • 1.5 Logic Diagram
    • Figure 11. CX29610 Logic Diagram
    • Figure 12. CX29610 Logic Diagram
    • Figure 13. CX29610 Logic Diagram
    • Table 14. Pin Definitions (1 of 16)
  • 1.6 Block Diagram and Descriptions
    • Figure 14. STS-12 Mode Data Flow Diagram
    • Figure 15. 4xSTS-3 Mode Data Flow Diagram
    • Figure 16. Framer Block Diagram
• 2.0 Functional Description
  • Figure 21. CX29610 Block Diagram
  • 2.1 Line Interface
    • Table 21. PECL Input Logic Table
    • Table 22. PECL output Logic Table
    • 2.1.1 Transmit and Receive PLL Filter Networks
      • Figure 22. PLL Bias Network
    • 2.1.2 Signal Detect Interface
      • Figure 23. Single-ended PECL Diagram
  • 2.2 Clock Circuits
    • Figure 24. Functional Block Diagram
    • Figure 25. Receive Clock Generation and Data Path
    • Figure 26. Transmit Clock Generation and Data Path
    • Table 23. Transmit/Receive Default Clock Configuration
    • Table 24. TxClkSel[1:0] Control Bits
    • Figure 27. Bellcore GR-253-CORE Jitter Specifications
    • Table 25. SONET Category II Jitter Tolerance Mask
    • Table 26. Category II Jitter Transfer Mask
    • Table 27. CX29610 Jitter Specification
    • 2.2.1 Loss of Lock
  • 2.3 Device Configuration and Setup
    • Table 28. Valid Framing Modes for the CX29610
    • Figure 28. Default Clock and Data Receive Path
    • Figure 29. Default Clock and Data Transmit Path
    • Table 29. Transmit/Receive Configuration: OC-12 Mode, Internal CDR and Transmit Clock Synthesis ...
  • 2.4 SONET/SDH Framer and Overhead Processor
    • Table 210. Valid Framing Modes for the CX29610
    • Table 211. Default J0/Z0 Transmitted Values
    • Figure 210. AU-3 to TUG-2
    • Figure 211. AU-3 Basic Frame (STM-4 to 4 x AUG to 3 x AU-3 Mapping)
    • Figure 212. TUG-2 to TUG-3 to AU-4
    • Figure 213. STM-4 to TUG-2
    • Figure 214. STS-4�STS-12
    • Figure 215. TU-3 to TUG-3 to AU-4
    • Figure 216. TU-3 Basic Frame (STM-4 to 4 x AUG to AU-4 to VC-4 to 3 x TU-3 Mapping)
    • Table 212. SONET Overhead Byte Definitions and Values (1 of 2)
    • 2.4.1 Loss of Signal
    • 2.4.2 Section Overhead
      • Table 213. Section Overhead Transmit and Receive Functions
      • 2.4.2.1 A1, A2 Severely Errored Frames (SEF)
      • 2.4.2.2 Loss of Frame
      • 2.4.2.3 J0, Z0
        • Figure 217. J0 Buffer Behavior
      • 2.4.2.4 B1
      • 2.4.2.5 E1
      • 2.4.2.6 F1
      • 2.4.2.7 D1-D3
        • Table 214. DCC Transmit Values
    • 2.4.3 Line Overhead
      • Table 215. Line Overhead Transmit and Receive Functions
      • 2.4.3.1 H1 and H2
      • 2.4.3.2 H3
      • 2.4.3.3 Loss of Pointer
      • 2.4.3.4 B2
      • 2.4.3.5 APS Threshold
        • Table 216. Bit Error Rate Analysis for STS-3
      • 2.4.3.6 BER
      • 2.4.3.7 Minimum Observation
      • 2.4.3.8 Frames Observed
      • 2.4.3.9 Actual Bits Observed
      • 2.4.3.10 Error Threshold
      • 2.4.3.11 Threshold Detect Time
      • 2.4.3.12 APS Switch Requirement
        • Table 217. Window and Threshold requirements for STS-12
      • 2.4.3.13 K1, K2
      • 2.4.3.14 Line RDI/AIS Detect
        • Table 218. K2 Indications
      • 2.4.3.15 D4-D12
      • 2.4.3.16 S1
        • Table 219. S1 Byte Description
      • 2.4.3.17 Z1
      • 2.4.3.18 Z2
      • 2.4.3.19 M1
      • 2.4.3.20 E2
    • 2.4.4 Path Overhead
      • Table 220. Path Overhead Transmit and Receive Functions
      • 2.4.4.1 J1
      • 2.4.4.2 B3
      • 2.4.4.3 C2
      • 2.4.4.4 G1
        • Table 221. G1 bit Interpretation
        • Table 222. G1 bit Indications
      • 2.4.4.5 F2
      • 2.4.4.6 H4
      • 2.4.4.7 F3 (Z3)
      • 2.4.4.8 K3 (Z4)
      • 2.4.4.9 N1 (Z5)
    • 2.4.5 Custom Extensions
    • 2.4.6 SONET Frame Scrambler
  • 2.5 Microprocessor Interface
    • 2.5.1 Interface Modes
    • 2.5.2 Status and Control
    • 2.5.3 Counters
    • 2.5.4 One-second Latching
    • 2.5.5 Interrupts
      • Table 223. Receiver Registers
      • Figure 218. Interrupt Hierarchy
      • 2.5.5.1 Interrupt Suppression During Error Conditions
        • Table 224. Interrupt Suppression during Error Conditions
  • 2.6 SI-Bus Interface
    • 2.6.1 Description
    • 2.6.2 Signals
      • Table 225. Signal Definition for Transmit Interface
      • Table 226. Signal Definition for Receive Interface
    • 2.6.3 Operation
      • 2.6.3.1 Clock Operation
        • Figure 219. SI-Bus Clock Relationships
      • 2.6.3.2 Basic Operation
        • Figure 220. Unit of Transfer (3 Interleaved STS-1 Frames)
        • Figure 221. SI-Bus Mode Interface to CN29503
        • Figure 222. Mode Transmit Signal Relationship
        • Figure 223. Mode Receive Signal Relationship
  • 2.7 TTL/PECL Interface
    • Figure 224. Single-ended PECL Diagram
    • 2.7.1 PECL Bias Network
      • Figure 225. PECL Bias Network
  • 2.8 Loopback Modes
    • 2.8.1 Line Loopback
      • Figure 226. Line Loopback Diagram
    • 2.8.2 Source Loopback
      • Figure 227. Source Loopback Diagram
      • Figure 228. Line Loopback�Receive
      • Figure 229. Line Loopback�Transmit
      • Figure 230. Local Source Loopback�Receive
      • Figure 231. Local Source Loopback�Transmit
      • Figure 232. Source Loopback�Receive
      • Figure 233. Source Loopback�Transmit
• 3.0 Applications
  • 3.1 OC-12/STM-4 Path Termination for HDLC Application
    • Figure 31. OC-12/STM-4 Channeled to DS1/E1 Application
  • 3.2 OC-3/STM-1 Path Termination for HDLC Application
    • Figure 32. OC-3/STM-1 Full DS0/E0 Channelization Application
• 4.0 Registers
  • 4.1 Memory Map
    • Table 4-1. Port Register Address Sections
    • Section and Path Buffers
    • Register Map
      • Table 4-2. Processor Memory Map (1 of 12)
    • APSINT (APS/Pointer Interrupt Indication Status Register)
    • APSTHRESH (APS Threshold Control Register)
    • B1CNTH (Section BIP Error Counter [High Byte])
    • B1CNTL (Section BIP Error Counter [Low Byte])
    • B2CNTH (Line BIP Error Counter [High Byte])
    • B2CNTL (Line BIP Error Counter [Low Byte])
    • B2CNTM (Line BIP Error Counter [Mid Byte])
    • B3CNTH (Path BIP Error Counter [High Byte])
    • B3CNTL (Path BIP Error Counter [Low Byte])
    • BUSMODE (SI-Bus Mode Control Register)
    • CLKREC (Clock Recovery/Loopback Control Register)
    • CLKRECPD (Clock Recovery/Power Down Control Register)
    • CNTMODE (Counter Mode Control Register)
    • DOWNALM (Downstream Alarm Control Register)
    • ENAPS (APS Interrupt Mask Control Register)
    • ENLIN (Receive Line Interrupt Mask Control Register)
    • ENPNTR (Pointer Interrupt Mask Control Register)
    • ENPORTINT (Summary Port Interrupt Mask Control Register)
    • ENPTH (Receive Path Interrupt Mask Control Register)
    • ENSEC (Receive Section Interrupt Mask Control Register)
    • ENSUMINT (Summary Interrupt Mask Control Register)
    • ERRINS (Error Insertion Control Register)
    • ERRPAT (Error Pattern Control Register)
    • GEN (General Control Register)
    • LININT (Receive Line Interrupt Indication Status Register)
    • NDFCNT (New Data Flag Counter)
    • NJCNTH (Negative Pointer Justification Counter [High Byte])
    • NJCNTL (Negative Pointer Justification Counter [Low Byte])
    • PJCNTH (Positive Pointer Justification Counter [High Byte])
    • PJCNTL (Positive Pointer Justification Counter [Low Byte])
    • PNTRINT (Pointer Interrupt Indication Status Register)
    • PNTRSTAT (Receive H1/H2 Pointer Action Status Register)
    • PORTINT (Summary Port Interrupt Indication Register)
    • PORTMAP (Port Mapping Control Register)
    • PRBS (Pseudo-Random Bit Sequence Control Register)
    • PROVC2 (Provisioned C2 Control Register)
    • PTHINSH (Path Overhead Insertion Control Register [High Byte])
    • PTHINSL (Path Overhead Insertion Control Register [Low Byte])
    • PTHINT (Receive Path Interrupt Indication Status Register)
    • PWRDWN (PowerDown/Three-State Control Register)
    • RLCNTH (REI-L Error Counter [High Byte])
    • RLCNTM (REI-L Error Counter [Mid Byte])
    • RLCNTL (REI-L Error Counter [Low Byte])
    • RPCNTH (REI-P Error Counter [High Byte])
    • RPCNTL (REI-P Error Counter [Low Byte])
    • RXAPS (Receive APS Status Register)
    • RXC2 (Receive C2 Path Overhead Status Register)
    • RXF1 (Receive F1 Section Overhead Status Register)
    • RXF2 (Receive F2 Path Overhead Status Register)
    • RXF3 (Receive Z3/F3 Path Overhead Status Register)
    • RXFRMREF (Receive Frame Reference Control Register)
    • RXK1 (Receive K1 Line Overhead Status Register)
    • RXK2 (Receive K2 Line Overhead Status Register)
    • RXK3 (Receive Z4/K3 Path Overhead Status Register)
    • RXLIN (Receive Line Overhead Status Register)
    • RXN1 (Receive Z5/N1 Path Overhead Status Register)
    • RXPNTR (Receive H2 Pointer Value Status Register)
    • RXPTH (Receive Path Overhead Status Register)
    • RXPTHBUF (Receive Path Trace Circular Buffer)
    • RXRDI (Receive RDI-P Status Register)
    • RXS1 (Receive S1 Line Overhead Status Register)
    • RXSEC (Receive Section Overhead Status Register)
    • RXSECBUF (Receive Section Trace Circular Buffer)
    • RXZ1b (Receive Z1b Overhead Status Register)
    • RXZ1c (Receive Z1c Overhead Status Register)
    • RXZ2a (Receive Z2a Overhead Status Register)
    • RXZ2b (Receive Z2b Overhead Status Register)
    • RXZ2c (Receive Z2c Overhead Status Register)
    • SECINT (Receive Section Interrupt Indication Status Register)
    • SEFCNT (Out of Frame Event Counter)
    • STATUS (Status Output Control Register)
    • SUMINT (Summary Interrupt Indication Register)
    • TESTMODE (Test Mode Control Register)
    • TCCNTH (Tandem Connection Error Counter [High Byte])
    • TCCNTL (Tandem Connection Error Counter [Low Byte])
    • TXC2 (Transmit C2 Path Overhead Control Register)
    • TXF1 (Transmit F1 Section Overhead Control Register)
    • TXF2 (Transmit F2 Path Overhead Control Register)
    • TXF3 (Transmit Z3/F3 Path Overhead Control Register)
    • TXK1 (Transmit K1 Overhead Control Register)
    • TXK2 (Transmit K2 Overhead Control Register)
    • TXK3 (Transmit K3 Overhead Control Register)
    • TXLIN (Transmit Line Overhead Control Register)
    • TXN1 (Transmit N1 Overhead Control Register)
    • TXPNTR (Transmit H1/H2/H3 Pointer Control Register)
    • TXPTH (Transmit Path Overhead Control Register)
    • TXPTHBUF (Transmit Path Trace Circular Buffer)
    • TXS1 (Transmit S1 Overhead Control Register)
    • TXSEC (Transmit Section Overhead Control Register)
    • TXSECBUF (Transmit Section Trace Circular Buffer)
    • TXZ1b (Transmit Z1b Overhead Control Register)
    • TXZ1c (Transmit Z1c Overhead Control Register)
    • TXZ2a (Transmit Z2a Overhead Control Register)
    • TXZ2b (Transmit Z2b Overhead Control Register)
    • TXZ2c (Transmit Z2c Overhead Control Register)
    • VERSION (Part Number/Version Register)
    • WINDOW_H (CDR Window Register [high byte])
    • WINDOW_L (CDR Window Register [low byte])
    • WINHYST1_H (CDR Hysteresis Register [high byte])
    • WINHYST1_L (CDR Hysteresis Register [low byte])
    • WINHYST2_H (CDR Hysteresis Register [high byte])
    • WINHYST2_L (CDR Hysteresis Register [low byte])
  • 4.2 Register Differences between STS-3 and STS-12 Modes
• 5.0 Electrical and Mechanical Specifications
  • 5.1 Timing Specifications
    • Table 51. Timing Diagram Nomenclature (1 of 3)
    • Figure 51. Input Waveform
    • Figure 52. Output Waveform
    • 5.1.1 Microprocessor Interface Timing
      • 5.1.1.1 Motorola MPC860 Interface
        • Figure 53. MPC 860 Read Timing Diagram
        • Table 52. MPC 860 Read Timing Table
        • Figure 54. MPC 860 Write Timing Diagram
        • Table 53. MPC 860 Write Timing Table
      • 5.1.1.2 Conexant EBUS Interface
        • Figure 55. EBUS Read Timing Diagram
        • Table 54. EBUS Read Timing Table
        • Figure 56. EBUS Write Timing Diagram
        • Table 55. EBUS Write Timing Table
    • 5.1.2 SI-Bus Transmit Timing
      • Figure 57. Transmit Timing Parameters
      • Table 56. Transmit Timing Values
    • 5.1.3 SI-Bus Receive Timing
      • Figure 58. Receive Timing Parameters
      • Table 57. Receive Timing Values
    • 5.1.4 JTAG Interface Timing
      • Figure 59. JTAG Timing Diagram
      • Table 58. JTAG Timing Table
    • 5.1.5 One-second Interface Timing
      • Figure 510. One-second Timing Diagram
      • Table 59. One-second Timing Table
    • 5.1.6 DCC Interface Timing
      • Figure 511. DCC Timing Diagram
      • Table 510. LDCC Timing Table
      • Table 511. SDCC Timing Table
    • 5.1.7 SONET Reference Timing
      • Figure 512. SONET Reference Timing Diagram
      • Table 512. SONET Reference Timing Table
    • 5.1.8 Frame Reference Timing
      • Figure 513. Frame Reference Timing Diagram
      • Table 513. Frame Timing Table
    • 5.1.9 Rx8kHz Interface Timing
      • Figure 514. Rx8kHz Timing Diagram
      • Table 514. Rx8kHz Timing Table
    • 5.1.10 E1/E2 Interface Timing
      • Figure 515. E1/E2 Timing Diagram
      • Table 515. E1/E2 Timing Table
  • 5.2 Absolute Maximum Ratings
    • Table 516. Absolute Maximum Ratings
  • 5.3 DC Characteristics
    • Table 517. DC Characteristics
    • 5.3.1 PECL Input
      • Table 518. PECL�Input Characteristics
    • 5.3.2 PECL Output
      • Table 519. PECL�Output Characteristics
    • 5.3.3 Single-ended PECL Input (LSigDet)
      • Table 520. Single-ended PECL Table
    • 5.3.4 Low Voltage PECL (LVPECL) Interface Example
      • Figure 516. LVPECL Interface
    • 5.3.5 PECL to LVPECL Interface Example
      • Figure 517. PECL to Low Voltage PECL (LVPECL) Interface
  • 5.4 Mechanical Specifications
    • Figure 518. CX29610 Ballout Diagram (Top View)
    • Figure 519. CX29610 Ballout Diagram (Bottom View)
    • Figure 520. CX29610 Mechanical Drawing
    • Table 521. Listing of Pin Numbers and Labels (Numeric Order) (1 of 4)
• Appendix A : CX29610 Software Overview
  • Figure A-1. Conceptual Software Architecture
  • A.1 HPI Overview
    • A.1.1 Device Initialization, Configuration, and Shutdown
    • A.1.2 SONET Overhead Management
    • A.1.3 Status and Interrupt Processing
    • A.1.4 Error Insertion
    • A.1.5 Loopback Configuration
    • A.1.6 Counter Retrieval
    • A.1.7 Register Mirrors
  • A.2 DDPI Overview
    • A.2.1 Device Initialization, Configuration, and Shutdown Capability
    • A.2.2 SONET Overhead, Status and Interrupt Processing
    • A.2.3 Statistics and Counter Retrieval
  • A.3 General CX29610 Software Features
    • A.3.1 Portability
    • A.3.2 Reentrancy
    • A.3.3 Error codes
    • A.3.4 Integration and Performance Friendly
    • A.3.5 Multiple Device Support
    • A.3.6 Common libraries
• Appendix B : Related Standards