Document Outline

• Preface
  • Maker Products
  • Using this manual
  • Contacting Maker Support Services
  • Changes Installed in This Version of the Manual
• CHAPTER 1 Introduction
  • MXT3010 features
    • FIGURE 1. MXT3010 and surrounding system devices
  • MXT3010 subsystems
  • What information is in this manual
• CHAPTER 2 The SWAN Processor
  • The SWAN advantage
    • SWAN�s instructions and address spaces
      • Instruction features
      • Address spaces
        • FIGURE 2. SWAN processor address spaces and access instructions
    • Instruction execution
    • Instruction space organization
      • FIGURE 3. SWAN instruction space
    • Instruction cache
      • Cache organization and mapping
        • FIGURE 4. Formation of the page offset and the instruction tag
      • Using the Cache
      • Instruction prefetch
      • Observing cached program flow
  • SWAN processor instruction classes
    • TABLE 1. SWAN processor instruction classes
    • Arithmetic Logic Unit (ALU) instructions
    • Branch instructions
      • FIGURE 5. Target address format in Fast Memory
      • TABLE 2. Methods of specifying the branch target field
  • Registers
    • FIGURE 6. Pipeline feedback
    • TABLE 3. Hardware registers requiring one instruction delay
    • TABLE 4. Hardware registers requiring two instruction delays
    • Flag registers
  • HEC generation and check circuit
• CHAPTER 3 The Cell Scheduling System
  • How the Cell Scheduling System works
    • TABLE 5. Scoreboard sectioning control
    • FIGURE 7. Connection ID entries
  • Data transmission - servicing and scheduling
    • Servicing
    • Scheduling
      • FIGURE 8. Servicing and scheduling
      • Calculating target time slots
  • Pacing the transmission rate of cells
  • Programming the Cell Scheduling System
    • FIGURE 9. Scoreboard operation
  • Guaranteeing the availability of a location in the Connection ID table
  • The PUSHC/POPC instruction buffer
  • POPC, PUSHC, POPF, and PUSHF instruction operation
    • POPC and PUSHC timing
    • POPF and PUSHF timing
    • Connection ID table and Scoreboard addressing
      • FIGURE 10. Connection ID table address generation
      • TABLE 6. Connection ID table address bits
      • FIGURE 11. Scoreboard address generation
      • TABLE 7. Scoreboard address bits
  • Initializing the Scoreboard
  • Selecting a Scoreboard size
  • Supporting multiple Scoreboard sections
• CHAPTER 4 The Fast Memory Interface
  • SWAN processor accesses to Fast Memory
    • Loading
      • FIGURE 12. Load Fast Memory instruction
    • Storing
      • FIGURE 13. Store Fast Memory instruction
  • Cell Scheduling System accesses to Fast Memory
  • SWAN executable fetches from Fast Memory
  • Fast Memory configurations
    • Memory sizes supported
      • FIGURE 14. Fast Memory SRAM options
    • RAM selection and configuration
    • Mode 0 operation
      • TABLE 8. Comparison of Mode 0 and Mode 1 operation
      • FIGURE 15. Mode 0 design example
    • Mode 1 operation
      • FIGURE 16. Mode 1 design example
    • Bus contention avoidance
  • Fast Memory sequence diagrams
    • FIGURE 17. Fast Memory read operations - single bank
    • FIGURE 18. Fast Memory write operations - single bank
    • FIGURE 19. Fast Memory reads and writes - back-to-back and dual bank
• CHAPTER 5 The Cell Buffer RAM
  • Internal cell storage in the Cell Buffer RAM
    • TABLE 9. UTOPIA Configuration control of the Cell Buffer RAM
    • FIGURE 20. Cell Buffer RAM organization
    • FIGURE 21. Cell fields defined
    • TABLE 10. Cell field functions
    • FIGURE 22. Receive cell organization: 52-byte and 56-byte cells
  • Cell Buffer RAM memory construction
    • FIGURE 23. Gather method accesses
  • Cell Buffer RAM access
    • FIGURE 24. Cell Buffer RAM access
• CHAPTER 6 The UTOPIA port
  • UTOPIA port interface overview
    • Features
    • Operating modes
      • TABLE 11. UTOPIA port data bus width selection
      • TABLE 12. UTOPIA port Tx and Rx pin utilization in 16-bit mode
      • FIGURE 25. The UTOPIA port: 8/8 and 16-bit modes
      • TABLE 13. Cell length and HEC control
      • TABLE 14. UTOPIA port clock selection
      • FIGURE 26. Clock phases for RX/TX CLK = 1/2 Internal Clock
      • FIGURE 27. Clock phases for RX/TX CLK = 1/4 Internal Clock
    • UTOPIA cell formats
      • FIGURE 28. UTOPIA 8-bit and 16-bit cell formats
      • FIGURE 29. HEC-enabled 52-byte mode
      • FIGURE 30. HEC-disabled 52-byte mode
      • FIGURE 31. HEC-enabled 56-byte mode
      • FIGURE 32. HEC-disabled 56-byte mode
  • Receive cell flow
    • UTOPIA receiver counters
      • FIGURE 33. The RXBUSY counter
      • The RXBUSY counter
        • FIGURE 34. The RXFULL counter
      • The RXFULL counter
  • Transmit cell flow
    • UTOPIA transmitter counters
      • FIGURE 35. The TXBUSY counter
    • The TXBUSY counter
      • FIGURE 36. The TXFULL counter
    • The TXFULL counter
    • CRC10 generation and checking support
  • Multi-PHY support
    • TABLE 15. Bit assignments for multi-PHY operation
    • FIGURE 37. Level 2 PHY configurations
    • FIGURE 38. Mixed Level 1 and Level 2 PHY configuration
  • Receive Header Reduction hardware
    • TABLE 16. Receive Header Reduction control
    • TABLE 17. Receive Header Reduction enable bit
  • UTOPIA port configuration summary
    • TABLE 18. UTOPIA configuration information
  • UTOPIA port sequence diagrams
    • FIGURE 39. UTOPIA Port receive timing - single PHY, 8-bit mode
    • FIGURE 40. UTOPIA Port transmit timing - single PHY, 8-bit mode
    • FIGURE 41. UTOPIA Port receive full timing - single PHY, 8-bit mode
    • FIGURE 42. UTOPIA Port transmit full timing - single PHY, 8-bit mode
• CHAPTER 7 The Port1 and Port2 Interfaces
  • Port interface overview
    • TABLE 19. Characteristics of Port1 and Port2
  • The Port DMA command queues
    • Port1 and Port2 DMA command queues
      • FIGURE 43. DMA command queues for the MXT3010EP
    • Testing DMA Controller queues with the ESS bits
      • TABLE 20. ESS Bits for DMA Controller status
      • TABLE 21. Example of DMA Controller status bit utilization
  • Port Controller features
    • The Cyclical Redundancy Check 32 generator for Port1
      • TABLE 22. Specification of the CRCX/CRCY instruction field option
    • Cyclical Redundancy Check operation acceleration
    • Silent transfers
    • Post-increment option on rla operations
    • Data alignment
    • Byte manipulations on Port1
      • TABLE 23. Valid and invalid first, mid-cell, and last transfers.
    • Post-DMA Operation Directives (PODs)
  • Burst and non-burst operation (Port2)
  • Port Operations
    • Port1 basic protocol
      • FIGURE 44. Diagram of Port1 DMA instruction bits
      • TABLE 24. Port 1 DMA instruction bit mapping
      • Port1 control signals
      • Restrictions on Port1 Addressing
        • TABLE 25. Signals to control Port1 transfers
    • The Port1 control state machine
      • General information concerning DMA transfers
        • TABLE 26. State table for the Port1 DMA burst read state machine
        • FIGURE 45. Port1 DMA Read transfer with a Wait state
        • FIGURE 46. Port1 DMA Read transfer without a Wait state
      • Port1 DMA write transfers
        • TABLE 27. State table for the Port1 DMA burst write state machine
        • FIGURE 47. Port1 DMA Write transfer with a Wait state
        • FIGURE 48. Port1 DMA Write transfer without a Wait state
      • Multiple Port1 Read and Write Transfers
        • FIGURE 49. Cut-and-Paste Version of Port1 Read
        • FIGURE 50. Cut-and-Paste Version of Port1 Write
    • Communication register I/O transfers
      • TABLE 28. State table for Port1 communication I/O state machine
      • FIGURE 51. COMMIN write followed by COMMOUT read
    • Port2 basic protocol
      • FIGURE 52. Diagram of Port2 burst DMA instruction bits
      • TABLE 29. Port2 burst DMA instruction bit mapping
      • TABLE 30. Another view of Port2 burst DMA instruction bit mapping
      • FIGURE 53. Diagram of Port2 non-burst DMA instruction bits
      • TABLE 31. Port2 non-burst DMA instruction bit mapping
      • TABLE 32. Another view of Port2 non-burst DMA instruction bit mapping
      • Multi-function AI pins (P2AI[3:0])
      • Port2 control signals
        • TABLE 33. Signals to control Port2 transfers
    • The Port2 control state machine
      • Port2 DMA burst-mode read transfers
        • TABLE 34. State table for the Port2 DMA burst-mode read state machine
        • FIGURE 54. Port2 DMA burst-mode Read transfer with a Wait state
        • FIGURE 55. Port2 DMA burst-mode Read transfer without a Wait state
      • Port2 DMA burst-mode write transfers
        • TABLE 35. State table for the Port2 DMA burst write state machine
        • FIGURE 56. Port2 DMA burst-mode write transfer with a Wait state
        • FIGURE 57. Port2 DMA burst-mode write transfer without a Wait state
    • Port2 DMA non-burst-mode read transfers
      • TABLE 36. State table for the Port2 DMA non-burst-mode read state machine
      • FIGURE 58. Port2 DMA non-burst-mode Read transfer.
    • Port2 DMA non-burst-mode write transfers
      • TABLE 37. State table for the Port2 DMA non-burst-mode write state machine
      • FIGURE 59. Port2 DMA non-burst-mode Write transfer.
  • Additional Port1 and Port2 Design Information
    • Arbitrating access to Port1
      • FIGURE 60. System example for Port1 bus.
    • Simplified Port2 interfaces
    • Bus driving, turnaround, and bus parking
    • Data Alignment
  • Transfer complete
    • Byte Count zero
      • FIGURE 61. DMA Read transfer with standard END_ signal
      • FIGURE 62. DMA Read transfer with Early END
    • External DMA cycle abort (P1ABORT_)
      • FIGURE 63. DMA Read transfer terminated by P1ABORT_
  • Endian-ness
    • FIGURE 64. Most Significant Byte is the Lowest Address (�Big-endian�)
    • FIGURE 65. Least Significant Byte is the Lowest Address (�Little- endian�)
    • TABLE 38. Comparison of Big-endian and Little-endian Read Operations
    • FIGURE 66. Hardware Byte-swapping Circuit
    • FIGURE 67. Word Access
    • TABLE 39. Accesses With Hardware and Software Swaps, 32-bit
    • FIGURE 68. 16-bit xxx0 Access
    • FIGURE 69. 16-bit xxx2 Access
    • TABLE 40. Accesses With Hardware and Software Swaps, 32-bit and 16-bit
    • FIGURE 70. Byte Access
    • TABLE 41. Accesses With Hardware and Software Swaps, 32-bit, 16-bit, and 8-bit
  • Port1 and Port2 Reference Designs
    • P1MemMaker
      • FIGURE 71. The Port1 MemMaker FPGA
      • FIGURE 72. Data Path Connections - Shared Memory to PCI
      • FIGURE 73. Data Path Connections - Shared Memory to MXT3010
    • P2MemMaker
      • FIGURE 74. The Port2 MemMaker FPGA
      • FIGURE 75. Data Path Connections - Shared Memory to PCI
      • FIGURE 76. Data Path Connections - Shared Memory to MXT3010
• CHAPTER 8 Communications
  • The COMMIN/COMMOUT register
    • TABLE 42. Definitions of CIN_BUSY and COUT_RDY
    • FIGURE 77. Timing of CIN_BUSY and COUT_RDY
  • Interchip communications
    • TABLE 43. ICSI pins
    • TABLE 44. ICSO pins
  • Registers
    • TABLE 45. Hardware registers
  • Instructions
    • TABLE 46. Alphabetical list of instructions
    • Instruction description notations
      • TABLE 47. Abbreviations used in SWAN instructions
• CHAPTER 9 Registers
  • Register types
    • Software registers
    • Hardware registers
    • Specifying registers in SWAN instructions
      • TABLE 48. Field abbreviations
    • Initializing software and hardware registers
      • TABLE 49. Hardware registers
  • R32 General Purpose - 0000
  • R33 General Purpose - FFFF
  • R34 General Purpose - FF00
  • R35 General Purpose - 0040
  • R36-write Bit Bucket register
  • R37-R39 General Purpose registers
  • R40-R41 Host Communication registers
  • R42-read External State Signals (ESS) register
  • R42-write Mode Configuration register
  • R43-read Fast Memory Bit Swap register (R42w[8]=0)
  • R43-read Special Features register (R42w[8]=1)
  • R43-write UTOPIA Control FIFO register
  • R44-R47 CRC32PRX and CRC32PRY registers
  • R48-R51 Local Address registers (rla)
  • R52 Alternate Byte Count/ID register
  • R53 Instruction Base Address register
  • R54-R55 Programmable Interval Timer registers
  • R56 Fast Memory Data register
  • R57-read Sparse Event/ICS register
  • R57-write Sparse Event/ICS register (Set/Clear)
  • R58 Fast Memory Shadow register
  • R59 Branch register
  • R60 The Cell Scheduling System (CSS) Configuration register
  • R61-read Scheduled Address register
  • R62 The UTOPIA Configuration register
    • TABLE 50. Signal utilization for 1-PHY and 2-PHY modes
  • R63 The System register
• CHAPTER 10 Arithmetic Logic Unit Instructions
  • Addressing modes
    • Triadic register
      • FIGURE 78. Triadic register operation
      • FIGURE 79. Triadic instruction format
    • Immediate
      • FIGURE 80. Immediate 10-bit instruction format
      • FIGURE 81. Immediate 6-bit instruction format
  • Overflow flag
  • Instruction options
    • Modulo arithmetic
      • TABLE 51. Modulo arithmetic options
    • Automatic memory updates
      • The Update Memory field (UM)
    • ALU branching
      • The ALU Branch Condition field (abc)
        • TABLE 52. ALU Branch Conditions for all instructions except Compare and Min/Max instructions
        • TABLE 53. ALU Branch Conditions for Compare and Min/Max instructions
      • The Always Execute field (AE)
  • ADD Add Registers
  • ADDI Add Register and Immediate
  • AND And Registers
  • ANDI And Register and Immediate
  • CMP Compare Two Registers
  • CMPI Compare Register and Immediate
  • CMPP Compare Two Registers with Previous
  • CMPPI Compare Register and Immediate with Previous
  • FLS Find Last Set
  • LIMD Load Immediate
  • MAX Maximum of Two Registers
  • MAXI Maximum of Register and Immediate
  • MIN Minimum of Two Registers
  • MINI Minimum of Register and Immediate
  • OR Or Registers
  • ORI Or Register and Immediate
  • SFT Shift Signed Amount
  • SFTA Shift Right Arithmetic
  • SFTAI Shift Right Arithmetic Immediate
  • SFTC Shift Left Circular
  • SFTCI Shift Circular Immediate
  • SFTRI/SFTLI Shift Right or Left Immediate
  • SUB Subtract Registers
  • SUBI Subtract Register and Immediate
  • XOR XOR Registers
  • XORI XOR Register and Immediate
• CHAPTER 11 Branch Instructions
  • General Branch instruction information
    • Introduction
      • FIGURE 82. Branch instruction format (simplified)
    • Target address
      • FIGURE 83. Target address format in Fast Memory
      • TABLE 54. Methods of specifying the Branch target field
    • Condition code (ESS Field)
      • TABLE 55. External State Signals register (R42) bits
    • The logical state identifier (S-Bit)
      • TABLE 56. Use of the S-bit
    • Committed slot instructions
    • The Conditional operator (C-bit)
      • TABLE 57. Use of the Conditional and Nullify operators
      • TABLE 58. Example - conditional branch, condition satisfied
      • TABLE 59. Example - conditional branch, condition not met
      • TABLE 60. Example - unconditional branch
      • TABLE 61. Example - conditional operator, conditional branch, condition satisfied
      • TABLE 62. Example - conditional operator, conditional branch, condition not satisfied
    • Subroutine linking
      • TABLE 63. Example - Branch with link, and return
    • Counter system operation
      • TABLE 64. The CSO field
  • BF Branch Fast Memory Shadow Register
  • BFL Branch Fast Memory Shadow Register and Link
  • BI Branch Immediate
  • BIL Branch Immediate and Link
  • BR Branch Register
  • BRL Branch Register and Link
• CHAPTER 12 Cell Scheduling Instructions
  • Cell Scheduling System target address
  • POPC Service Schedule
  • POPF POP Fast
  • PUSHC Schedule
  • PUSHF Push Fast
• CHAPTER 13 Direct Memory Access Instructions
  • General DMA instruction information
    • Introduction
      • FIGURE 84. DMA instruction format (simplified)
    • Op codes for DMA instructions
      • TABLE 65. Op codes for DMA instructions
    • The RLA increment bit (i-bit)
      • TABLE 66. Use of Bit 26
      • TABLE 67. Timing chart for accessing rla after a DMA
    • The Byte Count instruction field option (BC)
      • TABLE 68. Use of the BC field
      • The �Use Alternate Byte Count Register (R52)� Feature
      • Use of odd BC values
    • The Control instruction field option
      • FIGURE 85. Control field format)
      • TABLE 69. Use of the Control byte
  • DMA1R Direct Memory Operation - Port1 Read
  • DMA1W Direct Memory Operation - Port1 Write
  • DMA2R Direct Memory Operation - Port2 Read
  • DMA2W Direct Memory Operation - Port2 Write
• CHAPTER 14 Load and Store Fast Memory Instructions
  • General information for Load and Store Fast Memory instructions
    • Introduction
      • TABLE 70. Load Fast Memory instruction format
      • TABLE 71. Store Fast Memory instruction format
    • Transfer size (the #HW field)
    • Fast Memory address (the rsa and rsb fields)
      • TABLE 72. Use of the rsa and rsb fields
    • Address masking (the Z-bit)
      • TABLE 73. Use of the Z-bit
      • FIGURE 86. Z-bit usage example
    • Destination register (the rd field)
    • Linking (the LNK bit)
      • FIGURE 87. Simplified Channel Descriptors
      • TABLE 74. Limits on #HW when linking to rd
      • FIGURE 88. Channel Descriptor for LMFM and UM example
      • TABLE 75. Memory alignment requirements
  • Instructions for accelerating CRC operations
    • Alternate address (the adr field)
      • TABLE 76. Use of the adr field
    • Hardware register (reg field)
      • TABLE 77. Use of the reg field
    • Least significant bits (the lsbs field)
  • LMFM Load Multiple from Fast Memory
    • TABLE 78. Restrictions on access to rd registers after LMFM
  • SHFM Store Halfword to Fast Memory
  • SRH Store Register Halfword
• CHAPTER 15 Load and Store Internal RAM Instructions
  • General information for Load and Store internal RAM instructions
    • Introduction
      • TABLE 79. Load internal RAM instruction format
      • TABLE 80. Store internal RAM instruction format
    • Register load address (rla field)
      • TABLE 81. Use of the rla field
    • The index field (IDX)
      • Using IDX to calculate the target address
        • FIGURE 89. XOR operation between IDX and rla
      • Selecting the Cell Buffer RAM or the Scoreboard
      • Cell Buffer RAM accesses
        • FIGURE 90. Gather method accesses
      • Cell Scheduling System Scoreboard accesses
  • Byte swap support
    • The Swap field
      • TABLE 82. Byte-swapping Load instructions
      • TABLE 83. Byte-swapping Store instructions
  • LD Load Register
  • LDD Load Double Register
  • ST Store Register
  • STD Store Double Register
• CHAPTER 16 Swan Instruction Reference Examples
  • Add and Subtract examples
  • Branch examples
  • Load and Store Fast Memory examples
  • Load and Store Internal RAM examples
  • Logical examples
  • Shift examples
  • Miscellaneous examples
• CHAPTER 17 Timing
  • MXT3010EP timing - general information
    • Definition of switching levels
      • FIGURE 91. Switching level voltages
    • Input clock details
      • FIGURE 92. Input clock waveform (pin FN)
      • TABLE 84. Input clock timing parameters
  • MXT3010EP Fast Memory interface timing
    • TABLE 85. Fast Memory timing for the Maker MXT3010EP
    • FIGURE 93. Timing for Fast Memory reads
    • FIGURE 94. Timing for Fast Memory writes
  • MXT3010EP UTOPIA interface timing
    • FIGURE 95. FN and half-speed RX_CLK/TX_CLK
    • FIGURE 96. FN and quarter-speed RX_CLK/TX_CLK
    • TABLE 86. UTOPIA timing for Maker MXT3010EP
    • TABLE 87. Delay of UTOPIA clocks relative to MXT3010EP internal clock (CLK)
    • FIGURE 97. UTOPIA port receive timing
    • FIGURE 98. UTOPIA port transmit timing
  • MXT3010EP Port1 timing
    • TABLE 88. Port1 timing table
    • FIGURE 99. Port1 read timing
    • FIGURE 100. Port1 write timing
    • FIGURE 101. COMMIN register write, COMMOUT register read timing
  • MXT3010EP Port2 timing
    • TABLE 89. Port2 timing table
    • FIGURE 102. Port2 read timing
    • FIGURE 103. Port2 write timing
  • MXT3010EP miscellaneous control signal timing
    • TABLE 90. Miscellaneous control signal timing
    • FIGURE 104. Timing of CIN_BUSY and COUT_RDY
    • MXT3010EP Reset timing
      • TABLE 91. MXT3010EP reset timing
      • FIGURE 105. MXT3010EP reset timing
      • FIGURE 106. Reset trailing edge timing
      • TABLE 92. MXT3010EP RESET_ timing parameters
      • FIGURE 107. Reset timing circuit
  • MXT3010EP Fast Memory interface operation
  • MXT3010EP JTAG operation
• CHAPTER 18 Pin Information
  • MXT3010EP pinout
    • FIGURE 108. MXT3010EP package/pin diagram
  • MXT3010EP signal descriptions
    • TABLE 93. MXT3010EP Port1 signal descriptions
    • TABLE 94. MXT3010EP Port2 signal descriptions
    • TABLE 95. UTOPIA port signal description
    • TABLE 96. MXT3010EP Fast Memory controller signal description
    • TABLE 97. MXT3010EP inter-chip and communication registers signal description
    • TABLE 98. MXT3010EP miscellaneous clock, control, and test signal descriptions
    • TABLE 99. Power and ground pin descriptions
  • MXT3010EP JTAG/PLL pin termination
    • TABLE 100. MXT3010EP pin terminations
  • MXT3010EP pin listing
    • TABLE 101. MXT3010EP pin listing
    • I/O pad reference
      • TABLE 102. I/O pad types
• CHAPTER 19 Electrical Parameters
  • MXT3010EP maximum ratings and operating conditions
    • TABLE 103. Absolute maximum ratings (VSS = 0V)
    • TABLE 104. Recommended operating conditions
    • DC electrical characteristics
      • TABLE 105. DC Electrical characteristics
    • AC electrical characteristics
      • I/O performance levels
  • MXT3010EP power sequencing
    • Overview
    • Damage to I/O pad metal
    • I/O pad latch-up
  • MXT3010EP PLL considerations
    • Overview
    • VAA decoupling
      • FIGURE 109. Generating a quiet VAA
    • General decoupling
      • FIGURE 110. MXT3010EP decoupling capacitor location
    • Reference clock jitter
    • Circuit design goals
• CHAPTER 20 Mechanical and Thermal Information
  • MXT3010EP mechanical/thermal information
    • FIGURE 111. MXT3010EP package/pin diagram - top view
    • FIGURE 112. MXT3010EP package/pin diagram - side view
    • TABLE 106. MXT3010EP package summary
• APPENDIX A Acronyms
• APPENDIX B Device Initialization
  • Initializing the MXT3010EP
  • Downloading firmware
    • How the system determines the boot path
      • TABLE 107. Selecting boot mode with ISCO_A and ICSO_B
    • How the application uses the output pins
    • How the code set is structured
      • TABLE 108. User code set�s four fields
    • How to boot
      • Booting from Port1
      • Booting from Port2
      • Booting from the COMMIN Register
    • Limitations on the size of boot code
  • Initializing the Mode Configuration register
    • Restrictions on starting addresses
      • TABLE 109. Bootstrap starting addresses for Fast Memory mode 1
• APPENDIX C Quick Reference
  • Hardware register summary
    • TABLE 110. Hardware registers
  • ALU instruction field summary
    • TABLE 111. MODx fields
    • TABLE 112. abc fields
    • TABLE 113. AE field
    • TABLE 114. UM field
  • Shift amount summary
    • TABLE 115. Shift amount chart for SFT, SFTLI, and SFTRI
    • TABLE 116. Shift amount chart for SFTC and SFTCI
    • TABLE 117. Shift amount chart for SFTA
    • TABLE 118. Shift amount chart for SFTAI
  • Branch instruction field summary
    • TABLE 119. The ESS field (condition codes)
    • TABLE 120. The S-bit field
    • TABLE 121. The C-bit field
    • TABLE 122. The CSO field
  • DMA instruction field summary
    • TABLE 123. Use of the I-bit
    • TABLE 124. Use of the BC field
    • TABLE 125. Use of the Control byte
  • Instruction summary
    • TABLE 126. Instruction summary