Document Outline

• Preface
  • Maker Products
    • Traffic Stream Processing Solutions
    • ATM Cell Processing Solutions
  • Using this Manual
    • Additional Document References
  • Organization of this manual
• Section 1 Subsystems
  • CHAPTER 1 Device Overview
    • Circuit Interface
    • The Data Mover (Scatter/Gather) Units
    • Scatter and Gather Memory Interfaces
    • Port2 Interface
  • CHAPTER 2 Circuit Interface
    • Circuit Interface registers
      • Per-Link registers
      • Global registers
    • Link Configuration register
      • Added detail: Bits 12-10 � clock source control
      • Added detail: Bit 6 � link pair mode
      • Added detail: BSCE pin
    • Link Buffer Address counters
      • Link Rx Buffer Address counter
      • Link Tx Buffer Address counter
      • Details of the Link Tx/Rx Buffer Address counters
    • Link Tri-state Control Address counter
      • An example of the tri-state control process
      • The tri-state enable control map
      • Summary of tri-state control operation
    • Link service clock generation registers
      • Link Service Clock N register
      • Link Service Clock K register
      • Link Service Clock L counter
      • Link FTC counter
      • Link SRTS Value register
    • CI Tri-state Control Base Address register
    • CI Configuration register
      • MAXDS0, MAXTBS, and MAXRBS and buffer sizing
    • CI Quiet Frame Base Address register
      • Quiet Logic
    • CI SRTS FTC register
    • CI SRTS Valid Status register
    • CI Status register
    • Interface Pins
  • CHAPTER 3 Data Mover Units and Task Buffer RAMs
    • Lists and Tasks
    • Activating the Data Mover Unit
      • Loading list blocks
      • Loading the Task Buffer RAM
    • Data Mover Unit Instruction Set
    • Task Buffer Format
      • Channel Map Pointer
      • List Size
      • Frame Number
      • SAR Size
      • SAR Offset
      • Register 06 (write) - Additional control bits
      • Register 06 (read) - Additional status bits
    • Data Mover Unit Registers
      • Channel Map Pointer (CMP)
      • Instruction Pointer (IP)
      • Frame Counter (FC)
      • Transfer Counter (TC)
      • CRC Function Code (FNC)
      • HSCT Control Flags
      • Instruction Segment (ISEG)
      • Immediate (CONST)
      • Command (CMD)
      • Task Timer (TKT)
      • Status (STAT)
      • MAPD and Fill
      • TT register
      • TVR register
      • CRC-10 [9:0]
      • Start of CRC-10 [5:0]
    • Address Generation
      • List Block Address Generation
      • List RAM Address Generation
      • Scatter/Gather Memory Address Generation
      • Task Buffer RAM Address Generation
    • Interface Pins
    • Examples of Scatter and Gather Operations
      • Scatter
      • Gather
      • Multicast
  • CHAPTER 4 Scatter and Gather Memory Interfaces
    • Scatter Memory Controller
    • Gather Memory Controller
    • Determining Scatter and Gather Memory requirements
      • Scatter Memory
      • Gather Memory
    • Interface Pins
  • CHAPTER 5 Port2 Interface
    • MXT3020 addressing
    • MXT3020 address space
    • Interface Pins
  • CHAPTER 6 Register Reference
    • Channel Map Pointer (TBR and DMU)
    • CI Configuration register
    • CI Quiet Frame Base Address register
    • CI SRTS FTC register
    • CI SRTS Valid Status register
    • CI Status register
    • CI Tri-state Control Base Address register
    • Command register
    • CRC-10 register
    • Immediate and Control Flags register (TBR and DMU)
    • Instruction Pointer and Frame Counter
    • Link Configuration register
    • Link FTC counter
    • Link Rx Buffer Address counter
    • Link Service Clock K register
    • Link Service Clock L counter
    • Link Service Clock N register
    • Link SRTS Value register
    • Link Tri-state Control Address counter
    • Link Tx Buffer Address counter
    • List Size and Frame Number
    • MAPD and FILL registers
    • SAR SDU registers
    • SAR Size and SAR Offset
    • TT and TVR registers
    • Status register
    • Task Timer register
    • Transfer Counter and Task Buffer Offset registers
• Section 3 Physical Specification
  • CHAPTER 7 Interfacing Guidelines
    • Interfacing to Scatter/Gather Memory
    • Interfacing the MXT3020 to the MXT3010
      • Port2 Burst and Non-Burst Operation
      • The DMA2 instructions
    • Multiple MXT3020 implementation
    • Device selection code example
    • Scatter/Gather Task Buffer Busy flags
      • Quad MXT3020 layout considerations
      • Timing analysis of quad MXT3020 on Port 2
      • PCB Design Concerns for quad MXT3020
    • Clock tree distribution
  • CHAPTER 8 Timing
    • MXT3020 timing - general information
      • Definition of switching levels
      • Input clock details
    • Timing
    • Circuit Interface
    • Port2 Interface timing
    • Scatter/Gather Memory Interface
    • Status Interface
    • SCSA Bus Timing
    • MVIP Bus Timing
    • MXT3020 Assistance to Non-burst Devices
    • MXT3020 reset timing
  • CHAPTER 9 Pin Information
    • MXT3020 pinout
    • MXT3020 signal descriptions
    • JTAG/PLL Miscellaneous pin terminations
    • Pin Listing
  • CHAPTER 10 Electrical Parameters
    • MXT3020 maximum ratings and operating conditions
      • DC electrical characteristics
    • MXT3020 power sequencing
    • MXT3020 PLL considerations
      • Overview
      • VDD_PLLVCC decoupling
      • General decoupling
      • Reference clock jitter
  • CHAPTER 11 Mechanical and Thermal Information
    • MXT3020 mechanical/thermal information
      • Storage conditions