Document Outline

• RS8235
• Endstation ATM ServiceSAR with xBR Traffic Management
• Table of Contents
• List of Figures
• List of Tables
• 1.0 Product Overview
  • 1.1 Introduction
    • Figure 11. RS8235 Functional Block Diagram
  • 1.2 Service Specific Performance Accelerators
  • 1.3 Designer Toolkit
• 2.0 Architecture Overview
  • 2.1 Introduction
  • 2.2 High Performance Host Architecture With Buffer Isolation
    • 2.2.1 Multiple ATM Clients
      • Figure 21. Multiple Client Architecture
    • 2.2.2 RS8235 Queue Structure
      • Figure 22. RS8235 Queue Architecture
      • Figure 23. Interaction of Queues with RS8235 Functional Blocks
    • 2.2.3 Buffer Isolation Utilizing Descriptor-Based Buffer Chaining
      • Figure 24. Reassembly Buffer Isolation � Data Buffers Separated from Descriptors
      • Figure 25. Segmentation Buffer Isolation � Data Buffers Separated from Descriptors
    • 2.2.4 Status Queue Relation to Buffers and Descriptors
      • Figure 26. Segmentation Status Queues Related to Data Buffers and Descriptors
      • Figure 27. Reassembly Status Queues Related to Data Buffers and Descriptors
    • 2.2.5 Write-Only Control/Status
      • Figure 28. Write-Only Control and Status Architecture
    • 2.2.6 Scatter/Gather DMA
    • 2.2.7 Interrupts
  • 2.3 Automated Segmentation Engine
  • 2.4 Automated Reassembly Engine
  • 2.5 Advanced xBR Traffic Management
    • Figure 29. Multi-Level Model for Prioritizing Segmentation Traffic
    • 2.5.1 CBR Traffic
    • 2.5.2 VBR Traffic
    • 2.5.3 ABR Traffic
    • 2.5.4 UBR Traffic
    • 2.5.5 GFR Traffic
    • 2.5.6 xBR Cell Scheduler
    • 2.5.7 ABR Flow Control Manager
  • 2.6 Implementation of OAM Protocols
  • 2.7 Standards-Based I/O
  • 2.8 Electrical/Mechanical
  • 2.9 Logic Diagram and Pin Descriptions
    • Figure 210. RS8235 Logic Diagram (1 of 3)
      • Table 21. Hardware Signal Definitions (1 of 5)
• 3.0 Host Interface
  • 3.1 Overview
  • 3.2 Multiple Client Architecture
    • Figure 31. Client/Server Model of the RS8235
    • 3.2.1 Logical Clients
    • 3.2.2 Resource Allocation
    • 3.2.3 Resource Isolation
    • 3.2.4 Peer-to-Peer Transfers
      • Figure 32. Peer-to-Peer vs. Centralized Memory Data Transfers
  • 3.3 Write-Only Control and Status
    • Table 31. RS8235 Control and Status Queues
    • 3.3.1 Write-Only Control Queues
      • 3.3.1.1 Control Variables
        • Table 32. Write-Only Control Queue Variables
      • 3.3.1.2 Queue Management
      • Figure 33. Write-Only Control Queue
      • 3.3.1.3 Underflow Conditions
    • 3.3.2 Write-only Status Queues
      • 3.3.2.1 Control Variables
        • Table 33. Write-only Status Queue Variables
      • 3.3.2.2 Queue Management
      • Figure 34. Write-Only Status Queue
      • 3.3.2.3 Overflow Conditions
      • 3.3.2.4 Status Queue Interrupt Delay
  • 3.4 System Clocking
  • 3.5 RS8235 Reset
• 4.0 Segmentation Coprocessor
  • 4.1 Overview
  • 4.2 Segmentation Functional Description
    • 4.2.1 Segmentation VCCs
      • 4.2.1.1 Segmentation VCC Table
      • Figure 41. Segmentation VCC Table
      • 4.2.1.2 VCC Identification
    • 4.2.2 Submitting Segmentation Data
      • 4.2.2.1 User Data Format
      • 4.2.2.2 Buffer Descriptors
        • Table 41. Segmentation PDU Delineation
      • 4.2.2.3 Host Linked Segmentation Buffer Descriptors
      • Figure 42. Segmentation Buffer Descriptor Chaining
      • 4.2.2.4 Transmit Queues
      • Figure 43. Before SAR Transmit Queue Entry Processing
      • Figure 44. After SAR Transmit Queue Entry Processing
      • 4.2.2.5 Partial PDUs
      • 4.2.2.6 Virtual Paths
    • 4.2.3 CPCS-PDU Processing
      • 4.2.3.1 AAL5
      • Figure 45. AAL5 CPCS-PDU Generation
      • 4.2.3.2 AAL0
    • 4.2.4 ATM Physical Layer Interface
    • 4.2.5 Status Reporting
    • 4.2.6 Virtual FIFOs
  • 4.3 Segmentation Control and Data Structures
    • 4.3.1 Segmentation VCC Table Entry
      • Table 42. Segmentation VCC Table Entry � AAL5/AAL0 Format
      • Table 43. Segmentation VCC Table Entry � AAL5 and 0 Field Descriptions (1 of 2)
      • Table 44. Segmentation VCC Table Entry � Virtual FIFOs
      • Table 45. Segmentation VCC Table Entry � Virtual FIFO Format Field Descriptions
    • 4.3.2 Data Buffers
    • 4.3.3 Segmentation Buffer Descriptors
      • Table 46. Segmentation Buffer Descriptor Entry Format
      • Table 47. MISC_DATA Field Bit Definitions with HEADER_MOD Bit Set (1)
      • Table 48. MISC_DATA Field Bit Definitions with RPL_VCI BIt Set (1)
      • Table 49. Field Descriptions of the Segmentation Buffer Descriptor (1 of 3)
    • 4.3.4 Transmit Queues
      • 4.3.4.1 Entry Format
        • Table 410. Transmit Queue Entry Format
        • Table 411. Field Descriptions of the Transmit Queue Entry
      • 4.3.4.2 Transmit Queue Management
        • Table 412. Transmit Queue Base Table Entry
        • Table 413. Transmit Queue Base Table Entry Field Descriptions
    • 4.3.5 Segmentation Status Queues
      • 4.3.5.1 Entry Format
        • Table 414. Segmentation Status Queue Entry
        • Table 415. Segmentation Status Queue Entry Field Descriptions
      • 4.3.5.2 Status Queue Management
        • Table 416. Segmentation Status Queue Base Table Entry
        • Table 417. Segmentation Status Queue Base Table Entry Field Descriptions
      • 4.3.5.3 Status Queue Overflow
    • 4.3.6 Segmentation Internal SRAM Memory Map
      • Table 418. Segmentation Internal SRAM Memory Map
• 5.0 Reassembly Coprocessor
  • 5.1 Overview
  • 5.2 Reassembly Functional Description
    • Figure 51. Reassembly � Basic Process Flow
    • 5.2.1 Reassembly VCCs
      • Figure 52. Reassembly VCC Table
      • 5.2.1.1 Relation to Segmentation VCCs
    • 5.2.2 Channel Lookup
      • Figure 53. Direct Index Method for VPI/VCI Channel Lookup
      • 5.2.2.1 Programmable Block Size for VCC Table/ VCI Index Table
      • Figure 54. Programmable Block Size Alternate Direct Index Method
        • Table 51. Programmable Block Size Values for Direct Index Lookup
      • 5.2.2.2 Setup
      • 5.2.2.3 Operation
  • 5.3 CPCS-PDU Processing
    • Figure 55. CPCS-PDU Reassembly
    • 5.3.1 AAL5 Processing
      • 5.3.1.1 AAL5 COM Processing
      • 5.3.1.2 AAL5 EOM Processing
      • Figure 56. AAL5 EOM Cell Processing � Fields to Status Queue
      • Figure 57. AAL5 Processing � CRC and PDU Length Checks
      • 5.3.1.3 AAL5 Error Conditions
    • 5.3.2 AAL0 Processing
      • 5.3.2.1 Termination Methods
      • Figure 58. AAL0 PTI PDU Termination
      • 5.3.2.2 AAL0 Error Conditions
    • 5.3.3 ATM Header Processing
    • 5.3.4 BOM Synchronization Signal
      • Table 52. STAT Output Pin Values for BOM Synchronization
  • 5.4 Buffer Management
    • 5.4.1 Host vs. Local Reassembly
    • 5.4.2 Scatter Method
      • Figure 59. Host and SAR Shared Memory Data Structures for Scatter Method
    • 5.4.3 Free Buffer Queues
      • Figure 510. Free Buffer Queue Structure
    • 5.4.4 Linked Data Buffers
      • Figure 511. Buffer Structures
    • 5.4.5 Initialization of Buffer Structures
      • 5.4.5.1 Buffer Descriptors
      • 5.4.5.2 Free Buffer Queue Base Table
      • 5.4.5.3 Free Buffer Queue Entries
      • 5.4.5.4 Other Initialization
    • 5.4.6 Buffer Allocation
    • 5.4.7 Error Conditions
    • 5.4.8 Early Packet Discard
      • 5.4.8.1 General Description
      • 5.4.8.2 Frame Relay Packet Discard
      • 5.4.8.3 CLP Packet Discard
      • 5.4.8.4 LANE-LECID Packet Discard � Echo Suppression on Multicast Data Frames
      • 5.4.8.5 DMA FIFO Full
      • 5.4.8.6 Error Conditions
    • 5.4.9 Hardware PDU Time-out
      • 5.4.9.1 Reassembly Time-out Process
      • 5.4.9.2 Halting Time-out Processing
      • 5.4.9.3 Timer Reset
      • 5.4.9.4 Reassembly Time-out Condition
      • 5.4.9.5 Time-out Period Calculation
    • 5.4.10 Virtual FIFO Mode
      • 5.4.10.1 Setup
      • 5.4.10.2 Operation
      • 5.4.10.3 Errors
    • 5.4.11 Firewall Functions
      • 5.4.11.1 Setup
      • 5.4.11.2 Operation
      • 5.4.11.3 Credit Return
  • 5.5 Global Statistics
  • 5.6 Status Queue Operation
    • 5.6.1 Structure
      • Figure 512. Data Structure Locations for Status Queues
      • Figure 513. Status Queue Structure Format
      • 5.6.1.1 Setup
      • 5.6.1.2 Operation
      • 5.6.1.3 Errors
      • 5.6.1.4 Host Detection of Status Queue Entries
    • 5.6.2 Status Queue Overflow or Full Condition
  • 5.7 Reassembly Control and Status Structures
    • 5.7.1 Channel Lookup Structures
      • Figure 514. VPI/VCI Channel Lookup Structure
        • Table 53. Normal VPI Index Table Entry Format
        • Table 54. VPI Index Table Entry Format with EN_PROG_BLK_SX(RSM_CTRL1) Enabled
        • Table 55. VPI Index Table Entry Descriptions
        • Table 56. Normal VCI Index Table Format
        • Table 57. VCI Index Table Format with EN_PROG_BLK_SZ(RSM_CTRL1) Enabled
        • Table 58. VCI Index Table Descriptions
    • 5.7.2 Reassembly VCC Table
      • Figure 515. Reassembly VCC Table Entry Lookup Mechanism
        • Table 59. Reassembly VCC Table Entry Format � AAL5
        • Table 510. Reassembly VCC Table Entry Format � AAL0
        • Table 511. PDU_FLAGS Field Bit Definitions
        • Table 512. ABR_CTRL Field Bit Definitions
        • Table 513. AAL_EN Field Bit Definitions
        • Table 514. Reassembly VCC Table Descriptions (1 of 2)
    • 5.7.3 Reassembly Buffer Descriptor Structure
      • Table 515. Reassembly Buffer Descriptor Structure
      • Table 516. Reassembly Buffer Descriptor Structure Definitions
    • 5.7.4 Free Buffer Queues
      • Table 517. Free Buffer Queue Base Table Entry Format
      • Table 518. Free Buffer Queue Base Table Entry Descriptions
      • Table 519. Free Buffer Queue Entry Format
      • Table 520. Free Buffer Queue Entry Descriptions
    • 5.7.5 Reassembly Status Queues
      • Table 521. Reassembly Status Queue Base Table Entry Format
      • Table 522. Reassembly Status Queue Base Table Entry Descriptions
      • Table 523. Reassembly Status Queue Entry Format
      • Table 524. PDU_CHECKS Field Bits
      • Table 525. STATUS Field Bits
      • Table 526. STM Field Bits
      • Table 527. Reassembly Status Queue Entry Descriptions (1 of 2)
    • 5.7.6 LECID Table
      • Figure 516. LECID Table
        • Table 528. LECID Table Entries
        • Table 529. LECID Table Field Definition
    • 5.7.7 Global Time-out Table
      • Table 530. Global Time-out Table Entry Format
      • Table 531. Global Time-out Table Entry Descriptions
• 6.0 Traffic Management
  • 6.1 Overview
    • Table 61. ATM Service Category Parameters and Attributes (1 of 2)
    • 6.1.1 xBR Cell Scheduler
      • Figure 61. Non-ABR Cell Scheduling
    • 6.1.2 ABR Flow Control Manager
      • Figure 62. ABR Flow Control
  • 6.2 xBR Cell Scheduler Functional Description
    • 6.2.1 Scheduling Priority
      • 6.2.1.1 8 Priority Levels + CBR
      • 6.2.1.2 VCC Priority Assignment
    • 6.2.2 Dynamic Schedule Table
      • 6.2.2.1 Overview
      • Figure 63. Schedule Table with Size = 100
      • 6.2.2.2 Schedule Table Slots
        • Table 62. Selection of Schedule Table Slot Size by System Requirements
      • 6.2.2.3 Schedule Slot Formats
      • Figure 64. Schedule Slot Formats
      • 6.2.2.4 Some Scheduling Scenarios
      • Figure 65. One Possible Scheduling Priority Scheme with the RS8235
    • 6.2.3 CBR Traffic
      • 6.2.3.1 CBR Rate Selection
      • 6.2.3.2 Available Rates
      • Figure 66. Assigning CBR Cell Slots
      • 6.2.3.3 CBR Cell Delay Variation (CDV)
      • Figure 67. Introduction of CDV at the ATM/PHY Layer Interface
      • Figure 68. Schedule Table with Slot Conflicts at Different CBR Rates
      • Figure 69. CDV Caused by Schedule Table Size at Certain CBR Rates
      • 6.2.3.4 CBR Channel Management
    • 6.2.4 VBR Traffic
      • 6.2.4.1 Mapping RS8235 VBR Service Categories to TM 4.1 VBR Service Categories
      • 6.2.4.2 Rate Shaping vs. Policing
      • 6.2.4.3 Single Leaky Bucket
      • 6.2.4.4 Dual Leaky Bucket
      • 6.2.4.5 CLP Based Buckets
      • 6.2.4.6 Rate Selection
      • 6.2.4.7 Real-Time VBR and CDV
    • 6.2.5 UBR Traffic
    • 6.2.6 CBR Tunnels (Pipes)
    • 6.2.7 Guaranteed Frame Rate
    • 6.2.8 PCR Control for Priority Queues
  • 6.3 ABR Flow Control Manager
    • 6.3.1 A Brief Overview of TM 4.1
    • 6.3.2 Internal ABR Feedback Control Loop
      • Figure 610. ABR Service Category Feedback Control
      • 6.3.2.1 Source Flow Control Feedback
      • Figure 611. RS8235 ABR-ER Feedback Loop (Source Behavior)
      • 6.3.2.2 Destination Behavior
      • Figure 612. RS8235 ABR-ER Feedback Generation (Destination Behavior)
      • 6.3.2.3 Out of Rate Cells
    • 6.3.3 Source and Destination Behaviors
    • 6.3.4 ABR VCC Parameters
    • 6.3.5 ABR Templates
  • 6.4 GFC Flow Control Manager
    • 6.4.1 A Brief Overview of GFC
    • 6.4.2 The RS8235�s Implementation of GFC
    • 6.4.3 Configuring the Link for GFC Operation
  • 6.5 Traffic Management Control and Status Structures
    • 6.5.1 Schedule Table
      • Table 63. Schedule Slot Entry � CBR/Tunnel Traffic
    • 6.5.2 CBR-Specific Structures
      • 6.5.2.1 CBR Traffic
        • Table 64. CBR_TUN_ID Field, Bit Definitions � CBR Slot
      • 6.5.2.2 Tunnel Traffic
        • Table 65. CBR_TUN_ID Field, Bit Definitions � Tunnel Slot
        • Table 66. Schedule Slot Field Descriptions � CBR Traffic
      • 6.5.2.3 SCH_STATE Fields For CBR
        • Table 67. SCH_STATE for SCH_MODE = CBR
        • Table 68. CBR SCH_STATE Field Descriptions (1 of 2)
    • 6.5.3 VBR-Specific Structures
      • 6.5.3.1 VBR SCH_STATE
      • 6.5.3.2 VBR1 or VBR2 Schedule State Table
        • Table 69. SCH_STATE for SCH_MODE = VBR1 or VBR2
        • Table 610. VBR1 and VBR2 SCH_STATE Field Descriptions (1 of 2)
      • 6.5.3.3 Bucket Table for VBR2 and VBRC
        • Table 611. Bucket Table Entry
        • Table 612. Bucket Table Entry Field Descriptions
    • 6.5.4 GFR-Specific Structures
      • 6.5.4.1 GFR Schedule State Table
        • Table 613. SCH_STATE for SCH_MODE = GFR
        • Table 614. SCH_STATE Field Descriptions for SCH_MODE = GFR
      • 6.5.4.2 GFR MCR Limit Bucket Table
        • Table 615. GFR MCR Limit Bucket Table Entry
        • Table 616. GFR MCR Bucket Table Entry Field Descriptions
    • 6.5.5 ABR-Specific Structures
      • 6.5.5.1 ABR Schedule State Table
        • Table 617. SCH_STATE for SCH_MODE = ABR
        • Table 618. ER SCH_STATE Field Descriptions (1 of 2)
    • 6.5.6 Scheduler Internal SRAM Registers
      • Figure 613. Head and Tail Pointers
        • Table 619. Scheduler Internal SRAM Memory Map
• 7.0 OAM Functions
  • 7.1 OAM Overview
    • 7.1.1 OAM Functions Supported
    • 7.1.2 OAM Flows Supported
      • 7.1.2.1 F4 OAM Flow
      • 7.1.2.2 F5 OAM Flow
    • 7.1.3 OAM Cell Format
      • Figure 71. OAM Cell Format
  • 7.2 Segmentation of OAM Cells
    • 7.2.1 Key OAM-Related Fields for OAM Segmentation
      • 7.2.1.1 Segmentation Buffer Descriptors
      • 7.2.1.2 Low Latency Transmission
      • 7.2.1.3 Segmentation Status Queue
      • 7.2.1.4 F4 Flow
    • 7.2.2 Error Condition During OAM Segmentation
  • 7.3 Reassembly of OAM Cells
    • 7.3.1 Key OAM-Related Fields for OAM Reassembly
      • 7.3.1.1 Reassembly VCC State Table
      • 7.3.1.2 Reassembly Status Queue
      • 7.3.1.3 F4 Flow
    • 7.3.2 OAM Reassembly Operation
    • 7.3.3 Error Conditions During OAM Reassembly
  • 7.4 OAM Control and Status Structures
• 8.0 DMA Coprocessor
  • 8.1 Overview
  • 8.2 DMA Read
  • 8.3 DMA Write
  • 8.4 Misaligned Transfers
    • Figure 81. LIttle Endian Aligned Transfer
    • Figure 82. Little Endian Misaligned Transfer
    • Figure 83. Big Endian Aligned Transfer
    • Figure 84. Big Endian Misaligned Transfer
  • 8.5 Control Word Transfers
• 9.0 Local Memory Interface
  • 9.1 Overview
    • Figure 91. RS8235 Memory Map
  • 9.2 Memory Bank Characteristics
    • Table 91. Memory Bank Size
    • Figure 92. 0.5 MB SRAM Bank Using by_8 Devices
    • Figure 93. 1 MB SRAM Bank Using by_16 Devices
  • 9.3 Memory Size Analysis
    • Table 92. Memory Size in Bytes
• 10.0 PCI Bus Interface
  • 10.1 Overview
  • 10.2 Unimplemented PCI Bus Interface Functions
  • 10.3 PCI Configuration Space
  • 10.4 PCI Bus Master Logic
  • 10.5 Burst FIFO Buffers
  • 10.6 PCI Bus Slave Logic
  • 10.7 Byte Swapping of Control Structures
  • 10.8 Power Management
  • 10.9 Interface Module to Serial EEPROM
    • 10.9.1 EEPROM Format
      • Table 101. EEPROM Fields
    • 10.9.2 Loading the EEPROM Data at Reset
    • 10.9.3 Accessing the EEPROM
    • 10.9.4 Using the Subsystem ID Without an EEPROM
  • 10.10 PCI Host Address Map
• 11.0 ATM UTOPIA Interface
  • 11.1 Overview of ATM UTOPIA Interface
  • 11.2 Typical Interface Connection to the RS8250 PHY
    • Table 111. Standalone Interface Pins 
    • Figure 111. RS8250 and SAR (RS8235) Interface
    • Figure 112. RS8235/PHY Functional Timing with Inserted Wait States
    • Figure 113. RS8235/RS8250 Read/Write Functional Timing
  • 11.3 ATM Physical Interface Logic
    • Table 112. ATM Physical Interface Mode Select
  • 11.4 ATM Physical I/O Pins
    • Table 113. UTOPIA Mode Signals
    • Table 114. Slave UTOPIA Mode Interface Signals
  • 11.5 UTOPIA Mode Cell Handshake Timing
    • Figure 114. Receive Timing in UTOPIA Mode with Cell Handshake
    • Figure 115. Transmit Timing in UTOPIA Mode with Cell Handshake
  • 11.6 UTOPIA Mode Octet Handshake Timing
    • Figure 116. Receive Timing in UTOPIA Mode with Octet Handshake
    • Figure 117. Transmit Timing in UTOPIA Mode with Octet Handshake
  • 11.7 Slave UTOPIA Mode
    • Figure 118. Receive Timing in Slave UTOPIA Mode
    • Figure 119. Transmit Timing in Slave UTOPIA Mode
  • 11.8 Loopback Mode
    • Figure 1110. Source Loopback Mode Diagram
  • 11.9 Receive Cell Synchronization Logic
  • 11.10 Transmit Cell Synchronization Logic
• 12.0 RS8235 Registers
  • 12.1 CSR Registers
    • Table 121. RS8235 Control and Status Registers (1 of 2)
    • 12.1.1 Register Terminology
  • 12.2 System Registers
    • 12.2.1 0x00 - Real-Time Clock Register (CLOCK)
    • 12.2.2 0x04 - Alarm Register 1 (ALARM1)
    • 12.2.3 0x0c - System Status Register (SYS_STAT)
    • 12.2.4 0x14 - Configuration Register 0 (CONFIG0)
    • 12.2.5 0x1c - Interrupt Delay Register (INT_DELAY)
  • 12.3 Segmentation Registers
    • 12.3.1 0x80 - Segmentation Control Register (SEG_CTRL)
    • 12.3.2 0x84 - Seg VCC Table & Schedule Table Base Address Register (SEG_VBASE)
    • 12.3.3 0x88 - Segmentation PM Base Register (SEG_PMBASE)
    • 12.3.4 0x8c - Segmentation Transmit Queue Base Register (SEG_TXBASE)
  • 12.4 Scheduler Registers
    • 12.4.1 0xa0 - Schedule Priority Register (SCH_PRI)
    • 12.4.2 0xa8 - Schedule Size Register (SCH_SIZE)
    • 12.4.3 0xac - Scheduler Control Register (SCH_CTRL)
    • 12.4.4 0xb0 - Maximum ABR VCC_INDEX Register (SCH_ABR_MAX)
    • 12.4.5 Schedule ABR Constant Register (SCH_ABR_CON)
    • 12.4.6 0xb4 - Schedule ABR Constant Register (SCH_ABR_CON)
    • 12.4.7 Schedule ABR Constant Register (SCH_ABR_CON)
    • 12.4.8 0xb8 - ABR Decision Table Lookup Base Register (SCH_ABRBASE)
    • 12.4.9 Schedule ABR Constant Register (SCH_ABR_CON)
    • 12.4.10 0xbc - ABR Congestion Register (SCH_CNG)
    • 12.4.11 Schedule ABR Constant Register (SCH_ABR_CON)
    • 12.4.12 0xc0 - PCR Queue Interval 0 and 1 Register (PCR_QUE_INT01)
    • 12.4.13 0xc4 - PCR Queue Interval 2 and 3 Register (PCR_QUE_INT23)
  • 12.5 Reassembly Registers
    • 12.5.1 0xf0 - Reassembly Control Register 0 (RSM_CTRL0)
    • 12.5.2 0xf4 - Reassembly Control Register 1 (RSM_CTRL1)
    • 12.5.3 0xf8 - Reassembly Free Buffer Queue Base Register (RSM_FQBASE)
    • 12.5.4 0xfc - Reassembly Free Buffer Queue Control Register (RSM_FQCTRL)
    • 12.5.5 0x100 - Reassembly Table Base Register (RSM_TBASE)
    • 12.5.6 0x104 - Reassembly Time-out Register (RSM_TO)
    • 12.5.7 0x108 - Reassembly/Segmentation Queue Base Register (RS_QBASE)
  • 12.6 Counters and Status Registers
    • 12.6.1 0x160 - ATM Cells Transmitted Counter (CELL_XMIT_CNT)
    • 12.6.2 0x164 - ATM Cells Received Counter (CELL_RCVD_CNT)
    • 12.6.3 0x168 - ATM Cells Discarded Counter (CELL_DSC_CNT)
    • 12.6.4 0x16c - AAL5 PDUs Discarded Counter (AAL5_DSC_CNT)
    • 12.6.5 0x1a4 - Host Status Write Register (HOST_ST_WR)
    • 12.6.6 Host Interrupt Status Registers
      • 12.6.6.1 0x1c0 - Host Interrupt Status Register 0 (HOST_ISTAT0)
      • 12.6.6.2 0x1c4 - Host Interrupt Status Register 1 (HOST_ISTAT1)
      • 12.6.6.3 0x1d0 - Host Interrupt Mask Register 0 (HOST_IMASK0)
      • 12.6.6.4 0x1d4 - Host Interrupt Mask Register 1 (HOST_IMASK1)
  • 12.7 PCI Bus Interface Registers
    • 12.7.1 PCI Configuration Register
      • 12.7.1.1 PCI Configuration Register Field Descriptions
      • 12.7.1.2 PCI Command Register Description
      • 12.7.1.3 PCI Status Register Description
      • 12.7.1.4 PCI Special Status Register Description
      • 12.7.1.5 EEPROM Register Description
• 13.0 SAR Initialization - Example Tables
  • 13.1 Segmentation Initialization
    • 13.1.1 Segmentation Control Registers
      • Table 131. Table of Values for Segmentation Control Register Initialization
    • 13.1.2 Segmentation Internal Memory Control Structures
      • Table 132. Table of Values for Segmentation Internal Memory Initialization
    • 13.1.3 Segmentation SAR Shared Memory Control Structures
      • Table 133. Table of Values for SEG SAR Shared Memory Initialization (1 of 2)
  • 13.2 Scheduler Initialization
    • 13.2.1 Scheduler Control Registers
      • Table 134. Table of Values for Scheduler Control Register Initialization
    • 13.2.2 Scheduler Internal Memory Control Structures
    • 13.2.3 Scheduler SAR Shared Memory Control Structures
      • Table 135. Table of Values for Scheduler SAR Shared Memory Initialization (1 of 2)
  • 13.3 Reassembly Initialization
    • 13.3.1 Reassembly Control Registers
      • Table 136. Table of Values for Reassembly Control Register Initialization (1 of 2)
    • 13.3.2 Reassembly Internal Memory Control Structures
      • Table 137. Table of Values for Reassembly Internal Memory Initialization
    • 13.3.3 Reassembly SAR Shared Memory Control Structures
      • Table 138. Table of Values for RSM SAR Shared Memory Initialization (1 of 2)
  • 13.4 General Initialization
    • Table 139. Table of Values for General Control Register Initialization (1 of 2)
• 14.0 Electrical and Mechanical Specifications
  • 14.1 Timing
    • 14.1.1 PCI Bus Interface Timing
      • Table 141. PCI Bus Interface Timing Parameters (1 of 2)
      • Figure 141. PCI Bus Input Timing Measurement Conditions
      • Figure 142. PCI Bus Output Timing Measurement Conditions
    • 14.1.2 ATM Physical Interface Timing�UTOPIA and Slave UTOPIA
      • Table 142. UTOPIA Interface Timing Parameters 
      • Table 143. Slave UTOPIA Interface Timing Parameters
      • Figure 143. UTOPIA and Slave UTOPIA Input Timing Measurement Conditions
      • Figure 144. UTOPIA and Slave UTOPIA Output Timing Measurement Conditions
    • 14.1.3 System Clock Timing
      • Table 144. System Clock Timing (1 of 2)
      • Figure 145. Input System Clock Waveform
      • Figure 146. Output System Clock Waveform
    • 14.1.4 RS8235 Memory Interface Timing
      • Table 145. SRAM Organization Loading Dependencies
      • Table 146. SAR Shared Memory Output Loading Conditions
      • Table 147. RS8234 Memory Interface Timing 
      • Figure 147. RS8235 Memory Read Timing
      • Figure 148. RS8235 Memory Write Timing
    • 14.1.5 PHY Interface Timing (Standalone Mode)
      • Table 148. PHY Interface Timing (PROCMODE = 1)
      • Figure 149. Synchronous PHY Interface Input Timing
      • Figure 1410. Synchronous PHY Interface Output Timing
  • 14.2 Absolute Maximum Ratings
    • Table 149. Absolute Maximum Ratings
  • 14.3 DC Characteristics
    • Table 1410. DC Characteristics
  • 14.4 Mechanical Specifications
    • Figure 1411. 208-Pin Plastic Quad Flat Pack
    • Figure 1412. RS8235 Pinout Configuration
      • Table 1411. RS8235 Pinout (1 of 6)
• Appendix A : Boundary Scan
  • Table A-1. Boundary Scan Signals
  • Figure A-1. Test Circuitry Block Diagram
  • A.1 Instruction Register
    • Table A-2. IEEE Std. 1149.1 Instructions
  • A.2 BYPASS Register
  • A.3 Boundary Scan Register
  • A.4 Boundary Scan Register Cells
    • Table A-3. Boundary Scan Register Cells (1 of 6)
  • A.5 Electrical Characteristics
    • Table A-4. Timing Specifications
    • Figure A-2. Timing Diagram For Boundary Scan
  • A.6 Boundary Scan Description Language (BSDL) File