ACE9030 is a combined radio interface circuit and twin

synthesiser, intended for use in a cellular telephone.

The radio interface section contains circuits to monitor

and control levels such as transmit power in the telephone,
circuits to demodulate the frequency modulated signal to
audio, and a crystal oscillator with a frequency multiplier.

The Main synthesiser has normal and fractional-N modes

both with optional speed-up to select the desired channel. The
Auxiliary synthesiser is used for the transmit-receive offset
and for modulation.

Both sections are controlled by a serial bus and have

software selected power saving modes for battery economy.
The circuit techniques used have been chosen to minimise
external components and at the same time give very high
performance.

Fig.1 Pin connections - top view

ORDERING INFORMATION
Industrial temperature range
TQFP 64 lead 10 x 10 mm, 0·5 mm pitch
ACE9030M/IW/FP1N - shipped in trays and dry packed
ACE9030M/IW/FP1Q - tape & reel and dry packed
TQFP 64 lead 7 x 7 mm, 0·4 mm pitch
ACE9030M/IW/FP2N - shipped in trays and dry packed
ACE9030M/IW/FP2Q - tape & reel and dry packed

APPLICATIONS

AMPS and TACS Cellular Telephone

Two-way Radio Systems

RELATED PRODUCTS
ACE9030 is part of the following chipset:

ACE9020 Receiver and Transmitter Interface

ACE9040 Audio Processor

ACE9050 System Controller and Data Modem

VP64
FP64

FEATURES

Low Power Low Voltage (3·6 to 5·0 V) Operation

Serial Bus Controlled Power Down Modes

Simple Programming Format

Reference Crystal Oscillator

Frequency Multiplier for LO2 Signal

8·064 MHz Output for External Microcontroller

Main Synthesiser with Fractional-N Option

Auxiliary Synthesiser

Main Synthesiser Speed-up Options

FM Discriminator for 450 kHz or 455 kHz I.F. Signal

Radio System Control Interface

Part of the ACE Integrated Cellular Phone Chipset

TQFP 64 pin 0·4 mm and 0·5 mm pitch packages

Note: Pin 1 is identified by moulded spot
and by coding orientation

DOUT5

DOUT6

DOUT7

FIAB

FIA

VDDSA

VSSSA

FIMB

FIM

VSSD

PDI

PDP

RSMA

DECOUP

RSC

VDDD

DOUT0
VDDX
DOUT1
VDDA
VSSA
LO2
ADC1
ADC3A
ADC3B
ADC5
DOUT8
DAC2
DAC1
DOUT2
CIN1
CIN2

MODMP

MODMIN

TEST

PDA

VDDSUB

DOUT3
DOUT4
AMPP2

AMPN2

DAC3

AMPP1

AMPN1

AMP01

ADC2A
ADC2B

ADC4

AMP02

RXCD

TCHC

TCHB

ATA

AFCOUT

AUDIO

AFCIN

IREF

VSSL

VDDL

CLK8

C8B

VDDSUB2

ACE9030

Fig. 2 ACE9030 Simplified Block Diagram

POLLING

ADC

BUS

INTERFACE

LOCK

DETECT

TWIN

SYNTHESISER

DIGITAL

OUTPUTS

CRYSTAL

MULTIPLIER

CRYSTAL

OSCILLATOR

8 MHz

PLL

TRIMMING

DACs

AFC

MIXER

AMP &

LIMITER

AUDIO

DEMOD.

L.F. AMPS

ACE9030

Radio Interface and Twin Synthesiser

Supersedes February 1997 edition, DS4288 - 1.4

DS4288 - 2.0 January 1998

ACE9030

PIN DESCRIPTIONS

The relevant supplies (V

) and grounds (V

) for each circuit function are listed. All V

and V

pins should be used.

Pin No.

Name

Description

VDD

VSS

AMPO2

LF amplifier 2 output.

VDDA

VSSA

RXCD

Receive carrier detect (ADC1 comparator) output.

VDDL

VSSL

LATCHC

Synthesiser programme enable input.

VDDL

VSSL

LATCHB

Radio interface programme enable input.

VDDL

VSSL

DATA

Serial data; programming input, results output.

VDDL

VSSL

Clock input for programming bus and for I.F. sampling.

VDDL

VSSL

AFCOUT

Output from AFC amplifier after sampling.

VDDL

VSSL

AUDIO

Output from f.m. discriminator after filtering.

VDDA

VSSA

Feedback input to audio bandpass filter.

VDDA

VSSA

AFCIN

Input to AFC amplifier and f.m. discriminator.

VDDL

VSSL

IREF

Bias current input for radio interface, connect setting resistor to ground.

VSSA

VSSL

Ground for radio interface logic.

VDDL

Power supply to radio interface logic.

CLK8

Output clock at 8·064 MHz, locked to crystal.

VDDL

VSSL

C8B

8·064 MHz oscillator charge pump output and control voltage input.

VDDA

VSSA

VDDSUB2

Second connection for clean positive supply to bias substrate.

VDDA

VSSA

CIN2

Connection for crystal oscillator.

VDDL

VSSL

CIN1

Connection for crystal oscillator.

VDDL

VSSL

DOUT2

Digital control output 2.

VDDL

VSSL

DAC1

Analog control output 1.

VDDA

VSSA

DAC2

Analog control output 2.

VDDA

VSSA

DOUT8

Digital control output 8.

VDDA

VSSA

ADC5

Analog to digital converter input 5.

VDDA

VSSA

ADC3B

Analog to digital converter input 3B.

VDDA

VSSA

ADC3A

Analog to digital converter input 3A.

VDDA

VSSA

ADC1

Analog to digital converter input 1.

VDDA

VSSA

LO2

Output from crystal frequency multiplier.

VDDA

VSSA

Ground for radio interface analog parts.

VDDA

Power supply to radio interface analog parts.

DOUT1

Digital control output 1.

VDDX

Power supply to DOUT1 and DOUT2 switches.

DOUT0

Digital control output 0.

VDDX

VDDD

Power supply to synthesisers, except input buffers and the bandgap.

RSC

Fractional-N compensation bias current, resistor to ground.

VSSSA

DECOUP

Bandgap reference decoupling capacitor connection.

VDDSA

VSSSA

RSMA

Bias current for synthesiser charge pumps, resistor to ground.

VSSSA

PDP

Main synthesiser proportional charge pump output.

VDDD

VSSD

PDI

Main synthesiser integral charge pump output.

VDDD

VSSD

Ground for synthesisers, except input buffers and the bandgap.

FIM

Main synthesiser positive input from prescaler.

VDDSA

VSSSA

FIMB

Main synthesiser negative input from prescaler.

VDDSA

VSSSA

Ground for FIM and FIA input buffers and the bandgap.

VDDSA

Power for FIM and FIA input buffers and the bandgap.

FIA

Auxiliary synthesiser positive input from VCO.

VDDSA

VSSSA

FIAB

Auxiliary synthesiser negative input from VCO.

VDDSA

VSSSA

DOUT7

Digital control output 7.

VDDD

VSSD

DOUT6

Digital control output 6.

VDDD

VSSD

DOUT5

Digital control output 5.

VDDD

VSSD

MODMP

Modulus control output to prescaler - positive sense.

VDDD

VSSD

MODMN

Modulus control output to prescaler - negative sense.

VDDD

VSSD

TEST

Test input and output for synthesisers.

VDDD

VSSD

PDA

Auxiliary synthesiser charge pump output.

VDDD

VSSD

VDDSUB

Clean positive supply to bias substrate.

DOUT3

Digital control output 3.

VDDL

VSSL

DOUT4

Digital control output 4.

VDDL

VSSL

AMPP2

LF amplifier 2 positive input.

VDDA

VSSA

AMPN2

LF amplifier 2 negative input.

VDDA

VSSA

DAC3

Analog control output 3.

VDDL

VSSL

AMPP1

LF amplifier 1 positive input.

VDDA

VSSA

AMPN1

LF amplifier 1 negative input.

VDDA

VSSA

AMPO1

LF amplifier 1 output.

VDDA

VSSA

ADC2A

Analog to digital converter input 2A.

VDDA

VSSA

ADC2B

Analog to digital converter input 2B.

VDDA

VSSA

ADC4

Analog to digital converter input 4.

VDDA

VSSA

ACE9030

Fig.4 Typical VDD local decoupling networks without series resistors

Fig.5 Typical VDD local decoupling networks with series resistors

ABSOLUTE MAXIMUM RATINGS

Supply voltage from ground 0·3 V to + 6·0 V
(any V

to any V

)

Supply voltage difference 0·3 V to + 0·3 V
(any V

to any other V

)

Input voltage V

0·3 V to V

+ 0·3 V

(any input pin to its local V

and V

)

Output voltage V

0·3 V to V

+ 0·3 V

(any output pin to its local V

and V

)

Storage temperature 55

C to + 150

Operating temperature 40

C to + 85

tions V

DDSUB

and V

DDSUB2

must be the most positive of all V

at all times including during power on and off ramping. As the
current taken through these V

's is significantly less than

through the other V

's this requirement can be easily met by

directly connecting all V

pins to a common point on the

circuit board but with the decoupling capacitors distributed to
minimise cross-talk caused by common mode currents. If low
value series resistors are to be included in the V

connec-

tions, with decoupling capacitors by the ACE9030 pins to
further reduce interference, the V

DDSUB

and V

DDSUB2

pins should

not have such a resistor in order to guarantee that their
voltage is not slowed down at power-on. Power switches to
DOUT0 and DOUT1 are supplied from V

DDX

and are specified

for a total current of up to 40 mA so any resistor in the V

DDX

connection must be very low, around 1

, in order to avoid

excessive voltage drop; it is recommended that this supply
has no series resistor. These two methods are shown in circuit
diagrams, figures 4 and 5. In both circuits the main V

must

also have good decoupling.

These are not the operating conditions, but are the

absolute limits which if exceeded even momentarily may
cause permanent damage. To ensure sustained correct op-
eration the device should be used within the limits given under
Electrical Characteristics.

To avoid any possibility of latch-up the substrate connec-

Main VDD

VDDSUB

VDDSUB2

VDDL

VDDA

VDDX

VDDD

VDDSA

VDDSUB

VDDSUB2

VDDL

VDDA

VDDX

VDDD

VDDSA

Main VDD

No Resistor

Very
Small

ACE9030

Parameter

Min.

Typ.

Max.

Unit

Conditions

Power supply
Supply current, Radio Interface:
Sleep mode

2.3

2·7

XO, OSC8 on

Fully operating (excluding I

DDX

)

(see Note 1)

Supply current, Synthesisers: V

=5V

REF

= 10 MHz

Main and Auxiliary ON

MAIN

= 10 MHz

Main ON and Auxiliary in Standby

3.7

AUX

= 10 MHz

Main in Standby and Auxiliary ON

(see Note 2)

Main and Auxiliary in Standby, with Bandgap off

100

Supply current, Synthesisers:

REF

= 15 MHz

Main and Auxiliary ON

MAIN

= 16 MHz

Main ON and Auxiliary in Standby

AUX

= 90 MHz

Main in Standby and Auxiliary ON

(see Note 2)

Main and Auxiliary in Standby

100

Input and output signals
Logic input HIGH (LATCHC, LATCHB, DATA,
CL, and TEST)

0·7 x V

+ 0·3

Logic input LOW (LATCHC, LATCHB, DATA,
CL, and TEST)

0·3

+ 0·8

Input capacitance (signal pins)

Pin voltage

Input leakage (signal pins)

to V

Logic output HIGH (RXCD, DATA, AFCOUT,

0·5

TEST and DOUT2, 3 and 4)

External load:

Logic output LOW (RXCD, DATA, AFCOUT,

0·4

20 k

& 30 pF

TEST and DOUT2, 3 and 4)
Output ON level, DOUT0 and DOUT1

DDX

0·2

= 20 mA.

Output HIGH level, DOUT5, 6 and 7

2·3

2·9

= 80

Output LOW level, DOUT5, 6 and 7

0·3

= 0.2

Trimmed output level ON, DOUT8

3·35

3·55

= 135 to 400

Level difference, DOUT8 ON ADC reference

+ 15

Output level OFF, DOUT8

0.4

MODMP, MODMN output HIGH

/2 + 0·35

/2 + 1·0

= 10

MODMP, MODMN output LOW

/2 1·0

/2 0·35

= 10

Input Schmitt Hysteresis, pins CL, LATCHB,

0·3

LATCHC, DATA.
Analog circuits bias resistor on I

REF

@ 3·75 V

100

@ 4·85 V

ELECTRICAL CHARACTERISTICS

These characteristics apply over these ranges of conditions (unless otherwise stated):

AMB

= 40

C to + 85

C, V

= + 3·6 to + 5·0 V, GND ref. = V

D.C. Characteristics

Notes
1. The sleep current is specified with the crystal oscillator (XO) and the OSC8 oscillator and PLL running as these are normally needed to provide

the clock to the system controller.

2. The terms f

REF

, f

MAIN

, and f

AUX

refer to the frequencies of the Reference inputs (Crystal oscillator, pins CIN1 and CIN2), the Main synthesiser

inputs (pins FIM and FIMB) and the Auxiliary synthesiser inputs (pins FIA and FIAB) respectively.

ACE9030

Parameter

Min.

Typ.

Max.

Unit

Conditions

Synthesiser charge pump current
Current setting resistor R

SMA

Note 3

Current setting resistor R

Note 3

External capacitance on pin R

SMA

Ensures stable

External capacitance on pin R

bias current.

Bias current I

RSMA

(nominally 1·25V / R

SMA

)

28·8

35·2

SMA

= 39 k

Bias current I

RSC

(nominally 1·25V / R

)

28·8

35·2

= 39 k

Iprop(0) scaling accuracy, pin PDP

+10

@ 200

A. Note 4

Iprop(1) scaling accuracy, pin PDP

+10

@ 800

A. Note 4

Iint scaling accuracy, pin PDI

+10

@ 4 mA. Note 4

Icomp(0) scaling accuracy, pin PDP

+10

@ ACC x 0·2

Note 4

Icomp(1) scaling accuracy, pin PDP

+10

@ ACC x 0·8

Note 4

Icomp(2) scaling accuracy, pin PDI

+10

@ ACC x 4

Note 4

Iauxil scaling accuracy, pin PDA

@ 256

A. Note 4

Auxiliary Charge Pump,

+10

Note 5

Up or Down I

AUX

current variation

Main Charge Pumps,

+10

Note 6

Up or Down I

MAIN

or I

INTEGRAL

current variation

Iprop(0) or Iprop(1) setting from PDP pin

1·0

Iint setting from PDI pin

Icomp(0) or Icomp(1) setting from PDP pin

Icomp(2) setting from PDI pin

180

Iauxil setting from PDA pin

512

ELECTRICAL CHARACTERISTICS

These characteristics apply over these ranges of conditions (unless otherwise stated):

AMB

= 40

C to + 85

C, V

= + 3·6 to + 5·0 V, GND ref. = V

D.C. Characteristics (continued)

Notes
3. The circuit is defined with resistors R

SMA

and R

connected from pins RSMA and RSC to V

SSSA

but in most practical applications all V

pins

will be connected to a ground plane so R

SMA

and R

should then also be connected to this ground plane.

4. The charge pump currents are specified to this accuracy when the relevant output pin is at a potential of V

/2 and with R

SMA

= 39 k

, CN

= 200, L= 1, K = 5, R

= 19 k

The nominal value is set by external resistors and by programming registers, as defined in Table 6. Tolerances

in the internal Bandgap voltage and bias circuits are within the limits given for I

RSMA

and I

RSC

, the scaling accuracy of the multiplying DAC's

is within these limits given for Iprop(0), Iprop(1), Iint, Icomp(0), Icomp(1), Icomp(2), and auxil.

5. The Auxiliary charge pump output voltage is referred to as V

PDA

and the output current I

AUX

is the Up or Down current measured when

PDA

= V

/2.

The conditions for the variation limits for the Up current are:
either

AUX

= 128 or 256

and

0 < V

PDA

< V

0·5 V

AUX

= 512

and

0 < V

PDA

< V

0·65 V

The conditions for the variation limits for the Down current are:
either

AUX

= 128 or 256

and

0·5 V < V

PDA

< V

AUX

= 512

and

0·65 V < V

PDA

< V

6. The Main charge pump output voltage at pin PDP is referred to as V

PDP

and at pin PDI as V

PDI.

The output currents I

MAIN

and I

INTEGRAL

are the

up or down current Iprop(0), Iprop(1) or Iint measured when V

PDP

or V

DPI

= V

/2.

The conditions for the variation limits for the Up current are :

MAIN

= 100 to 1000

A or I

INTEGRAL

= 1 to 5 mA and 0 < V

PDP

< V

0·45 V

The conditions for the variation limits for the Down current are:

MAIN

= 100 to 1000

A or I

INTEGRAL

= 1 to 5 mA and 0·45 V < V

PDP

< V

ACE9030

Parameter

Min.

Typ.

Max.

Unit

Conditions

CONTROL BUS
Clock rate CL input

1008

kHz

Clock duty cycle CL input

, input data set-up time

See Fig. 7

, input data hold time

See Fig. 7

CWL

, t

CWH

, CL input pulse width (to bus logic)

400

600

See Fig. 7

, delay time, clock to latch

440

See Fig. 7

, latch pulse high time

230

See Fig. 7

, delay time, latch to clock

220

See Fig. 7

DSO

, output data set-up time

See Fig. 8

DHO

, output data hold time

See Fig. 8

, DATA line available to ACE9030

1200

See Fig. 8

, DATA line released by ACE9030

1200

See Fig. 8

, delay from received message to

cycles

See Figs. 8 and 10

transmitted response

of CL

Rise and Fall times, all digital inputs:

DIGITAL OUTPUTS
DOUT0 and 1 On time to V

0·2 V

100

100 nF load and from

DOUT0 and 1 Off time to > 1 M

100

LATCHB rising edge

DOUT5, 6 and 7 rise and fall times

30 pF load and to D.C.

DOUT8 rise and fall time

specification noise

A to D CONVERTER
Lowest transition, 0000 0000 to 0000 0001

0·07

0·15

0·23

Bandgap multiplier

Highest transition, 1111 1110 to 1111 1111

3·35

3·45

3·55

correctly trimmed

ADC conversion time (20 cycles of CL)

CL = 1008 kHz

Input scanning rate (CL

40)

25·2

kHz

CL = 1008 kHz

Integral Non-linearity

+ 1

LSB

Differential Non-linearity

0·8

+ 0·8

LSB

Power supply sensitivity

LSB/0.3V

0 to 10 kHz

CRYSTAL OSCILLATOR
Start-up time of crystal oscillator

Crystal effective series resistance (ESR)

Power dissipation in crystal

150

D to A CONVERTERS
Full scale output level, DAC1, DAC2 & DAC3

3·35

3·45

3·55

Bandgap multiplier

Zero scale output level, DAC1

1·0

1·2

trimmed to nominal

Zero scale output level, DAC2 & DAC3

0·3

0·5

reference voltage

Integral Non-linearity

+ 1

LSB

Differential Non-linearity

0·5

+ 0·5

LSB

Output wideband and clock noise:
50 Hz to 1·1 MHz, flat integration

rms

Power supply rejection ratio

50 Hz to 25 kHz.

Settling time to within 10% of end of step

DAC1 and DAC2

(DAC3 with external 15 k

resistor)

10 pF load

Output load capacitance, DAC1 and DAC2

100

Output load capacitance, DAC3

To guarantee stability

Internal series resistor, DAC1 and DAC2

DAC3 output current, sink or source

1·0

ELECTRICAL CHARACTERISTICS

These characteristics apply over these ranges of conditions (unless otherwise stated):

AMB

= 40

C to + 85

C, V

= + 3·6 to + 5·0 V, GND ref. = V

A.C. Characteristics

ACE9030

ELECTRICAL CHARACTERISTICS

These characteristics apply over these ranges of conditions (unless otherwise stated):

AMB

= 40

C to + 85

C, all V

= + 3·6 to + 5·0 V, GND ref. = V

A.C. Characteristics (continued)

Note
7. AUDIO signal quality is measured with feedback components as shown in figure 18 and with 500 mV peak to peak input to AFCIN.

Discriminator gain is set with D = 3 and M = 40 and V

= 3·75 V and a crystal at 14·85 MHz. SINAD is defined as the ratio of wanted signal

to all unwanted output, measured simultaneously with filters. The hum and noise figure is defined as the ratio of output power at AUDIO when
AFCIN is unmodulated to the output power when AFCIN is driven as specified above.

Parameter

Min.

Typ.

Max.

Unit

Conditions

LOW FREQUENCY AMPLIFIERS (1 and 2)
Voltage Gain

1200

2800

Input Offset

Open loop input resistance

Open loop output resistance

Unity Gain bandwidth

MHz

Input bias current, inverting input

200

Power supply rejection at 120 Hz, 10 kHz

Output voltage maximum

DDA

0·2

10 k

to 6ND

Output voltage maximum, as a comparator

DDA

0·1

10 k

to 6ND

Output voltage minimum level

0·2

10 k

to 6ND

Output voltage minimum level

0·1

10 k

to 6ND

Common mode input range (LF1 1)

SSA

2.5

Common mode input range (LF1 2)

SSA

DDA

Output slew rate

0.15

0.25

Output load capacitance

8 MHz OSCILLATOR and PLL
OSC8 centre frequency

8·064

MHz

OSC8 VCO sensitivity

MHz/V

OSC8 charge pump output current

CLK8 output load, resistive:

100

capacitive:

CLK8 output amplitude

0·8

1·0

2·4

pk-pk

CLK8 total output jitter

500

0 - 3 kHz

Start-up time at power-on, to default settings

With a loop filter as
described in fig. 17

Lock time to within 125 ppm, after
reprogramming set-ups

AFCIN F.M. DISCRIMINATOR and AFC
AFCIN input signal level

0·05

2·5

pk-pk

AFCIN input impedance, resistive:

capacitive:

Input frequency

400

500

kHz

Input signal to integrated noise ratio

I.F.

15 kHz.

Input Schmitt Hysteresis

AUDIO signal SINAD, psophometric, note 7

1 kHz tone at 3 kHz

AUDIO signal hum and noise, note 7

peak deviation on

AUDIO output signal level, note 7

195

260

rms

AFCIN input at I.F.

AFCOUT load

AFCOUT duty cycle

AFCOUT rise and fall times

ACE9030

ELECTRICAL CHARACTERISTICS

These characteristics apply over these ranges of conditions (unless otherwise stated):

AMB

= 40

C to + 85

C, all V

= + 3·6 to + 5·0 V, GND ref. = V

A.C. Characteristics (continued)

Note
8. To simplify single ended drive there is a resistor between FIA and FIAB and another between FIM and FIMB. In this mode the inputs should

drive FIA or FIM with D.C. coupling and the other inputs FIAB and FIMB should be decoupled to ground by external capacitors.

Parameter

Min.

Typ.

Max.

Unit

Conditions

LO2 Multiplier
Amplitude

235

500

rms

Circuit as in fig. 15,

Reference frequency content of output

-10.5

dBc

2nd, 4th harmonic content of output

-13.5

dBc

5th harmonic of output

-15

dBc

6th and higher harmonics in output

-20

dBc

SYNTHESISERS
Reference divider
Reference divider input frequency

MHz

Drive level into CIN1 from external oscillator

400

pk-pk

With crystal oscillator
powered down

CIN1 input capacitance

CIN1 input resistance

Auxiliary synthesiser
FIA input frequency

135

MHz

May be a sinewave

Rise and fall times of inputs

Timing Skew between FIA and FIAB

See Fig. 6

10%

signal Both maxima

period must be met

FIA, FIAB differential signal level with both

180

pk-pk

Each input, 5 to 50 &

sides driven

99 to 135 MHz

100

pk-pk

Each input,
50 to 99 MHz

FIA single input drive level with FIAB

360

pk-pk

One input, 5 to 50 &

decoupled to V

99 to 135 MHz

200

pk-pk

One input,
50 to 99 MHz

FIA, FIAB common mode range

1·7

0·7

= 3.6V

FIA, FIAB common mode range

2.8

0·85

= 5V

FIA, FIAB input capacitance

FIA, FIAB differential input resistance

Note 8

Auxiliary Synthesiser comparison frequency

MHz

Main Synthesiser
FIM input frequency

MHz

Rise and fall times of inputs

FIM - FIMB Timing Skew

See Fig. 6

10%

signal Both maxima

period must be met

FIM, FIMB differential signal level

100

pk-pk

Each input,

with both sides driven.

4 to 20 MHz

FIM single input drive level

200

1000

pk-pk

One input,

with FIMB decoupled to V

4 to 20 MHz

FIM, FIMB common mode range

1·7

0·7

=3.6V

FIM, FIMB common mode range

2·8

0·85

=5V

FIM, FIMB input capacitance

FIM, FIMB differential input resistance

Note 8

Delay FIM rising to MODMP/MODMN changing

Main Synthesiser comparison frequency

MHz

ACE9030

FUNCTIONAL DESCRIPTION - CONTROL BUS

The functions of the ACE9030 fall into two separate

groups, the Radio Interface and the Synthesisers.

The common control bus splits the input strings differ-

ently for these two sections so this bus operation is described
first as an introduction to the available features.

All functions are controlled by a serial bus; DATA is a bi-

directional data line, to input all control data and to output the
results of measurements in the Radio Interface section, CL is
the clock, and LATCHB and LATCHC are the latch signals at
the end of each control word for either the Radio Interface or
the Synthesiser section respectively.

CL is a continuously running clock at typically 1·008 MHz,

and all incoming and output data are latched on rising edges
of this clock. The controller should clock data in and out on
falling clock edges. For bus control purposes the frequency of

CL may be widely varied and this clock does not need to be
continuous, however, the sampled I.F. signal AFCOUT, the
Polling ADC, and the Lock Detect Filter also use CL as the
sampling clock. In systems where any of these are required
the clock CL is constrained to be 1·008 MHz and to be
continuous.

To ensure clean initialisation the clock CL should give at

least 8 cycles before the power-up command and similarly to
set the control logic to known states there should be 8 cycles
of CL after a power-down command.

During normal operation there should be at least 30

cycles of CL between latch pulses, 24 for the data bits (see
figures 9,10 & 11) plus 6 extra. This minimum becomes 36
cycles if the extended synthesiser programming command
(A2) is used.

Radio Interface Bus - Receive

Fig.9 Radio Interface receive bus timing

The received data is split into three bytes, where DATA1

normally contains a value to be loaded into a destination set
by DATA2 and DATA3. When a command does not need to
put any information into byte DATA1 a preamble xx1010xx is
recommended to fill this byte. It is possible to set-up several
features in one bus operation and to allow this the decoding
only acts on single or selected bits; the others are given as "x"
in the block descriptions. Two bits of DATA2 also set the type
of command, with four options:

DATA2

Type of

Comment

bit 7

bit 6

Command

SLEEP

No reply

NORMAL

Send requested data

SET-UP

No reply

TEST

No reply

and the CLK8 output driver will be active, and are used to clock
the microcontroller. To reduce the supply current to its mini-
mum in Sleep the synthesisers must also be powered down,
by a Word D message with DA and DM both set HIGH as
described under Synthesiser Bus - Receive Only. During
Sleep all set-up values are retained unless changed by a Set-
up command. The exit from Sleep is by any Normal command.

Normal commands will end Sleep mode but are primarily

used to change the operating mode of the cellular terminal or
to request ADC data. The ACE9030 will output data onto the
serial bus after a Normal command.

Set-up commands are used to adjust various operating

parameters but can also initiate a logic restart if DATA3 bits 1
and 0 are both "1" so for routine changes of set-ups these bits
should always be 00.

Test mode is included only for use during chip manufac-

ture.

Sleep mode is selected to put the cellular terminal into a

very low power state for when it is "Off" and neither waiting for,
nor setting up a call. In Sleep only the crystal and 8·064 MHz
oscillators, DAC1 and DAC2, the OSC8 phase locked loop,

The Sleep Command - DATA2 bits 7, 6 = 00

DATA1

DATA2

DATA3

xx1010xx

00xxxxxx

xxxxxxxx

DATA

LATCHB

DATA1

DATA2

DATA3

7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0

ACE9030

Summary of Normal Commands - DATA2 bits 7, 6 = 01

Normal commands are always a request for data; the ADC registers to be read are defined by Y1 and Y0 in DATA3. A normal

command will also end Sleep mode.

BIT

EFFECT when at 0

EFFECT when at 1

DATA2:

With DATA2:6 defines command type

With DATA2:7 defines command type

Discriminator powered down

Discriminator active.

Load Lock threshold register from DATA1:7-1

DAC3 powered down

DAC3 active

Load DOUT7-0 from DATA1:7-0

Load DAC3 from DATA1:7-0

Not used

DATA3:

Not used

LO2 multiplier powered down

LO2 multiplier active

Set DOUT8 to OFF

Set DOUT8 to ON, to output the ADC reference voltage

Load ADC1 comparator from DATA1:7-0

Load DAC1 from DATA1:7-0

Load DAC2 from DATA1:7-0

Y1 Decode with DATA3:0 for Polling ADC register read

Y0 Decode with DATA3:1 for Polling ADC register read

BIT

EFFECT when at 0

EFFECT when at 1

DATA2:

With DATA2:6 defines command type

With DATA2:7 defines command type

Not used

Set OSC8 VCO range from DATA1:5-0

Set OSC8 VCO offset from DATA1:5-0

Select input A for ADC3

Select input B for ADC3

Select input A for ADC2

Select input B for ADC2

OSC8 off

OSC8 on

DATA3:

Crystal oscillator off

Crystal oscillator on

Bandgap off - use external reference

Bandgap on

Set discriminator divisors from DATA1:7,6
and lock detect period from DATA1:5
and OSC8 divisors from DATA1:2-0

Set bandgap trim from DATA1:7-0

Not used

Do a restart if both DATA3 bits 1 and 0 are at 1

Summary of Set-up Commands - DATA2 bits 7, 6 = 10

ACE9030

Radio Interface Bus - Transmit

The output Preamble word begins with a fixed pattern

1 0 1 0 and then includes the source code number (Y1, Y0) for
the Result words and the status of the Lock Detect from the
synthesiser, all as described in the section Polling A to D
Converter.

The ACE9030 only drives the bus in response to a request

for data by a Normal command as described above. To avoid
any bus contention, there is a delay from the end of a data
request to the start of the response, see figure 10. The data will
start on the fifth rising edge of CL after the rising edge of
LATCHB.

Fig.10 Radio Interface transmit bus timing

Synthesiser Bus - Receive Only

The overall format to control the synthesiser is basically the
same as for the Radio Interface. There is an option of a 32 bit

sequence for the A word. The width of the LATCHC pulse is
used to set the duration of speed-up mode when changing
channels.

Fig.11 Synthesiser bus timing

DATA3

LATCHB

PREAMBLE

RESULT1

RESULT2

7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0

1 2 3 4 5

DATA (WORD A)

DATA (WORD B)

DATA (WORD C)

DATA (WORD D)

DATA (WORD A2)

LATCHC

DURATION OF MAIN SYNTHESISER SPEED-UP MODE

DATA (DUMMY WORD)

- ONLY USED TO ALLOW

LATCHC TO REMAIN HIGH

0 1 0 1

FMOD

0 0 0 1

1 0 0 1

0 0

7 6 5 4 3 2 1 0 11 10 9 8 7 6 5 4 3 2 1 0 2 1 0

1 0 3 2 1 0 7 6 5 4 3 2 1 0 3 2 1 0

11 10 9 8 7 6 5 4 3 2 1 0

not used

1 0 1 0 11 10 9 8 7 6 5 4 3 2 1 0

7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 11 10 9 8 7 6 5 4 3 2 1 0 2 1 0

not used - any data may fill space

TEST

ACE9030

Data is accepted by the circuit on the rising edge of

LATCHC. Programmable divider ratios will be changed at their
next re-load, at up to a whole comparison period after the
LATCHC edge.

Normal channel changes require only word A but if it is

necessary to maintain exactly uniform loop dynamics the
parameter CN (see Main Synthesiser - Normal Mode) must
also change. This can be achieved by either sending a word
B for the CN parameter before word A for the frequency or
alternatively the extended command A2 can be used to
combine both in one long word. This A2 mode is not supported
by the ACE9050 as it is not necessary for most cellular
terminals.

If Word B is reprogrammed, the new values do not

become effective until the next Word A is written. This
prevents any spurious conditions during a channel change.

The LG bit in Word D sets whether A or A2 mode is to be

used, 0 for A and 1 for A2.

Speed-up drive is active for the duration of the LATCHC

pulse that loads the A or A2 word and if it is required the pulse
will typically be hundreds of cycles of CL in duration.

In some applications the system performance can be

improved by holding LATCHC at HIGH to minimise clock noise
on the synthesisers. LATCHC also controls Speed-up mode
and so to exit speed-up mode after a channel change the
LATCHC must be driven LOW and then a dummy command
can be added to get LATCHC back to HIGH. This dummy
command should be a non-functional word formed by setting
the last four bits to 1111 as in figure 11; the value or the number
of the data bits before the four 1's are of no significance so the
typical schemes are to send either a standard 24 bit message
ending 1111 or a special 4 bit only message of 1111 and in
both cases the LATCHC is kept HIGH until the next channel
change.

The TEST bits in Word B must be set to 0000 for normal

operation and the first two bits in Word B should be set to 00
to be sure of compatibility with future variants.

Summary of Synthesiser Programming

BIT STRING

Range of values

FUNCTION

3 - 4095

Main synthesiser down count; prescaler at lower modulus.

1 - 255

Main synthesiser up count; prescaler at higher modulus.

0 - 7

Main synthesiser fractional increment numerator.

TEST

0000

This state must be selected in every Word B for normal operation.
TEST pin will be held LOW to screen adjacent PDA pin.

Other test modes are for use during chip manufacture only.

0 - 255

Main charge pump current scaling coefficient.

0 - 15

Integral charge pump speed-up mode multiplying factor.

0 - 3

Proportional charge pump speed-up mode exponent, giving x 2, x4, x 8
or x 16 current.

3 - 4095

Auxiliary synthesiser VCO divider ratio.

8 - 4095

Reference divider ratio.

0 - 3

Main synthesiser comparison frequency select.

0, 1

Main synthesiser in standby mode if DM set HIGH.

0 - 3

Auxiliary synthesiser comparison frequency select.

0, 1

Auxiliary synthesiser in standby mode if DA set HIGH.

FMOD

0, 1

Fractional-N denominator,

's when at "0" or

's when at "1".

0, 1

Control bus mode select - Word A if LOW or Word A2 if HIGH.

ACE9030

FUNCTIONAL DESCRIPTION - BLOCKS IN THE RADIO INTERFACE

Power-On Reset Generator

To ensure a tidy start-up there is an internal power-on

detector to initialise various registers.

This initialisation leaves the Radio Interface in Sleep

mode with the crystal and 8·064 MHz oscillators running. The
8·064 MHz PLL will be set up for a 15·36 MHz crystal as a
default to ensure the microprocessor is not clocked too fast
during the start up sequence. Any Normal command can be
used to change to active operation.

A software Restart command can be sent to force the

Radio Interface to the power-on reset state. This command is:

DATA1

DATA2

DATA3

xxxxxxxx

10xxxxxx

xxxxxx11

Digital Outputs

The nine digital outputs, DOUT8 to DOUT0, are used to

control the status or function of radio subsections external to
the ACE9030 and are controlled by a Normal type command
with a logic "1" setting the output to HIGH or ON and a logic "0"
giving LOW or OFF.

Outputs DOUT0 and DOUT1 are power switches from

DDX

to supply Front-End circuits. Both are forced to OFF in

Sleep mode.

Fig. 12 Lock Detect Block Diagram

Lock Detect Filter

The Lock Detect Filter processes the phase errors in both

synthesisers to give a clean signal to put onto the bus as a
single bit added to the ADC read response.

In the synthesiser section of the ACE9030 the time

differences between the active edges of the outputs of the
programmable dividers and of the reference divider are com-
pared with a window of two cycles of the reference clock, XO,
from the crystal oscillator. If a loop has a time difference, or
phase error, larger than this window then that loop is deemed
unlocked and its lock signal is held low for a whole comparison

period, giving a Main Lock and an Auxiliary Lock signal. When
both synthesisers are active the error signals are combined by
an AND function to give the internal signal LOCK. If either
synthesiser is powered down its lock is disregarded and if both
are powered down the ACE9030 will always give LOCK at
LOW, the unlocked state, to be output on the bus. This final
signal LOCK is normally HIGH to indicate locked loops but will
pulse low for one or more comparison periods when an active
synthesiser is unlocked.

Outputs DOUT2 to DOUT4 are logic level outputs to

control various functions in the cellphone. DOUT2 and
DOUT3 are forced to HIGH and DOUT4 is forced to high
impedance in Sleep mode.

Outputs DOUT5 to DOUT7 are low current outputs with

reduced voltage swing to control power down in the ACE9010
and ACE9020. All three are forced to LOW in Sleep mode.

Output DOUT8 can be driven by the buffered Band-gap

based ADC reference voltage and is included for test and
setting-up purposes, as well as for driving a temperature
sensing thermistor read through one of the ADC channels.
DOUT8 is forced to high impedance in Sleep mode.

The control formats are Normal commands:

DATA1

DATA2

DATA3

01xxx1xx

xxxxxxxx

where DATA1 bits 7 to 0 control DOUT7 to DOUT0 respec-
tively when enabled by DATA2 bit 2, and:

DATA1

DATA2

DATA3

xxxxxxxx

01xxxxxx

xx D

xxxxx

where DATA3 bit 5 controls DOUT8 directly.

MAIN COMP.
FREQUENCY

MAIN PROG.
DIVIDER

AUX. PROG.
DIVIDER

AUX. COMP.
FREQUENCY

COMPARE
TIMING

ADD +2X0
WINDOW

CL
(1.008 MHz)

504 kHz

LOCK

LEVEL SET
FROM BUS

TO BUS

THRESHOLD
REGISTER

COMPARATOR

7 BIT
COUNTER

WINDOW
COUNT: 80/84

: 2

WINDOW SET FROM BUS

START/STOP

ACE9030

Fig. 13 Typical Lock Detect Waveforms

Pulses can occur on the LOCK signal at a rate up to the

higher of the Main and Auxiliary comparison frequencies, and
typically either 12·5 kHz for ETACS (50 kHz if Fractional-N is
used) or 30 kHz for AMPS so some extra filtering is needed to
get a clean lock indicator.

LOCK is filtered by first sampling at 504 kHz (the bus clock

CL divided by two) and then counting the number of HIGH
samples in a pre-determined period. There are two selections
available for this counting period, approximately 160

s (2

periods of 12·5 kHz or 8 of 50 kHz) or approximately 167

s (5

periods of 30 kHz) which are set by a second counter, also
running at 504 kHz and with a fixed modulus of 80 or 84. LOCK
is stable for each comparison period so the counts for each
comparison frequency are always in blocks of 40 for 12·5 kHz,
10 for 50 kHz or 16 for 30 kHz.

The value in the LOCK sample counter is compared with

a threshold previously set by another bus command, to
determine if the loops are locked, the result is then output as
the last bit in the pre-amble word in the response to a Normal
command, before the ADC levels are given, as described in
the section Polling A to D converter.

The filter period is selected by the following Set-up

command where DATA1 bit D

sets the period to one of the two

values to suit whichever cellular system is to be used:

DATA1

DATA2

DATA3

xx D

xxxxx

10xxxxxx

xx1xxx00

DATA1:5 = 0 sets 160

s for ETACS (Window count = 80) and

DATA1:5 = 1 sets 167

s for AMPS (Window count = 84).

The threshold is set by a Normal command:
DATA1 bits D

to D

form a 7 bit binary number in the range

Polling A To D Converter

A five channel polling Analog to Digital Converter is used

to monitor various analog levels, such as Received Signal
Strength, Transmitter Power, Temperature and Battery Volt-
age. The 8 bit ADC has a nominal range of 0·15 V to 3·45 V for
codes 00 to FF and is connected to each input channel, ADC1
to ADC5, in turn by the scanning logic. The results are put into
individual registers for reading by the microcontroller. The
successive approximation technique is used, with the bus
clock CL controlling both the timing of the conversion and also
the polling around the inputs. The voltage reference for the
ADC is shared with the three DAC's and is derived from the
bandgap voltage through a trimming multiplier which can be
monitored on DOUT8 and is described in the section Band-
Gap Reference. Some channels are scanned more frequently
than others, with the pattern:

5, 1, 5, 2, 5, 1, 5, 3, 5, 1, 5, 4,

which repeats continuously. With clock CL at its normal
1008 kHz frequency, the scanning rates are 12·6 kHz for
ADC5, 6·3 kHz for ADC1 and 2·1 kHz for ADC2, 3 and 4.

Channels 2 and 3 each have two options, 2A, 2B and 3A,

3B as pins to connect to alternative points to monitor. The
selection is by a Set-up command:

DATA1

DATA2

DATA3

xxxxxxxx

10xxx D

xxxxxx00

where DATA2 bit D

selects ADC3B when HIGH or ADC3A

when LOW for measurement by channel 3, and DATA2 bit D

selects ADC2B when HIGH or ADC2A when LOW for meas-
urement by channel 2.

0 to 127, which is the threshold value to be loaded. The window
period of 80 or 84 clock cycles sets the maximum count value
that can be found; the effect of unlock is to reduce the actual
count by at least one comparison period's worth of samples
40, 10, or 16 so a suitable threshold can easily be chosen.
Assuming that the maximum sensitivity is required the thresh-
old should be set at just above the maximum count (80 or 84)
minus the effect of one unlock count (40, 10, or 16), to give
suggested thresholds of at least 42 (for 12·5 kHz) or 72 (for 50
kHz) or 70 (for 30 kHz). In each case any convenient number
between these suggestions and the maximum count may be
used as the selection is not critical.

DATA1

DATA2

DATA3

01x1xxxx

xxxxxxxx

INDICATES
ACTIVE EDGE
IN THE PHASE
COMPARATOR

LOCK

ADEQUATE LOCK

UNLOCK

+ 2 X
XO

REF.CLOCK
(XO)

COMP. FREQ.
(MAIN)

TIME WINDOW
(MAIN)

PROG. DIVIDER
(MAIN)
MAIN LOCK

AUX.LOCK,
DERIVED SIMILARLY

LOCK

ACE9030

The ADC data in the five registers is read in response to

a Normal command, with the two results to be output being
selected by two bits of DATA3:

DATA1

DATA2

DATA3

xxxxxxxx

01xxxxxx

xxxxxxY

where Y

are decoded to select:

Data requested

ADC5 & ADC1

ADC5 & ADC2A/B

ADC5 & ADC3A/B

ADC5 & ADC4

The requested data is then clocked out after a fixed delay,

with a preamble followed by the two results:

PREAMBLE

RESULT 1

RESULT 2

1010 Y

0 L

RRRRRRRR

The Y

code is output to confirm the data selection and

is the same as in the Normal command that requested the
data, detailed above, L is the Lock Detect status from the Lock
Detect Filter, and the two results are in the order ADC5 in
RESULT 1 and ADC1, 2, 3, or 4 in RESULT 2.

The level in the ADC1 register is continuously compared

with a threshold number such that if ADC1 is above this
threshold the output pin RXCD is driven HIGH and can be
used to indicate the presence of a received carrier. The
threshold is set by a Normal command on the bus, with the
value in DATA1:

IREF Bias Circuit

To set the operating current for several blocks in the Radio

Interface there is a bias pin I

REF

which should be connected to

the ground plane (V

pins) via a resistor whose value de-

pends on the supply voltage, 68 or 100 k

for 3·75 V or 4·85 V

nominal V

. The current into this pin is then mirrored to the

various functional blocks. To reduce the noise on this bias a
capacitor can be added from the IREF pin preferably to the
supply or alternatively to a good ground. A value of 82 nF
offers a good compromise between noise rejection and
power-up time.

D to A Converters

There are three 8-bit DAC's with buffered outputs in the

ACE9030.

DAC1 and DAC2 have a high zero offset, a nominally

15 k

output series resistor, and are stable when driving up to

a 100 nF load capacitance.

DAC3 has a low zero offset and no output resistor. In

order to guarantee stability the capacitance of the load on
DAC3 must be no more than 30 pF.

The output resistors on DAC1 and DAC2 are used to form

part of a low pass filter and these DAC's are intended to be
used to adjust the crystal frequency as given below under
Crystal Oscillator.

DATA1

DATA2

DATA3

DDDDDDDD

01xxxx D

xxxx D

DATA1

DATA2

DATA3

xxxxxxxx

01xx D

xxx

xxxxxxxx

The level for each DAC is set by a Normal command:

where the data in DATA1 is loaded into DAC1 if DATA3 bit D

is HIGH, into DAC2 if DATA3 bit D

is HIGH, or into DAC3 if

DATA2 bit D

is HIGH.

DAC1 and DAC2 remain active during Sleep mode but the

outputs are driven with reduced current capability; this will
slightly reduce the accuracy and will significantly increase the
settling time to any level change. DAC3 is powered down in
Sleep mode.

To power down DAC3 outside of Sleep mode, a Normal

command may be used:

where DAC3 is active if DATA2 bit D

is HIGH or powered

down if DATA2 bit D

is LOW.

L.F. Amplifiers

Two identical low frequency amplifiers are provided; one

has inputs AMPP1 and AMPN1 driving output AMPO1, the
other has inputs AMPP2 and AMPN2 driving output AMPO2.

A typical use for AMP1 is as a linear amplifier to buffer the

DAC3 output to drive the transmit power control in a software
controlled loop with a power sensor input to ADC5.

AMP2 is typically used as a comparator to detect transmit

power independent of the software as a system integrity
check. The System Controller can then gate the presence of
transmitter power on AMPO2 with the absence of received
carrier on RXCD to detect a non-valid status and re-initialise
the system.

Crystal Oscillator

A crystal oscillator maintaining circuit is provided on pins

CIN1 and CIN2 for use with a crystal at 12·8, 14·85 or
15·36 MHz depending on the cellular system chosen. The
circuit is designed for a crystal cut for a 20 pF load and with an
ESR less than 25

. To ensure reliable fast start times for this

oscillator the bias current is increased significantly for the first
2047 cycles of oscillation after power-up, a restart command
or after an oscillator ON command and then automatically
changes to the lower normal level. The normal level has been
chosen to still guarantee start-up if the circuit should be
stopped by some external interference but to consume less
power than the fast start mode.

The buffered internal output of this oscillator is used in

several sections of the chip and is referred to as XO in this data
sheet. This oscillator can be trimmed by using DAC1 and
DAC2 to control varicap diodes and so to pull the frequency,
the two DAC's may be used to give separate AFC and
temperature compensation. A typical external circuit is shown
in figure 14. Each DAC provides typically 30ppm tuning range.

If preferred, an external oscillator can be used by driving

into CIN1 with CIN2 left open circuit. To allow this external
drive the internal oscillator should be shut down by using a
Set-up command with DATA3 bit D

at LOW. The internal

oscillator is switched on at power-up, at restart, and by a Set-
up command with DATA3 bit D

at HIGH:

DATA1

DATA2

DATA3

DDDDDDDD

01xxxxxx

xxx1xxxx

DATA1

DATA2

DATA3

xxxxxxxx

10xxxxxx

xxxxx00

ACE9030

DAC2

CIN1

CIN2

1 nF

47 pF

C1
82 pF

C2
82 pF

BB639

BB535

VSSA

47 pF

100 pF

LO2

470

MIXER

LOAD

6 k8

TUNED CIRCUIT AT
HARMONIC, VALUES
GIVEN FOR 44.55 MHz

VDDA

ACE9030

220 nH

DRIVE

FROM

CRYSTAL
OSC.

5.6 pF

Crystal

Multiplier

LO2

1st I.F.

2nd I.F.

14·85 MHz

x 3

44·55 MHz 45·00 MHz 450 kHz

15·36 MHz

x 5

76·80 MHz 77·25 MHz 450 kHz

Fig. 14 Crystal Oscillator Trimming Circuit with Typical

Component Values

Crystal Multiplier for LO2

To mix the first intermediate frequency signal down to the

second IF a second local oscillator is needed. In the ACE9030
there is a crystal frequency multiplier to generate this signal by
squaring the crystal oscillator waveform and selecting the
desired harmonic. To multiply the crystal frequency by 3 or 5
output LO2 is driven at the reference frequency with a 1:1 mark
space ratio. This ratio of 1:1 is chosen to minimise the even
harmonics, especially the second and fourth. A tuned circuit
will pick off the required harmonic. ACE9030 is specified with
the external components shown in Figure 15 giving 44.55 MHz
derived from 14.85 MHz crystal. The 6.8k

resistor and 5.6pF

capacitor represent the input impedance of a typical IF
amplifier LO input.

Typical performance for noise power measured in the

adjacent channels,16 kHz wide at 25 kHz offset is 70 dBc.

To power down the multiplier if it is not required, a Normal

command can be used with DATA3 bit D6 set to LOW, to set
the multiplier power on DATA3 bit D6 should be set to HIGH:

Typical frequencies generated by the multiplier are:

Fig. 15 Basic Circuit of the Crystal Multiplier

Band-Gap Reference

A band-gap voltage reference is used to set levels in the

ADC, in the DAC's and the currents in the synthesiser charge
pumps. This voltage is smoothed by an external decoupling
capacitor on the DECOUP pin.

The voltage derived for the ADC full range reference can

be monitored through pin DOUT8. The Radio Interface DAC
reference is nominally the same as the ADC reference and it
can be monitored independantly of DOUT8 by setting DAC3
(the low output impedance DAC) to full scale.

To power down the band-gap reference to allow the use

of an external reference voltage on pin DECOUP the following
Set-up command can be used:

where the band-gap is powered down if DATA3 bit D6 is LOW
or is active if DATA3 bit D6 is HIGH.

The band-gap voltage multiplier for the ADC and DAC

reference (nominally 3·45 V) can be adjusted by a Set-up
command to correct for production spreads:

DATA1

DATA2

DATA3

DDDDDDDD

10xxxxxx

xxx1xx00

DATA1

DATA2

DATA3

xxxxxxxx

10 xxxxxx

x D

xxxx00

DATA1

DATA2

DATA3

xxxxxxxx

01xxxxxx

x D

xxxxxx

where the value in DATA1, G

BG,

sets the gain from band-gap

to output voltage according to the approximate equation:

For a typical V

of 1·2 V the number is approximately 144

(= 90

HEX

) and for a typical V

of 1·3 V the number is approxi-

mately 70 (= 46

HEX

) and a suitable trimming pattern can be

chosen.

OUT

(430 x G + 355 x 10

)

(145 x 10

)

ACE9030

8·064 MHz Oscillator

Fig. 16 OSC8 Block Diagram

Table 2

Command

Crystal

PLL comp.

OSC8

Exact CLK8

Error

Data D2 D1 D0

frequency

divider

freq. (kHz)

divider

output (MHz)

(ppm)

1 0 0

12·8 MHz

100

128

8·064

0 1 1

14·85 MHz

825

448

8·064

1 0 1

14·85 MHz

337

44·065281

183

8·0639466

1 1 0*

15·36 MHz

120

128

8·064

* Power up default

An 8·064 MHz oscillator OSC8 is provided to drive the

ACE9050 System Controller through pin CLK8. ACE9050
further drives the ACE9040 Audio Processor and the CL bus
clock via a

8 divider. OSC8 is locked to the crystal oscillator

by a phase locked loop with an external filter on pin C8B.

This loop can be programmed by a Set-up command to

give the correct output frequency with any of the normally used
crystals. Note that the same Set-up command uses DATA1 bit
D

for the lock logic and bits D

and D

for the Discriminator

programming:

DATA1

DATA2

DATA3

xxxxx D

10xxxxxx

xx1xxx00

where D

act as in table 2. At power-on reset the setting

is D

= 110, the values for a 15·36 MHz crystal, so that

the microcontroller is never clocked too fast with any of the
crystals and can then send the Set-up message to set D

to the correct levels.

With a 14·85 MHz crystal it is not possible to both use a

high comparison frequency and get the exact 8·064 MHz
output, so two options are provided. The lower comparison
frequency will give the output exactly correct but will need
larger capacitors in the loop filter and the higher option allows
smaller capacitors and can improve close-in phase noise by
having a larger loop bandwidth, but gives a very small fre-
quency error - this error should have no effect in a practical
cellular terminal.

A Sleep command will not change the status of OSC8; if

enabled it will remain active when put into Sleep mode and
when returning to Normal mode. If the OSC8 oscillator is not

required it can be switched off by a Set-up command:

DATA1

DATA2

DATA3

xxxxxxxx

10xxxxx D

xxxxxx00

where DATA2 bit D0 at LOW gives OSC8 OFF or DATA2 bit
D

at HIGH gives OSC8 ON.

To allow for design and manufacturing tolerances the

VCO can be trimmed by two set-up commands, each of which
loads a 6 bit value in DATA1 into a control register. One sets
frequency "Range" (effectively the VCO gain but also with an
effect on the centre frequency):

DATA1

DATA2

DATA3

xx D

10x1xxxx

xxxxxx00

The default values loaded by the power-on reset are

Offset = 0A

HEX

and Range = 21

HEX

and were chosen to help

ensure that the output clock on CLK8 does not run faster than
8·064 MHz while better values are to be loaded. These default
values can usually be left unchanged for normal operation.

The output of the phase comparator charge pump is on

pin C8B so that an external loop filter can be connected. This
loop filter then drives the VCO control voltage, also through

DATA1

DATA2

DATA3

xx D

10xx1xxx

xxxxxx00

The other sets frequency "Offset" (effectively the VCO

centre frequency but also with an effect on the gain):

RANGE &
OFFSET
FROM BUS

RATIO, FROM BUS

8.064 MHz OUTPUT FREQUENCY

PHASE
DETECTOR

C8B

RATIO, FROM BUS

: 63/183/448

EXTERNAL
LOOP
FILTER

CLK8

CHARGE
PUMPS

DOWN

: 100/337/825

CRYSTAL
FREQUENCY
(XO)

VCO

ACE9030

C8B to close the loop. An integration is needed to set the VCO onto the correct frequency and other components can then

ensure loop stability. Enough filtering must be provided to give a clock output suitable for all of its uses - microprocessor clock
and audio filtering. A typical loop filter is shown in figure 17.

AFC Amplifier and Discriminator

Fig. 18 Audio Discriminator And AFCOUT Circuit

correct frequency. Further details of this feature are given in
the APPLICATIONS HINTS section. AFCOUT is also used by
the modem in the ACE9050 to receive signalling DATA.

The other path is the audio discriminator which is a purely

digital implementation of the quadrature technique where the
exclusive-OR gate acts as a digital multiplier and compares
two samples of the AFCIN signal separated by a programma-
ble delay to extract the audio and drive the speech and SAT
paths in the ACE9040. The delay length, M, and the crystal
divider, D, are both programmable for the various crystal and
intermediate frequency choices.

After demodulation the audio is low-pass filtered on-chip

to remove the doubled sampling clock and then bandpass

Fig. 17 Typical OSC8 Loop Filter

The input signal to the pin AFCIN is approximately a

squarewave from the second (final) I.F. amplifier-limiter at 450
or 455 kHz and is A.C. coupled to the pin through a capacitor
of typically 1 nF to drive a Schmitt trigger and become a logic
signal. This signal carries the received modulation - speech,
SAT and signalling data. AFCIN is first amplified and limited
and then processed in two separate paths as in figure 18.

One path samples the input signal at 504 kHz, with a clock

generated by a divide-by-two from the CL clock. This sampling
gives a mixed-down output AFCOUT at 54 kHz when the input
is at exactly 450 kHz and otherwise tracks the offset to allow
estimation of the local oscillator error and the crystal error so
that an AFC loop can be built to adjust the crystal to exactly the

C8B

10nF

12k

VDDA

AFCOUT

TO ACE9050
(FOR AFC
SOFTWARE)

AUDIO

TO ACE9040
PRECISION
BANDPASS
FILTER

EXTERNAL FEEDBACK
(BANDPASS FILTER)

AFCIN

FROM CRYSTAL
OSCILATOR

D = 2 OR 3,
FROM BUS

1 2 3 . . . . M

M = 37 OR 40,
FROM BUS

DRIVER

6 dB

ATT'N

L.PASS
FILTER

: D

: 2

ACE9030

, D

Crystal Freq.

Sampling Rate

I.F.

Delay as I.F. cycles

0, 0

12·80 MHz

6·400 MHz

450 kHz

2·742

0, 0

14·85 MHz

7·425 MHz

450 kHz

2·363

1, 0

12·80 MHz

4·267 MHz

455 kHz

4·266

1, 0

14·85 MHz

4·950 MHz

455 kHz

3·677

0, 1

15·36 MHz

5·120 MHz

450 kHz

3·252

1, 1

15·36 MHz

7·680 MHz

455 kHz

2·251

DATA1 bit D

Set D

Set M

Intended I.F.

Intended Crystal

450 kHz

12·8 or 14·85 MHz

455 kHz

12·8 or 14·85 MHz

450 kHz

15·36 MHz

455 kHz

15·36 MHz

Table 2

Table 3

rapidly increase relative to the I.F. signal and so avoid low
frequency beats, when the system could sit in the state where
a steady part of one cycle is compared with a steady part of
another for a long period of time and so give no output.

The accuracy of the delay is not important as a small error

will only give a D.C. offset in the output but the delay must be
consistant to avoid adding modulation to the output so in the
ACE9030 it is derived from the crystal frequency.

The sampling rate must not be a harmonic of the I.F., or

very close to one, to prevent the sampling phase becoming
synchronised to the signal and so missing all edges, leading
to the modulation being lost for long periods of time at the beat
frequency (a 14·85 MHz crystal cannot be used in D = 3 mode
with an I.F. at 450 kHz as 14·85 MHz

3 is 4·95 MHz which is

11 x 450 kHz). It cannot be assumed that a sampling rate
greater than 4 MHz always meets the Nyquist criterion for the
I.F. signal at nominally 450 or 455 kHz because the input
signal is often a square wave from a limiting amplifier and if not
is converted to a switching logic signal in the Schmitt trigger
input buffer giving many significant harmonics. The modula-
tion deviation is up to 14·5 kHz and is multiplied by the
harmonic number to give increasingly wide deviation such that
the spectrum eventually becomes continuous, but at a low
level, for the very high (e.g.17th or above) harmonics. A
sampling rate of a few MHz will then retain all required
information and allow distortion free demodulation but is
undersampling in Nyquist terms so aliasing effects must be
avoided by choosing a frequency separated from the nearest
harmonic of the I.F. by at least twice the modulation frequency.
All combinations given in tables 2 and 3 can safely be used but
care is needed if a different crystal or I.F. is required. For
example, a 14·4 MHz crystal cannot be used in

2 mode with

a 450 kHz I.F. but

3 can be used and with an M of 40 will give

a delay of 3·75 I.F. cycles and alias-free demodulation.

Sampling the I.F. signal at a rate of only 9·3 to 16·9 times

the I.F. will remove the fine detail of the modulation from each
individual cycle of the I.F. but the modulation bandwidth is very
low (both speech and tones) compared to this sampling rate
so the information will be preserved as infrequent whole
sample steps, which when averaged over many samples will
show the correct modulation.

To explain the operation of the discriminator an example

diagram of the sampling points and the comparison delay is
given in figure 19, with the effect of modulation on the input
shown by fine lines. The increasing separation of these dotted

filtered to nearer telephone bandwidth by an on-chip amplifier
with off-chip feedback components.

The I.F. signal is digitised at a rate set by the crystal in use

and by the divider D in figure 18 and so will be in the range
4·267 to 7·680 MHz. These rates are all greater than the
maximum audio frequency of 3·4 kHz by a factor of at least
1254 ( which is over 2

) and so the quantisation allows better

than 63 dB signal to noise ratio in the final audio, even though
only single bit quantising is used. The I.F. is oversampled by
a much smaller ratio and so will have a smaller signal to noise
ratio if measured in its total bandwidth, but this bandwidth is
reduced in the demodulation process to give a good audio
signal to noise ratio in the system.

To power down the discriminator a Normal command can

be used:

The two control bits D

, D

set the values for D and M as

in table 2. From this table of frequencies and division ratios it
is possible to calculate the length of the delay M in terms of
cycles of the input I.F. to understand the discrimination proc-
ess shown in table 3.

It can be seen that a 12·8 or 15·36 MHz crystal will give a

delay of a few whole cycles plus or minus one quarter cycle to
a very good accuracy and that a 14·85 MHz crystal similarly
gives some whole cycles plus or minus an odd third of a cycle.

These non-integer delays are needed because the delays

are not locked to the I.F. input on AFCIN, and to get a
demodulated output the comparisons must include an edge
time, at least for some samples. The odd quarter or third of a
cycle ensures that the phase of the start of the delay time will

DATA1

DATA2

DATA3

xxxxxx

10xxxxxx

xx1xxx00

DATA1

DATA2

DATA3

xxxxxxxx

01 D

xxxxx

xxxxxxxx

where the discriminator is powered down if DATA2:D

is LOW

or is set active if DATA2:D

is HIGH.

The values of the programmable constants D and M are

set by a Set-up command, which can also use DATA1 bit D

for the lock logic filter period and DATA1 bits D

, D

for the

OSC8 mode programming:

ACE9030

Fig. 19 F.M. Discriminator Example Timing Diagram

, D

Delay as

I.F.

Absolute Gain

Relative Gain

I.F. cycles

kHz

V/Hz,

= 3·75 V.

= 4·85 V.

0, 0

2·742

450

45·7

59·1

1·8 dB

0, 0

2·363

450

39·4

50·9

0·5 dB

1, 0

4·266

455

70·3

90·9

5·6 dB

1, 0

3·677

455

60·6

78·4

4·3 dB

0, 1

3·252

450

54·2

70·1

3·3 dB

1, 1

2·251

455

37·1

48·0

0 dB

Table 5

phase effect of f.m. increases as more cycles are exam-

ined. The modulation lines are drawn as the phase change on
the real input waveform but the separation from the nominal
edge position can also be interpreted as the probability of a
whole cycle shift on the sampled version of the signal as in the
ACE9030.

Only six delay comparisons are shown, stepping across

at the sampling rate, but the effect of the pattern can easily be
seen by continuing the sequence, and two conclusions can be
drawn:
1) The output waveform is at twice the frequency of the input
- this is true for all delay-and-multiply schemes.
2) The output high time is modulated by the phase modulation
accumulated over the delay duration and the output period is
only modulated slightly by the instantaneous input phase
shifts so the effect is to modulate the duty cycle. Due to the
sampling of the I.F. input the modulation will really be
quantised so the width of the modulation box should be read
as a probability of a whole cycle shift in edge position rather
than as a phase shift but the effect is the same when averaged
over many cycles.

By converting the modulation from a phase shift to a duty

cycle all that is then needed to recover the original baseband
signal is to smooth the discriminator output to remove the
900 kHz sampling, leaving an analog signal proportional to the
original frequency deviation and to the delay length. The low-

pass filter in ACE9030 is first order and has its 3 dB point at
approximately 70 to 80 kHz to significantly reduce the clock
level; the audio bandpass filter then further reduces this level
to give a cleaner audio output to drive the ACE9040 where it
is again filtered.

The demodulation gain can be determined by considering

the effects of a 1 kHz frequency offset on the input signal, and
using I.F. = 450 kHz and Delay = 2·742 cycles and
V

= 3·75 V in the example:

A 1 kHz frequency offset will give a phase change in the

I.F. signal, during each cycle, of 2

x (1 kHz / I.F.) radians or

as a fraction of a cycle, (1 kHz / I.F.) which in this example is
1/450 of a cycle.

If the discriminator delay is measured in I.F. cycles the

change in output pulse width for each of the two output pulses
is: (Delay in cycles) x (phase change per cycle)
= Delay x (1 kHz / I.F.) in I.F. periods, which in this example
is 2·742 x 1/450 periods of 450 kHz, or 13·5 ns.

Output pulses occur at a rate of 2 x I.F., so the change in

output pulse width measured in output periods is 2 x (change
measured in I.F. periods), giving 2 x Delay x 1 kHz / I.F. The
duty cycle is defined as pulse width / period so the result is also
the change in duty cycle. For this example the change is 0·012.

The output is a logic signal so its amplitude is V

for all

settings and for all modulation, thus the final effect of a 1 kHz
offset is an output change of 2 x Delay x 1 kHz x V

/ I.F. and

INPUT

ROLLING
PAIRS OF
SAMPLES
TO EX-OR
GATE FOR
COMPARISON

OUTPUT

2 NOMINAL CYCLES

ACE9030

the example gives 0·045 V.

Removing the arbitrary 1 kHz, the gain at the exclusive-

OR gate is given by:

Gain = 2 x Delay in I.F. cycles x V

/ I.F.

with the units of volts per Hertz of deviation.

To be strict, the pulse width is reduced for a positive

deviation, so the gain is negative, but this may be ignored as
the audio polarity is not of any relevance and also is inverted
several times before driving the earpiece.

Using the delay lengths from table 3 the range of gains (at

the exclusive-OR gate) can be listed and then compared with
the lowest as shown in table 5.

This shows a gain range of 5·6 dB which must be allowed

for in the later stages, but also gives absolute gains which
show the discriminator could cause saturation in the following
stage if a high deviation signal is received. For example
speech can be set to 8 kHz deviation so the maximum voltage
(with V

at 3·75 V) is 70·3 x 8000

V = 562 mV peak. With ST

and SAT the total deviation can become 14·5 kHz, potentially
giving 1·019 V peak signal, or over 2 V peak-to-peak and
leading to possible saturation. There is also the full V

switching waveform to handle. Other supply levels will simply
scale the signals and not change the saturation problem. A
6 dB attenuator is included in the low pass filter that follows the
discriminator output driver to avoid any possibility of saturation
in the audio reconstruction filter. This attenuator is a simple 2:1
potential divider so will also halve the D.C. level of the signal.

A further effect to be considered is the D.C. offset that

results from using delays that are not ideal multiples of cycles
of the AFCIN frequency. It can be seen from the Timing
Diagram, figure 19, that when the delay is exactly an odd
number of quarter cycles each half cycle at one end of the
delay will symmetrically straddle an edge the other end of the
delay so an unmodulated input will give an output with a 1:1

mark:space ratio; this corresponds to a mid-supply level at the
attenuator input, see figure 20. The attenuator output will then
be centred at V

/4, so the nominal D.C. gain, 2 x, of the

bandpass filter will give the AUDIO output centred at mid-
supply.

When a mode is selected with an odd number of thirds of

a cycle the output mark:space ratio is offset, and approximat-
ing 2·363 as

or 3·677 as

the effect can be seen in

figure 21.

The signal will now be centred on a level at

supply, at the attenuator input (giving

x V

at its

output) and by adjusting the D.C. gain of the bandpass filter it
is possible to set the AUDIO to a mid-supply centre if required.

The components used in the bandpass filter feedback

circuit should be chosen to both set the pass band frequencies
(for example 50 Hz to 30 kHz) and also to set the A.C. and D.C.
gains to complement the discriminator's gain and D.C. offset.
Typcal A.C. gain at mid-band is around 20 dB. This filter is not
of high enough order to remove all out of band noise without
distorting the speech channel so to get the final band limited
signal precision high order filters such as in the ACE9040 are
required.

The ACE9030 is specified with the following component

values (see fig 18):

R1 = 47k

R2 = 100k

R3 = 33k

C1 = 82pF
C2 = 100nF

Fig. 21 Demodulation With Odd Thirds Of A Cycle

Fig. 20 Demodulation With Odd Number Of Quarter Cycles

These values are compatible with AMPS using a 14.85MHz
reference crystal and 450kHz IF. Resistors R2 and R3
determine the dc gain and can be used to compensate for the
dc offset of the demodulated output. Resistors R2 and R3, R1
determine the mid band ac gain of the band pass filter.

AFCIN

AFCIN DELAYED
BY 2 / CYCLES:

OUTPUT
(EX-OR)

MARK:SPACE
RATIO = 1:1

MARK:SPACE
RATIO = 2:1

MARK:SPACE
RATIO = 1:2

AFCIN

AFCIN DELAYED
BY 7/3 CYCLES:

OUTPUT
(EX-OR)

OR BY 11/3
CYCLES:

OR BY 2 /
CYCLES:

ACE9030

Main

bit 1 bit 0

Tap

FUNCTIONAL DESCRIPTION - BLOCKS IN THE SYNTHESISERS

There are two synthesisers in the ACE9030 for use by the

radio system, a Main loop to set the first local oscillator to the
frequency needed for the channel to be received and an
Auxiliary loop to generate an offset frequency to be mixed with
the Main output to give the transmit frequency. The modula-
tion is added to the Auxiliary loop by pulling the VCO tank
circuit and is then mixed onto the final carrier frequency. In a
typical cellular terminal the first Intermediate Frequency is
45 MHz so the Main synthesiser will be set 45 MHz above the
receive channel frequency. Many cellular systems operating
around 900 MHz use a 45 MHz transmit-receive offset, with
the mobile transmit channel below the receive channel fre-
quency so the Auxiliary synthesiser will be set to a fixed
frequency of 90 MHz.

Loop dynamics needed for the Main synthesiser are set

by the re-tuning time during hand-off and to help simplify the
off-chip loop filter components there are Fractional-N and
Speed-up modes available for this synthsiser, primarily for use

in ETACS terminals. The Auxiliary loop does not change
frequency so the only constraints are power-up time and
microphonics, so a simple synthesiser is used.

The two loops share a common reference divider to save

power and also to control the relative phase of the two sets of
charge pumps.

As described in the section FUNCTIONAL DESCRIP-

TION - CONTROL BUS there is often benefit in holding
LATCHC at a high level to minimise bus clock interference to
the synthesiser loops. The dummy word in figure 11 is the
preferred technique to set LATCHC to high for normal opera-
tion.

At power-on, the reset generator in the Radio Interface

section is used to initialise both synthesisers to their power
down state. In this state they can be programmed with
required numbers to be ready for power-on when the whole
terminal has fully initialised.

Fig. 22 Reference Divider

A common reference divider is used for the two synthesis-

ers, but to allow some difference in comparison frequencies
the final four stage output selectors are repeated for each
synthesiser as shown in figure 22. To reduce interaction
between the two synthesisers the divider outputs are ar-
ranged in antiphase so that loop correction charge pump
pulses occur alternately in each loop. This phase separation
also reduces the peak current in the charge pump power
supply and can reduce interference to other sections of the
mobile terminal.

The input clock to the reference divider is the internal

signal XO from the crystal oscillator. The two outputs drive the
Auxiliary and the Main phase detectors directly.

A standby mode is available for the reference divider and

is enabled whenever both synthesisers are in standby.

The programming numbers are all loaded from the serial

bus in Word D, NR directly sets the ratio of the 12 bit divider
but SA and SM select the final divisions as in the following
tables:

Auxiliary

bit 1

bit 0

Tap

The minimum allowed value of NR is set by the need to

generate some small time windows around the comparison
edges for Lock Detect logic and for Fractional-N compensation
so a value of at least 8 is required. The maximum NR is 4095
as normal for a 12 bit counter and this is then increased by a
factor of 1, 2, 4, or 8 in the final divider. A typical required
reference division is

512 so neither of these limits should

constrain the system design.

Reference Divider

SELECT

- 1/2/4/8

SELECT

12 BIT DIVIDER

NR FROM BUS

SM FROM BUS

COMP.FREQ.
TO AUXILIARY
PHASE DETECTOR

COMP.FREQ.
TO MAIN
PHASE DETECTOR

ACE9030

Fig. 23 Auxiliary Synthesiser

The phase detector drives switched current sources to

pump charge onto an external passive loop filter which is
primarily an integrator, resulting in the minimum of external
components. The charge pump output current level is set by
the external resistor on pin RSMA and the ratio is fixed so that
nominal I

AUX

= 8 x I

RSMA

. This bias resistor also sets the main

synthesiser output current but that current has a programm-
able ratio to enable different currents for each loop. The pin
RSMA does not need any decoupling and to avoid all possi-
bilities of oscillation the external capacitance should be less
than 5 pF.

The polarity of the output is such that a more positive

voltage on the loop filter (PDA pin) sets a higher VCO
frequency.

A standby mode for the auxiliary synthesiser can be

selected if bit DA in Word D is HIGH.

This synthesiser is used to add modulation to the trans-

mitted signal. The most convenient approach, as shown in
figure 31, is to drive the positive end of the varactor diode in
the tank circuit with the loop filter to set the frequency and then
to drive the negative end with the modulation from a summing
circuit (speech plus SAT plus data or ST) from ACE9040.

Auxiliary Synthesiser

The Auxiliary Synthesiser operates with an input fre-

quency up to 135 MHz. The input buffer will amplify and limit
a small amplitude sinewave signal and so can be driven from
the ACE9020 VCO directly. There are three main blocks in this
synthesiser: a 12-bit programm-able divider, a digital phase
detector, and output charge pumps to drive a passive loop
filter.

To assist fast recovery from power-down the inputs FIA

and FIAB are designed to be d.c. driven by the TXOSC+ and
TXOSC outputs from ACE9020.

FIA can also be used single-ended if it is driven by a signal

with double amplitude, the correct d.c. level and if FIAB is
decoupled to ground by a capacitor (see Electrical Character-
istics for full details). Internal biasing will set the d.c. level on
FIAB.

The 12 bit programmable divider is set by the NA bits in

Word C and ratios from 3 to 4095 can be used. This drives the
phase detector along with the comparison frequency signal
from the common reference divider.

A digital phase detector is used and is designed to

eliminate any deadband around the locked state, this is
especially important when modulation is added.

Main Synthesiser

The main synthesiser in the ACE9030 is designed to

operate with a two-modulus prescaler and will accept frequen-
cies up to 30 MHz. To assist fast recovery from power-down
the inputs FIM and FIMB are designed to be d.c. driven by the
DIV_OUT+ and DIV_OUT outputs from the ACE9020 or
similar outputs from standard prescalers.

FIM can also be used single-ended if it is driven by a signal

with double amplitude, the correct d.c. level and if FIMB is
decoupled to ground by a capacitor (see Electrical Character-
istics for full details). Internal biasing will set the d.c. level on
FIMB.

The block diagram depends on which mode is selected

but is basically the same as the Auxiliary synthesiser with
added features for each mode. The common element is the
phase detector, which is the same circuit used in the Auxiliary
synthesiser and again drives switched current sources to
pump charge into an external passive loop filter to minimise
the external components. The charge pump output current
level is set by the external resistor on pin RSMA and the
multiplying ratio is programmable by the bus and the chosen
mode as in table 6. This bias resistor also sets the Auxiliary
synthesiser output current as described above.

A standby mode for the main synthesiser can be selected

if bit DM in Word D is HIGH.

The Main synthesiser can be used in different modes

depending on the requirements of the communication system
it is operating in:

Normal mode

The most straightforward to use and adequate for most

analogue cellular telephone systems.

Normal Mode with Speed-up

This adds a fast slew drive to the loop filter during channel

changes so that the time from channel to channel is signifi-
cantly reduced but once the change is expected to be com-
plete the loop reverts to normal mode. A little care is needed
in parameter choice and loop filter design to ensure the loop
is stable in both modes and there is likely to be a higher level
of comparison sidebands during speed-up mode. This combi-
nation offers a faster channel change or a lower level of
comparison frequency sidebands once on channel, or with
care some of each advantage.

NA FROM BUS

PHASE
DETECTOR

DOWN

12 BIT DIVIDER

RESET

CHARGE
PUMP

PDA

AUXILIARY COMPARISON
FREQUENCY (FROM
REFERENCE DIVIDER)

FIA

FIAB

ACE9030

Fractional-N mode

When selected this mode is permanently active and by

interpolating channels between comparison frequency steps
allows a higher comparison frequency to give both a faster
channel change time and a lower comparison sideband level.
The higher comparison frequency also allows a higher loop
bandwidth which can reduce phase noise in the locked sys-
tem. It is not difficult to get the Fractional-N loop compensation
correct to minimise sidebands at the fractional frequency as

Fig. 24 Main Synthesiser - Normal Mode

Main Synthesiser - Normal Mode

In Normal mode the Main synthesiser is similar to the

Auxiliary synthesiser with the addition of control for an external
prescaler, see figure 24.

The 12-bit counter first counts down for N1 cycles, with

MODMP set HIGH, then counts up for N2 cycles, with MODMP
set LOW, and finally gives an output pulse (every N1 + N2
cycles) to the phase comparator and repeats the whole
sequence. The use of an up/down counter allows the control
of a two modulus prescaler without needing a separate
counter for that purpose. To give time for the function
sequencing a minimum limit of 3 is put on N1 and a pro-
grammed value of 0 for N2 will be treated as 256 and so is not
normally used. Choices of values for N1 and N2 are described
in the later sections "Two Modulus Prescaler Control" and
"Programming Example for Both Synthesisers".

The phase detector operates with the same arrangement

of overlapping up and down pulses as the Auxiliary phase
detector to again avoid any dead band, the charge pump
current is also set by the same resistor on pin RSMA but for the
Main charge pumps the current is also controlled by the bus.
In the bias circuit the current I

RSMA

through the external resistor

on pin RSMA is divided by 32 to give a reference current Ibo
( Ibo = I

RSMA

) and this current is then multiplied by the

value CN from the control bus to give the normal charge pump
current Iprop(0). The pin RSMA again does not need any
decoupling and to avoid all possibilities of oscillation the
external capacitance should be less than 5 pF.

CN can be changed for different channels, to track the

division ratio set by N1 and N2, to maintain the same PLL loop
gain over the operating band but in most cellular systems the
total band is narrow compared to the frequencies and a fixed
CN is adequate. Other synthesiser control parameters do not
need changing and could be loaded at power-on and then left
unaltered.

Main Synthesiser - Normal Mode withSpeed-up

During Speed-up the drive to the loop filter is increased to

change channels faster. There will be a slight degradation of
sideband performance during the change but this does not
affect the final system performance. Speed-up lasts for the
duration of the LATCHC pulse that loads an A or A2 word from
the bus and as soon as the pulse ends the currents return to
normal to give clean synthesis. The normal charge pump
current is increased by a factor (2

L+1

) to give 2, 4, 8, or 16 times

Iprop(0), as defined in Normal Mode, and is then referred to as
Iprop(1), as in figure 26. A second charge pump is enabled to
drive the capacitor Ci in the loop filter directly, and as this is
always larger than capacitor Cp this extra output is set to
Iprop(1) x K. The factors L and K are used to control speed-up
and are loaded at power-up and can be left at fixed values.

Speed-up is always enabled by LATCHC when an A or A2

word is loaded. When speed-up is not required the LATCHC
pulse should be short and the parameters L and K set to their
minimum to give an insignificant effect.

Main Synthesiser - Fractional-N Mode

Fractional-N mode is the same as Normal mode with the

addition of the Fractional-N system, shown in figure 25.

In Fractional-N mode the modulus of the prescaler is

changed in a cyclic manner to interpolate channels between
the comparison frequency steps. Depending on the state of
the FMOD bit loaded in Word D the pattern can be 5
(FMOD = 0) or 8 (FMOD = 1) cycles long, giving the choice of

's or

's of the comparison frequency and the fractional

numerator is set by NF in Word A or A2. The accumulator
repeatedly adds NF to its own value and generates an
overflow whenever this value exceeds the count modulo
number. This overflow output to the Modulus Control logic will
force one cycle to change from MODMP HIGH to MODMP
LOW to in turn set the prescaler to the higher ratio for one cycle

the ACE9030 fractions are only

's or

's. For further details

see the later section "Detailed Operation of Fractional-N
Mode".

Fractional-N Mode with Speed-up

This gives the ultimate loop performance from the

ACE9030 but care is needed when designing the loop filter
and when choosing the values of the control parameters.

N1 & N2

FROM BUS

PHASE
DETECTOR

DOWN

12 BIT DOWN/UP
COUNTER

RESET

CHARGE
PUMP

PDP

MAIN COMPARISON
FREQUENCY (FROM
REFERENCE DIVIDER)

FIM

FIMB

MODMP

MODMN

MODULUS CONTROL

ACE9030

TIME GATING

SET CURRENT

OVERFLOW

COMPENSATION
CHARGE PUMP

CHARGE TO
LOOP FILTER

(TO PRESCALER
MODULUS CONTROL)

COMPENSATION

DAC

ACCUMULATOR

MODULO-5 OR 8

FRACTION
REGISTER

COMPARISON
FREQUENCY

Ico

PROPORTIONAL
CHARGE PUMP

FRACTIONAL-N
COMPENSATION
CHARGE PUMP
(INTEGRAL)

FRACTIONAL-N
COMPENSATION
CHARGE PUMP
(PROPORTIONAL)

EXTERNAL,
PASSIVE
LOOP FILTER
Cp, Ri, Ci

INTEGRAL
CHARGE PUMP

PDI

PDP

To VCO

VDD

Icomp(0) =
ACC.Ico
Icomp(1) =
x2, 4, 8, 16

Icomp2 =
K.Icomp(1)

lint =
K.lprop(1)

DOWN

VDD

Icomp(0) =
CN.lbo
Iprop(1) =
x 2, 4, 8, 16

DOWN

VSS (GND)

Fig. 25 Fractional-N Add-On To Main Synthesiser

and so increment the total division.

To avoid loop modulation due to the accumulating phase

shift at the fractional frequency, a compensation charge must
also be driven onto the loop filter to track the accumulated
phase error so a current Icomp(0) is output on PDP for a fixed
short duration. Icomp(0) is given by Icomp(0) = ACC x Ico,
where ACC is the value of the phase accumulator and Ico is
a current set by a resistor on pin RSC such that Ico = I

RSC

/320.

In a typical system the required value of Ico is between

and

of Ibo and thus the resistor on RSMA has a value between

one and three times the value of the resistor on RSC. As with
RSMA, the pin RSC does not need any decoupling and to
avoid all possibilities of oscillation the external capacitance
should be less than 5 pF. For a full description of this mode see
the later section "Detailed Operation of Fractional-N Mode".

In fractional-N mode a zero fraction numerator, in both

's and

's mode, will force the accumulator to zero and not

simply leave it at an arbitrary fixed value. This feature makes
testing easier by setting the accumulator to a known state, but
is also useful in operation by stopping all compensation pulses

when none are needed. Similarly in

's mode if

( and

)

fractions are set then the LSB or two LSB's in the

accumulator will be forced to zero to relax the tolerance on the
compensation.

Main Synthesiser - Fractional-N Mode with Speed-up

In Fractional-N mode with Speed-up the normal compen-

sation current is increased by the same factor (2

L+1

) as the

main charge pump current to give Icomp(1), and at the same
time the integrating capacitor is also driven with a compensat-
ing charge by a current Icomp(2) set to Icomp(1) x K. This extra
compensation is included so that the loop will step to exactly
the desired frequency during the Speed-up phase and then be
on channel when normal Fractional-N begins.

Main Synthesiser Charge Pumps

The charge pumps for all modes are shown together in

figure 26. The charge pumps on pin PDP are used normally to
hold a channel and are also used in speed-up modes at a

Fig. 26 Main Synthesiser Charge Pumps

ACE9030

larger current. The charge pumps on PDI are only used in

speed-up and then drive the integrating capacitor Ci directly.
The control signals Ø

and Ø

DOWN

are the error signals fron the

phase detector and have a duration proportional to the phase
error, the signal Fc is the Fractional-N compensation gating
pulse and has a fixed duration set by the crystal oscillator.

Nominal Charge Pump Currents

Shown in table 5, charge pump currents are set by the

resistors RSMA and RSC and by scaling coefficients loaded
from the serial bus. CN is an 8 bit number, L is 2 bit and K is
4 bit. Fractional-N compensation also depends on the instan-
taneous value ACC in the fractional accumulator, a 3 bit
number.

Two Modulus Prescaler Control

The Main ACE9030 synthesiser is designed to operate

with the two-modulus prescaler section of the ACE9020. This
allows channels to be spaced at the comparison frequency
while keeping the clock rates within the range possible in
CMOS. ACE9030 can also be used with standard two-modu-
lus prescalers such as SP8715.

The prescaler will have two division ratios, R1 and R2,

selected by a Modulus Control signal and designed to switch
quickly from one ratio to the other so that a sequence of R1 and
R2 can be used to give the required total division. It is usual to
have R2 = R1 + 1 and to select R1 by setting Modulus Control
to the HIGH state and R2 by a LOW state.

To reduce interference the Modulus Control output from

ACE9030 is a pair of differential signals MODMP and MODMN
each with a limited voltage swing but still able to drive selected

Pin

Charge pump

Normal

Speed-up

Maximum setting*

PDP

Main

Iprop(0) = CN x I

RSMA

/32

Iprop(1) = 2

L + 1

x Iprop(0)

1·0 mA

PDI

Main

Off

Iint = K x Iprop(1)

5 mA

PDP

Fractional-N

Icomp(0) = ACC x I

RSC

/320

Icomp(1) = 2

L + 1

x Icomp(0)

PDI

Fractional-N

Off

Icomp(2) = K x Icomp(1)

180

PDA

Auxiliary

Iauxil = 8 x I

RSMA

no auxiliary speed-up

512

* Larger values of current can be set by the programming numbers and the resistor values, but the circuit is not then guaranteed to give the
calculated current.

Table 5

standard prescalers from GEC-Plessey Semiconductors if
MODMP is used alone. Even if a prescaler with non-differen-
tial control input is used there could still be some benefit in
running a MODMN track on the circuit board beside the
MODMP track to partly cancel capacitive coupling to sensitive
nodes. Simplified waveforms are shown in figure 27.

Unlike many conventional synthesisers that use two

separate counters, to give both the total count, M, and the
portion for which the prescaler is at its higher ratio, A, there is
only one counter in the ACE9030 for both these functions. This
counter is loaded with the value N1, counts down to zero,
changes direction, counts up to N2, is again loaded with the
value N1 and changes direction to down, and so the cycle is
repeated indefinitely.

Fig. 27 Modulus Control Timing Diagram

N1 + N2

...R1...

R1 R1

...R2 ...

R2 R1

PRESCALER RATIO

FIM

FIMB

MODMP

MODMN

COUNTER OUTPUT TO
PHASE COMPARATOR

DELAY

SET-UP

ACE9030

CHANNEL

MOBILE TRANSMIT

MOBILE RECEIVE

MAIN VCO

NUMBER

FREQUENCY (MHz)

(MHz)

1329 or 719

872·0125

917·0125

962·0125

...

2047 or 1

889·9625

934·9625

979·9625

889·9875

934·9875

979·9875

890·0125

935·0125

980·0125

890·0375

935·0375

980·0375

890·0625

935·0625

980·0625

...

600

904·9875

949·9875

994·9875

An output to drive the phase comparator is generated

from the N1 load signal at the start of each cycle, giving a pulse
every (N1 + N2) counts and to help minimise phase noise in
the complete synthesiser this pulse is re-timed to be closely
synchronised to the FIM/FIMB input. During the N1 down
count the modulus control MODMP is held HIGH to select
prescaler ratio R1 and during the N2 up count it is LOW to
select R2, so the total count from the VCO to comparison
frequency is given by:

TOT

= N1 x R1 + N2 x R2

but

R2 = R1 + 1

TOT

= (N1 + N2) x R1 + N2

It can be seen from this equation that to increase the total
division by one (to give the next higher channel in many
systems) the value of N2 must be increased by one but also
that N1 must be decreased by one to keep the term (N1 + N2)
constant. It is normal to keep the value of N2 in the range 1 to
R1 by subtracting R1 whenever the channel incrementing
allows this (i.e. if N2 > R1) and to then add one to N1. These
calculations are different from those for many other synthesis-
ers but are not difficult.

The 12-bit up/down counter has a maximum value for N1

of 4095 and to give time for the function sequencing a
minimum limit of 3 is put on N1. There is no need for such large
values for N2 so its range is limited by the programming logic

to 8 bit numbers, 0 to 255 and to simplify the logic a set value
of 0 will give a count of 256. If a value of 0 for N2 is wanted then
N2 should be set instead to R1 and the value of N1 reduced
by (R1 + 1), also equal to R2.

To ensure consistent operation some care is needed in

the choice of prescaler so that the modulus control loop has
adequate time for all of its propagation delays. In the
synthesiser there is propogation delay T

DELAY

from the

FIM/FIMB input to the MODMP/MODMN output and in the
prescaler there will be a minimum time T

SET-UP

from the change

in MODMP/MODMN to the next output edge on FIM/FIMB, as
shown in figure 27. For predictable operation the sum
T

DELAY

+ T

SET-UP

must be less than the period of FIM/FIMB or

otherwise, if the rising and falling edges of MODMP/N are
delayed differently, the prescaler might give the wrong bal-
ance of R1 and R2. This will often set a lower limit on the
frequency of FIM than that set by the ability of the counter to
clock at the FIM rate. For 900 MHz cellular telephones the use
of a

64/65 prescaler normally ensures safe timing.

Fractional-N mode operates by forcing the

MODMP/MODMN outputs to the R2 state for the last count of
the N1 period whenever the Fractional-N accumulator over-
flows, effectively adding one to N2 and subtracting one from
N1, and so increases the total division ratio by one for each
overflow. The effect of this is to increase the average division
ratio by the required fraction.

PROGRAMMING EXAMPLE FOR BOTH SYNTHESISERS

Each channel is 25 kHz wide but as the channel edges are

put onto the whole 25 kHz steps the centre frequencies all
have an odd 12·5 kHz. This is not ideal for the synthesiser but
does give the maximum number of channels in the allocated
band.

The mobile receive channels are a fixed 45 MHz above

the corresponding transmit frequency, as is the case with most
cellular systems. In the ACE9030 the intention is to use the
main synthesiser to generate the receiver local oscillator at the
first I.F. above the mobile receive carrier, and to then mix the
auxiliary synthesiser frequency with this to produce the trans-
mit frequency. A typical I.F. is 45 MHz, leading to an auxiliary
frequency of 90 MHz and a crystal of 14·85 MHz with a tripler
for the second local oscillator, and a final I.F. of 450 kHz.

The channel numbers and corresponding frequencies

are shown in table 6.

To illustrate the choice of programming numbers consider

the ETACS system as now used in the UK.

This began as TACS with 600 channels (numbered 1 to

600) from 890 to 905 MHz (mobile transmit) with the provision
to expand by 400 channels (601 to 1000) from 905 to 915 MHz.
This additional spectrum was given over to GSM use before
TACS needed expanding, so TACS was later extended by 720
extra channels from 872 to 890 MHz, to form ETACS and
leaving a somewhat odd channel numbering system. The
channel numbers are stored as 11-bit binary numbers and are
listed here as both negative numbers to follow on downwards
from channel 1 and also as large positive numbers as these
are the preferred names. These two numbering schemes are
really the same, as the MSB of a binary number can be
interpreted as either a sign bit (2's complement giving the
negative values) or as the bit with the highest weight (1024 for
an 11 bit number, giving the large positive values).

Table 6

ACE9030

The reference divider needs to produce the main com-

parison frequency of 12·5 kHz from the crystal at 14·85 MHz,
a ratio of 1188, which can be formed by a NR of 1188 followed
by a SM select giving

1, or 594 followed by

2, or by 297 and

4. The auxiliary divider must divide 90 MHz down to the

auxiliary comparison frequency, which is related to the main
comparison frequency but can usefully be larger. Using
12·5 kHz needs a ratio of 7200 which is too large a value for
NA, 25 kHz needs 3600 and could be used, but 50 kHz and a
ratio of 1800 helps to minimise loop filter size. With this choice
the values to be set are:

NR = 297, to give 50 kHz into SA, SM selector.
SA = 00, to give

1, and leave 50 kHz for auxiliary

comparison frequency.

SM = 01, to give

4, and hence 12·5 kHz for main

compari

son frequency.

NA = 1800, to give 90 MHz.

In this example Fractional-N operation is not chosen, but if it
is required then SM should be set to 00 to give 50 kHz
comparison frequency in both synthesisers and then fractions
of

used by setting NF = 2 or 6, with FMOD set to 1 to

give

's. The values of N1 and N2 can then be found by

following a procedure similar to the following.

For the main synthesiser, starting at channel 1, to divide

980·0125 MHz down to 12·5 kHz is a total ratio of 78401 and
this will be split between the prescaler and the ACE9030
programmable divider. A

64/65 prescaler is most common,

and will be in

64 mode as its normal state, so the 78401 can

be split into a

64 followed by

1225 with a remainder of 1. The

remainder is achieved by setting the prescaler to

65 for 1

cycle, so using R1 = 64, and R2 = 65 the programmable values
can be:

N2 = 1, and (N1 + N2) = 1225, thus N1 = 1224

These values are suitable for use but are not the only

possible set - if desired N2 can be increased to 65 if N1 is
reduced to 1160. The actual choice in practice is set by
whichever gives the more convenient mathematics in the
system controller, the only limits are the basic equation:
N

TOT

= (N1 + N2) x R1 + N2, which must be met for all channels

and the fact that a set value of 0 for N2 will actually give a count
of 256 so for easy calculations N2

0 (in practice for a TACS

system not using Fractional-N all N2 values are odd numbers
so 0 is never needed).

Other channels can easily be added, without forgetting

that each channel is two comparison steps (2 x 12·5 kHz)
above the next lower, so for channels 1 to 32,

N2 = 2 x Channel Number 1, and N1 = 1225 N2

and for channels 33 to 64,

N2 = 2

( Channel Number 32 ) 1, and N1 = 1226 N2

Rather than having several sets of separate equations for

each group of channels it is possible to combine them all into
one set by adding two variables to split the channel number
into a modulo-32 and a remainder number. Let C32 =
int((Channel Number 1)

32), where "int(x)" means the

integer part of (x), and let CN2 = Channel Number (32 x C32),
then:

N2 = (2 x CN2) 1, and N1 = 1225 N2 + C32

These are clearly valid for channels 1 to 600 (the original

TACS channels) but to cover the extra channels for ETACS

the negative numbers need more processing to avoid nega-
tive N2 values. The simplest answer is to add an offset to the
channel number and then subtract an equivalent value from
the N1 equation. As the channels are in blocks of 32 for the
calculations it is helpful to choose a multiple of 32 for the offset,
and the most negative channel is 719 so the lowest suitable
offset value is 736 (that is 23 x 32). This gives the following
steps for all TACS/ETACS channels:

CNOFF = Channel Number + 736

CB32 = int((CNOFF 1)

32)

CN2 = CNOFF (32 x CB32)

N2 = (2 x CN2) 1
N1 = 1202 N2 + CB32

These operations are given in easy to understand stages

but in a real system it could be more efficient to combine or
rearrange some steps. If a high level language is used then
integer and remainder functions might be available and could
save a little programming time, whereas if low level or assem-
bler language is used an integer function will need to be built,
in this case by a 5 bit right shift to both divide by 32 and to lose
the fraction.

It might be noticed that avoiding N2 = 0 was very easy as

all values of N2 in this system are odd numbers, due to the 12·5
kHz offset from band edges. Other systems do not have this
offset so a little care is needed in choosing constants in the
corresponding equations.

DETAILED OPERATION OF FRACTIONAL-N MODE

Without using the Fractional-N mode the loop will lock the

VCO frequency, f

VCO

to the comparison frequency, f

COMP

at a

multiple set by the total division ratio N

TOT

, where:

TOT

= (N1 + N2) x R1 + N2

giving:

VCO

= f

COMP

x N

TOT

From these equations it can be seen that if N

TOT

is an

integer the minimum frequency step is f

COMP

. It is not possible

to make a non-integer divider but by alternating the ratio
between N

TOT

and N

TOT

+ 1 in a suitable pattern the effect of a

fractional increase in N

TOT

can be achieved. This is called

Fractional-N operation.

The control of the pattern of N

TOT

and N

TOT

+ 1 cycles is by

an accumulator set to count with a modulus equal to the
fractional denominator and which adds the numerator of the
fraction every comparison cycle. When the accumulator over-
flows by its value exceeding the value of the denominator the
total division ratio is increased for one cycle. In ACE9030 the
choice of denominator is 5 or 8 and is set by the FMOD bit in
Word D, the numerator is set by the three NF bits in Word A or
A2 and the increase in total division from N

TOT

to N

TOT

+ 1 is

done by changing the modulus control signal to the prescaler
so that an R1 cycle becomes an R1 + 1 cycle.

As an example of the operation of the accumulator

consider FMOD set HIGH to give modulo-8 counting and NF
set to 011 to give a

fraction and the accumulator starting at

any arbitrary value as shown in table 7.
From this table it can be seen that the pattern repeats every
8 cycles and that the ratio is incremented for 3 of each 8, giving
the desired N

TOT

. It can be shown that the pattern always

repeats every 8 cycles, or whatever modulus is chosen for all
fractions and that the number of N

TOT

+ 1 cycles is always the

fractional numerator.
By spreading the (N

TOT

+ 1) counts throughout the pattern

rather than having them as a continuous block the loop is less

ACE9030

Increment

Accumulator

Division

( = NF )

value

Ratio

...previous values

TOT

& overflows

TOT

+ 1

TOT

& overflows

TOT

+ 1

TOT

& overflows

TOT

+ 1

TOT

& overflows

TOT

+ 1

and so on...

and in this case the phase error increases in the opposite
direction each cycle by:

This phase error gives an unwanted correction pulse on

the Ø

output, as the VCO frequency is too low for the division

ratio in use.

Any phase can be considered to be the locked condition

so to simplify later calculations the phase given by a

(NTOT

+ 1) cycle which leaves 000 in the accumulator will be chosen
as the locked state and compensation will be added to achieve
this. Only unwanted Ø

DOWN

outputs then need to be removed

by cancellation and also that the total phase error in any cycle,
based on formula (2), is given by replacing F, the fraction
required, by the current sum of fractions, which is the value of
the accumulator ACC divided by the modulus in use. This
replacement is clearly valid if the state of the accumulator is
considered when starting from a zero value and then adding
the fractional count each cycle until an overflow is reached;
when starting from a non-zero value there is some residual
phase error from the overflow state so the accumulator still
gives the correct phase error. Thus the phase error needing
correction on the loop filter is:

This error could be cancelled by a phase shift on the

comparison clock from the reference divider but this is very
difficult in practice so the method used in ACE9030 is to add
an extra charge pump to the loop filter to directly cancel the
pulse given by the normal charge pump due to this phase
error. The current given by the proportional charge pump is
Iprop(0) in normal mode or Iprop(1) in speed-up mode so
taking normal mode first the charge that must be cancelled is:

This formula could be used as it stands but the circuit can

be simplified if it is recalled that Iprop(0) depends on the CN
value so that loop dynamics are kept constant over a wide
range of frequencies by changing CN in proportion to the total
division ratio N

TOT

. In those systems where CN is held constant

the synthesiser is in effect considered to be operating over a
narrow frequency band so N

TOT

can also be considered

constant and the following calculations still apply. The value of
Iprop(0) is set by a DAC in ACE9030 from the reference
current Ibo so that:

and the value of CN tracks N

TOT

with a scaling factor SF such

that:

putting both of these equations into formula (5) gives the
charge to be cancelled as:

NF is the fraction set in Word A or A2
MOD is the modulus, 5 or 8

disturbed by the variations in division ratio but there is still
some frequency modulation given by the Fractional-N opera-
tion. The simplest way to remove this ripple on the synthesiser
is to use a lower bandwidth loop filter but this also removes all
of the advantage of fast channel change when using Frac-
tional-N, so the method used in ACE9030 is to calculate the
waveform of the ripple and then inject a compensation signal
onto the loop filter.

Fractional-N Compensation

If the Fractional-N system is operating correctly the

synthesiser sets the VCO frequency so that:

where F is the fraction given by:

The total division alternates between N

TOT

and N

TOT

+ 1 so

the frequency seen at the phase comparator will also alter-
nate. This divided signal f

FRACN

is compared with the uniform

comparison frequency f

COMP

and will give a phase error due to

the different periods. There will also be some phase error due
to leakage on the loop filter, leading to some correction pulses
on the charge pumps to maintain lock, but these will be very
small in a well designed synthesiser once the loop is locked,
so can be ignored here. For each

TOT

) cycle:

and so the phase error increases each cycle by:

This phase error gives an unwanted correction pulse on

the Ø

DOWN

output as the VCO frequency is too high for the

division ratio in use. The phase error increases as

TOT

cycles follow each other until eventually the accumulator
overflows and causes a

TOT

+ 1) cycle.

For each

TOT

+ 1) cycle:

Table 7

x (f

COMP

Period) .... (2)

TOT

VCO =

COMP

x (N

TOT +

F) .... (1)

MOD

F =

FRANC =

COMP

TOT + 1

TOT +

FRANC =

COMP

x 1+

TOT

TOT +

TOT

TOT +

( )

x (f

COMP

Period) .... (3)

TOT +

(F - 1)

Phase error = x (f

COMP

Period) .... (4)

TOT

x MOD

ACC

Iprop (0) = CN x Ibo .... (6)

CN = SF x N

TOT

Charge = x (f

COMP

Period) x Ibo .... (7)

MOD

ACC x SF

x (f

COMP

Period) x Iprop (0) .... (5)

TOT

x MOD

ACC

ACE9030

The value of SF can be found from any channel but to get

a quick estimate the highest frequency can be considered as
there is a fixed upper limit on CN of 256 so:

Putting suggested typical values into equation (7);

TOT

(max) = 10000, CN(max) = 250, and MOD = 8, and then

assuming the current flows for the whole comparison period
the current to be multiplied by ACC is Ibo / 320. The typical Ibo
is only 1

A so this is a very small current of around 3 nA and

would be too small to control accurately and certainly too small
for production testing.

The error signal to be cancelled is a narrow pulse at the

comparison frequency so the best cancellation of the whole
spectrum of the error is also a narrow pulse. It is not practical
to generate a variable width pulse to match the error pulse but
a fixed width variable amplitude pulse is possible and it can be
timed to approximately coincide with the error pulse to give
good cancellation.

The compensation current amplitude is also increased by

gating it with a small time window and in ACE9030 the gate is
set to two cycles of the reference clock which straddle the
active edge of the comparison frequency signal to the phase
comparator. The total reference division from reference clock
to comparison frequency is the programmable divider set by
NR in Word D multiplied by 1, 2, 4, or 8 as selected by the SM
bits also in Word D and this total may be called R

MAIN

, so for the

compensation current the scaling is R

MAIN

/ 2.

The charge needed is still as in equation (7) but the

current can be defined as:

where, in ACE9030, the compensation reference current Ico
is set by an external resistor RSC such that:

but this Ico must be chosen to cancel the error charge in
equation (7), and the scaling effect of 2 reference cycles in
R

MAIN

has been derived above, giving:

then removing SF to help evaluate the values needed:

this can then be further processed by replacing R

MAIN

and

TOT

(max) by the frequency ratios:

then when substituting these into equation (9) the f

COMP

terms

cancel leaving:

MAIN

= and N

TOT

(max) =

MAIN

For a typical AMPS cellphone the f

VCO

(max) for 45 MHz

I.F. is 938·97 MHz, f

CRYSTAL

is 14·85 MHz, MOD is 8 and

CN(max) can be assumed to be chosen around 200, giving Ico
= 0·198 x I

Fractional-N Mode with Speed-Up

When Speed-up is active the main proportional charge

pumps are run at an increased current and the integral charge
pumps are switched on to move the loop filter voltage faster.
The phase errors due to Fractional-N mode will be the same
as normal once the loop is locked so the compensation pulses
must be increased to match the proportional and integral
charge pump currents in order to allow a smooth change over
to normal mode at the end of Speed-up time. The same 2

L + 1

and K coefficients as used for the proportional and integral
charge pump currents are used on the compensation currents
so from equation (8):

Normal Mode:

Proportional Compensation Current:

Icomp(0) = ACC x Ico

Integral Compensation Current:

none = off

Speed-up Mode:

Proportional Compensation Current:

Icomp(1) = 2

L + 1

x ACC x Ico

Integral Compensation Current:

Icomp(2) = K x 2

L + 1

x ACC x Ico

Required Accuracy of Compensation

With the compensation scheme used in ACE9030 it is not

possible to get perfect cancellation of the loop disturbance by
the Fractional-N system due to the mis-match of the pulse
shapes leaving some high frequency terms, but if the areas
are matched there will be complete removal of the low fre-
quency components and the loop filter can be assumed able
to remove higher frequencies.

Typical timing waveforms for the phase error and its

compensation are shown in figure 28 for a loop operating in

's mode (hence MOD = 8), with a VCO at 1 GHz, and a

comparison frequency of 100 kHz (hence N

TOT

= 10,000 and

COMP

period = 10

s) so that each phase error can be found

from equation (4) as:

(ACC x 10

s) / (10,000 x 8) = ACC x 0·125 ns.

If the reference is a 12·8 MHz crystal, it gives a correction

pulse duration, two reference cycles, of
2/(12·8 MHz) = 156 ns.

If the charge pump current of 250

A is set by a CN value

of 250 the reference current Ibo from equation (6) is 1

A and

the compensation step current Ico can be found from equation
(10) as 0·2 x I

= 0·2

Areas of the error and the compensation pulses, equa-

tions (4) and (8) must match to get good low frequency
cancellation. Although shown as a very narrow pulse on Ø

DOWN

the phase error will often appear as a change in size of the
pulses on either Ø

DOWN

or Ø

which occur to maintain lock.

The following calculations would then apply to the changes
and give the same final result.

If there was no compensation the Ø

DOWN

pulses would give

sidebands at a level set by the loop filter capacitor values and
the VCO gain.

In a typical system the filter proportional capacitor can be

6·8 nF and the VCO could cover 30 MHz in 3 V, giving
10 MHz/V. Assuming for the moment that all error pulses are
the same at the level of a mid-range ACC value, say 4, and do

SF =

CN(max)

TOT

(max)

Icomp (0) = ACC x Ico .....(8)

Ico =

RSC

320

Ico = x x Ibo

MOD x N

TOT

(max)

Ico = x x Ibo ....(9)

CN (max)

MAIN

CRYSTAL

COMP

vco

(max)

COMP

MOD x f

VOC

(max)

Ico = x x Ibo ....(10)

CN (max)

CRYSTAL

MOD

ACE9030

Fig. 28 Fractional-N Phase Error And Compensation Pulse

calculation of

92 Hz and the level of the fundamental is again

(2/

) x peak level, giving 102 Hz deviation at a frequency now

x f

COMP

(12·5 kHz).

then becomes 102/12500 = 0·00816,

giving sidebands at up to 0·00408 times or 47 dBc.

Compensation pulses are used to cancel the effect of the

unwanted phase corrections, and if these match to within
10 % they should give a reduction of 20 dB in the fundemental
sideband levels, down to a worst figure of 67 dBc. The low
harmonics will also be adequately cancelled but higher har-
monics will be left to the loop filter to remove, and as the
bandwidth is set by the comparison frequency at only 8 times
the Fractional-N fundamental these harmonics will always be
well attenuated.

A typical system specification (AMPS) is 60 dBc so the

harmonic spectrum of the modulation needs to be considered
to find the manufacturing margins but if the Fractional-N
system is only used to help achieve correct lock times and
spurious levels (rather than solve all loop problems on its own)
then this example suggests that the compensation is not
critical and can give a performance advantage at little cost.

More critical compensation is needed if N

TOT

is less or if

the comparison period is longer, but these cancel if the VCO
stays at the same frequency, equation (4). Changing only the
comparison frequency in the above example would then give
the same 184 Hz deviation. In practice the loop filter capacitor
value is likely to also change to match the new comparison
frequency giving a peak deviation proportional to the compari-
son frequency. The modulation index is inversely proportional
to the comparison frequency so the final sideband level is not,
in practice, much affected by the comparison frequency
choice, but the separation from the carrier is affected. This all
suggests the above example is not just a spot typical result but
will apply over a broad range of systems and allow Fractional-
N to be used whenever desired.

not ramp in size and that the loop somehow stays on the
correct frequency:

Average phase error:

= mid-range ACC x 0·125 ns
= 4 x 0·125 ns = 0·5 ns

Charge into filter:

ERR

= 0·5 ns x 250

= 125 fC per pulse

Voltage step:

ERR

= Q

ERR

PROP

= 125 fC

6·8 nF = 18·4

Frequency step:

ERR

= V

ERR

x VCO gain

= 18·4

V x 10 MHz/V = 184 Hz

This gives a signal with a modulation frequency of

100 kHz with a step deviation of 184 Hz and if the loop is to
stay on frequency the waveform must ramp back between
steps, giving a sawtooth with an amplitude of

92 Hz. Fourier

analysis gives the level of the fundamental as (2/

) x peak

level, to give 58·6 Hz deviation and hence a modulation index

(peak deviation

modulation frequency) of only 0·000586,

putting it well into the narrow band f.m. category. At such small
deviations the sideband amplitude is

/2 of the carrier, giving

0·000293 times or 71 dBc. There will also be higher harmon-
ics present but these will all be at lower levels.

This calculation assumed all phase error pulses are the

same, but in reality the size varies in a pattern determined by
the fractional numerator (0 to 7) with a period equal to the
demoninator (8) times the comparison period. The fractions
that give the highest level of output at

x f

COMP

are

and

and with these the phase error changes in seven steps of a
staircase waveform until the eighth cycle, when the phase
resets and the pattern starts again. The loop will settle to the
correct average frequency by adding a d.c. offset for the mean
level of the staircase, leading to an error waveform which is
approximately a sawtooth wave with a step size of 7 in units of
ACC value. The peak deviation is then

times the previous

DOWN due to

phase error

COMPENSATION
PULSE

156 ns

Icomp(0) = 0.2

A x ACC

Iprop(0) = 250

ACC x
0.125 ns

ACE9030

APPLICATIONS HINTS

& V

Supply Pins

All V

pins must be well decoupled to ground. All V

pins

must be connected through very low impedance lines to the
ground point.

Serial Bus

Edge speeds on the serial bus should not be too fast in

order to avoid ringing which then can cause significant modu-
lation of the synthesisers, including CLK8.

Loop Filters

Both synthesisers use passive loop filters and typical

circuits can be either of these two configurations; the need for
the extra roll-off in the right hand circuit is only for the more
critical applications.

The loop filter needed is partly set by the application

specification and partly by the architectural design of the
cellphone. The main synthesiser will need to hop channels at
a rate set by the hand-off times of the network and so is well
defined. The auxiliary synthesiser is always on the same

Fig. 29 Typical Synthesiser Loop Filters

frequency and so could be a very slow loop to lock but in many
systems it will be powered down for as much time as possible
to economise on battery use and will then need to power-up
and lock quickly, leading to a more complex filter.

The values of the components in these filters may be

calculated with the help of appendix AB43 in the Personal
Communications Handbook or for a more complete analysis
the application note AN94, available from Mitel Semiconduc-
tor Marketing Department, may be used. This note was written
specifically for the NJ88C33 synthesiser but the mathematics
apply equally well to the ACE9030.

AFC Circuit

Fig. 30 Simplified Receiver Architecture

In order to fine trim the crystal oscillator frequency to the

correct value the ACE9030 includes a sampling circuit to
convert the final intermediate frequency signal (input on
AFCIN) to a logic signal and then to mix it down to a low
frequency output (on AFCOUT) for counting in the
microcontroller. The operation of this system can be explained
with the use of a simplified block diagram of the receiver
architecture as in figure 30.

Most receivers run the first mixer with a high-side local

oscillator controlled by the Main synthesiser, so a positive
crystal frequency error will give an increased First I.F. This is
then mixed down further by a low-side second oscillator, LO2
in the ACE9030, derived by multiplying the same crystal as
used for the Main synthesiser. A positive crystal frequency
error would now give a reduced second I.F. if the error in the
first I.F. is ignored, but the overall effect is an increase by an
amount slightly smaller than the increase in the first I.F.

The second I.F. signal AFCIN at around 450 kHz drives

the F.M. Discriminator to recover the modulation and also
feeds a third mixer where high-side injection is used to give a
very low output frequency, around 54 kHz, and is output on
AFCOUT for counting. This third mixer is driven by a clock
derived from the crystal but at a much reduced frequency so

the effect of the high-side mixing dominates to give an output
which drops in frequency when the crystal has a positive
frequency error. As a result of the chain of mixing stages the
error in the first local oscillator due to the crystal frequency will
give a similar frequency shift at the output of the third mixer
which is then a large percentage change in the frequency of
AFCOUT so it is possible to measure AFCOUT against the
crystal to determine the trim needed.

To illustrate the sensitivity of the AFC loop a numerical

example can be used, and in the calculations that follow the
selection of parameters for the synthesisers are also included
to show how some choices are made.

Assume the required receiver frequency is AMPS chan-

nel 1, that is 870·030 MHz and that the cellular terminal is built
with a 45 MHz first I.F., a 450 kHz second I.F., and a
14·85 MHz crystal.

To receive 870·030 MHz with a 45 MHz first I.F. needs

the first local oscillator, the Main synthesiser, to run at a
frequency of 870·030 + 45·000 = 915·030 MHz when using
high-side injection. For AMPS the most convenient compari-
son frequency is the channel spacing of 30 kHz so the total
division from VCO to phase comparator (N

TOT

as used else-

where) will be 30501 for this channel and the reference

PDA

VCO

PDP

PDI

VCO

FIRST

I.F

SECOND

I.F

LO2

MAIN

SYNTH

RX BAND

RECEIVED
SIGNAL FROM
BASESTATION

AFCIN

AFCOUT

AFC SAMPLE

AT 504 kHz

ACE9030

ACE9030

division will be 495 for a 14·85 MHz crystal; the term f

CRYSTAL

used to refer to the exact crystal frequency in the following
calculations.

Thus Main synthesiser (nominally 915·030 MHz) gener-

ates:

CRYSTAL

x 30501

495 = f

CRYSTAL

x 61·61818182

This result is independant of the chosen comparison fre-
quency which is given above as an illustration only.

With this drive to the first mixer the actual first I.F.

(nominally 45 MHz) is:

CRYSTAL

x 61·61818182 870·030 MHz

The second mixer is required to downconvert 45 MHz to

450 kHz so needs an LO2 at 44·550 MHz which is 3

CRYSTAL

and this integer multiplication is the reason for choosing a
14·85 MHz crystal. This mixer operates with low-side injection
so the actual second I.F. on the AFCIN pin (nominally
450 kHz) is:

CRYSTAL

x 61·61818182 870·030 MHz 3

CRYSTAL

= f

CRYSTAL

x 58·61818182 870·030 MHz

This signal feeds the F.M. discriminator to extract the

modulation and is also used to derive the AFC information.

The AFC mixer uses a 504 kHz clock derived from the

crystal (f

CRYSTAL

504

14850 = f

CRYSTAL

0·03393939) to high-

side downconvert AFCIN to a low frequency on AFCOUT,

giving:

CRYSTAL

x 0·03393939)

CRYSTAL

x 58·61818182 870·030 MHz).

This is 870·030 MHz f

CRYSTAL

x 58·58424243 and is the

difference between two large but similar numbers, one fixed
and the other a multiple of f

CRYSTAL

and will have an overall value

strongly dependent on f

CRYSTAL

To evaluate the sensitivity of the system consider a

+ 1 ppm change in crystal frequency, giving AFCOUT at
53·130 kHz instead of its nominal at 54 kHz, a shift of 870 Hz
or 1·61 %. This frequency can be counted in the
microcontroller using a timebase derived from f

CRYSTAL

or any

other crystal reference as the error in the timebase due to the
crystal is swamped by the changes in AFCOUT.

The counting of AFCOUT should be over a period long

enough to resolve changes of around 1 % which means at
least 2 ms but is normally a little longer to filter off some noise
and modulation on the signal; around 10 ms is a good starting
value for system development.

Once the crystal error has been estimated the DAC's

controlling the crystal frequency can be adjusted to bring the
whole cellular terminal into frequency alignment with the
basestation which is normally assumed to be very accurately
held at the correct frequency; effects like Doppler shift will be
significantly less than 1 ppm for all intended users. Some
damping in the control loop for the crystal will be needed to
avoid overshoot and hunting, possibly implemented as always
under-correcting the crystal or by limiting the slew rate of the
corrections.

ACE9030

Fig. 31 Complete cellular terminal, showing details of ACE9030 typical application.

ACE9020

ACE9030

RADIO INTERFACE &

TWIN SYNTHESISER

DOUT5

DOUT6

DOUT7

FIAB

FIA

VDDSA

VSSSA

FIMB

FIM

VSSD

PDI

PDP

RSMA

DECOUP

RSC

VDDD

AMP02

RXCD

TCHC

TCHB

ATA

AFCOUT

AUDIO

AFCIN

IREF

VSSL

VDDL

CLK8

C8B

VDDSUB2

MODMP

MODMN

TEST

PDA

VDDSUB

DOUT3

DOUT4

AMPP2

AMPN2

DAC3

AMPP1

AMPN1

AMP01

ADC2A

ADC2B

ADC4

DOUT0

VDDX

DOUT1

VDDA

VSSA

LO2

ADC1

ADC3A

ADC3B

ADC5

DOUT8

DAC2

DAC1

DOUT2

CIN1

CIN2

VCC

n.c.
n.c.

VCC_RX

RSET_RXLO

RXVCOIN

GND_RX

VCC_TXOSO

TXOSC-

TXOSC+

GND_DIV

RATIO_SEL

DIV_OUT-

DIV_OUT+

PD_1
PD_2
GND
BIAS_REF
VCC_TX
TXPA+
TXPA-
RSET_TXPA
GND_TXOSC
TANK+
TANK-
VCC_DIV
GND_OSC
MOD_CNTAL

FIRST

I.F. AT

45 MHz

RX BAND

RX SIGNAL

LNA

DUPLEXER &

R.F. FILTERS

CONTROL

VOLTAGE

MIXER

MATCHING

MAIN

LOOP

FILTER

RX VCO (FIRST

L.O.)

RX FRONT

-END

450

KHz

RSSI

I.F

. OUTPUT

I.F

AMP

2ND MIXER

ACE9010

L.O. TO

SECOND

MIXER

MULTIPLIER

TUNED

CIRCUIT

8 MHz PLL

LOOP

FILTER

RSSI

TX POWER SENSE

TEMPERATURE SENSE

SWITCHED 5V POWER

FOR AL

TERNA

TIVE

FRONT

-END

CRYSTAL OSCILLATOR

SECOND I.F. SIGNAL

(450 KHz)

POWER SUPPLY TO BE

DECOUPLED EXTENSIVELY

AUDIO

BAND-

PASS

FILTER

ACE9050

SYSTEM CONTROLLER

ACE9040

AUDIO

PROCESSOR

MEMORY

USER INTERFACE

KEYPAD & DISPLAY

ADDR

DATA

CONTROL & DATA

EARPIECE

M.O.

SPEECH PLUS

ONES OR CONTROL

CHANNEL

HANDSFREE

AUDIO LEVEL

SENSING

AUDIO SIGNAL

SPEECH

AND SA

FIL

TERS

TRANSMITTER ACTIVE

RECEIVE CARRIER DETECTED

BATTERY LEVEL SENSOR

TX POWER

CONTROL

OPTIONAL
BUFFER
FOR DAC3

{

TX POWER
REF. LEVEL

AUXILLAR

LOOP

FIL

TER

(D.C. BIAS IS

NEAR GROUND)

VHF VCC

TANK

TRANSMIT

MODULA

TION

PLL

CONTROL

VOL

AGE

TX SIGNAL

TECHNICAL DOCUMENTATION - NOT FOR RESALE

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Tel: +1 (613) 592 2122

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