3-3
3-3
Features
Microprocessor compatible control inputs
On chip control memory and address decoding
Row addressing
Master reset
32 crosspoint switches in 8 x 4 array
5.0V to 15.0V operation
Low crosstalk between switches
Low on resistance: 90
(typ.) at 13V
Matched switch characteristics
Switches frequencies up to 40MHz
Applications
PABX and key sytems
Data acquisition systems
Test equipment/instrumentation
Analog/digital multiplexers
Description
The MT8804A is a CMOS/LSI 8 x 4 Analog Switch
Array incorporating control memory (32 bits), deco-
der and digital logic level converters. This circuit has
digitally controlled analog switches having very low
"ON" resistance and very low "OFF" leakage current.
Switches will operate with analog signals at
frequencies to 40 MHz and up to 15.0Vp-p. A
"HIGH" on the Master Reset input switches all
channels "OFF" and clears the memory. This device
is ideal for crosspoint switching applications.
Ordering Information
MT8804AC
24 Pin Ceramic DIP
MT8804AE
24 Pin Plastic DIP
MT8804AP
28 Pin PLCC
-40 to 85C
Figure 1 - Functional Block Diagram
3 to 8
Decoder
Latches
8 x 4
Switch
Array
1
1
8
32
AE
D0 D1 D2 D3
VDD
VEE
VSS
A0
A1
A2
MR
Ji I/O (i=0-3)
Li I/O
(i=0-7)
ISSUE 2
October 1989
MT8804A
8 x 4 Analog Switch Array
CMOS
MT8804A
CMOS
3-4
Figure 2 - Pin Connections
* Plastic DIP and CERDIP only
Pin Description
Pin #*
Name
Description
1-3
L2-L0
L2-L0 Analog Lines (Inputs/Outputs): these are connected to the L2-L0 columns of the
switch array.
4
D0
D0 Data (Input): Active High.
5
J0
J0 Analog Junctor (Input/Output): this is connected to the J0 row of the switch array.
6
DI
DI Data (Input). Active High.
7
J1
J1 Analog Junctor (Input/Output): this is connected to the J1 row of the switch array.
8
D2
D2 Data (Input): Active High.
9
J2
J2 Analog Junctor (Input/Output): this is connected to the J2 row of the switch array.
10
D3
D3 Data (Input): Active High.
11
J3
J3 Analog Junctor (Input/Output): this is connected to the J3 row of the switch array.
12
V
SS
Digital Ground Reference.
13
V
EE
Negative Power Supply.
14-16
A0-A2
A0-A2 Address Lines (Inputs).
17
AE
Address Enable/Strobe (Input): enables function selected by address and data. Address
must be stable before AE goes high and D0-D3 must be stable on the falling edge of the
AE. Active High.
18
MR
Master RESET (Input): this is used to turn off all switches. Active High.
19-23
L7-L3
L7-L3 Analog Lines (Inputs/Outputs): these are connected to the L7-L3 columns of the
switch array.
24
V
DD
Positive Power Supply.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
24
23
22
21
20
19
18
17
L2
L1
L0
D0
J0
D1
J1
D2
J2
D3
J3
VSS
VDD
L3
L4
L5
L6
L7
MR
AE
A2
A1
A0
VEE
28 PIN PLCC
24 PIN CERDIP/PLASTIC DIP
4
5
6
7
8
9
10
11
25
24
23
22
21
20
19
N
C
L5
L6
L7
MR
AE
A2
NC
NC
D0
J0
D1
J1
D2
J2
A
1
3
2
1
2
8
2
7
2
6
1
2
1
3
1
4
1
5
1
6
1
7
1
8
L
0
L
1
L
2
V
D
D
L
3
L
4
D
3
J
3
V
S
S
V
E
E
A
0
N
C
CMOS
MT8804A
3-5
Functional Description
The MT8804A is a CMOS/LSI 8 X 4 Analog Switch
Array incorporating an 8 X 4 analog switch array,
address decoder, control memory, and digital logic
level converter.
The analog switch array is arranged in 8 rows and 4
columns. The row input/outputs are referred to as
Lines (L0-L7) and the column input/outputs as
Junctors (J0-J3). The crosspoint analog switches
interconnect the lines and junctors when turned "ON"
and provide a high degree of isolation when turned
"OFF". Interchannel crosstalk is minimal despite the
high density of the analog switch array. The control
memory of the MT8804A can be treated as an 8
word by 4 bit random access memory. The 8 words
are selected by the ADDRESS (A0-A2) inputs
through the on chip address decoder. Data is
presented to the memory via the four DATA inputs
(D0-D3). This data is asynchronously written into the
control memory whenever the ADDRESS ENABLE
(AE) input is HIGH. A HIGH level written into a
memory cell turns the corresponding crosspoint
switch "ON" while a LOW level causes the crosspoint
to turn "OFF".
Only the crosspoint switches corresponding to the
addressed memory word are affected when data is
written into the memory. The remaining switches
retain their previous states. By establishing
appropriate patterns in the control memory, any
combination of lines and junctors may be
interconnected. A HIGH level on the MASTER
RESET (MR) input returns all memory locations to a
LOW level and turns all crosspoint switches "OFF"
effectively isolating the lines from the junctors. The
digital logic level converters allow the digital input
levels to differ from limits of the analog levels
switched through the array. For example, with
Figure 3 - On Resistance vs. Temperature
(Input Signal Voltage=Supply Voltage/2)
V
DD
=5V, V
SS
=0V and V
EE
=-6V, the control inputs
can be driven by a 5V system while the analog
voltages through the crosspoint switches can swing
from +5V to -6V.
Figure 4 - On Resistance vs. Input Signal Voltage
Figure 5 - 8 x 8 Analog/Digital Switch
8x8 Analog/Digital Switch
Two MT8804s configured as shown, implement
an 8 x 8 analog/digital switch. The switch capacity
can be expanded to an M x N array of inputs/
outputs. Expansion in the M dimension is as
shown with the MT8804A lines (L0-L7)
commoned. Expansion in the N dimension is
accomplished by replicating the circuit shown and
connecting the MT8804A junctors (J0-J3) in
common. The address and data control inputs of
the MT8804A's can be connected in common for
any size and switch provided that the address
enable (AE) inputs are driven individually. A
particular signal path is connected by setting up
the appropriate signals or the address and data
lines and taking the corresponding address
enable input high. The master reset (MR), when
taken high, disconnects all signal paths.
MT8804A
CMOS
3-6
* Exceeding these values may cause permanent damage. Functional operation under these conditions is not implied.
DC Electrical Characteristics are at ambient temperature (25C).
Typical figures are for design aid only; not guaranteed and not subject to production testing.
Absolute Maximum Ratings
* -
Voltages are with respect to V
EE
unless otherwise stated
.
Parameter
Symbol
Min
Max
Units
1
Supply Voltage
V
DD-
V
SS
V
DD-
V
EE
V
SS-
V
EE
-0.3
-0.3
-0.3
16
16
16
V
V
V
2
Analog Input Voltage
V
INA
V
EE
-0.3
V
DD
+0.3
V
3
Digital Input Voltage
V
IN
V
SS
-0.3
V
DD
+0.3
V
4
Current on any Logic Pin
I
10
mA
5
Storage Temperature
T
S
-65
+150
C
6
Package Power Dissipation
PLASTIC DIP
CERDIP
P
D
P
D
0.6
1.2
W
W
Recommended Operating Conditions
- Voltages are with respect to V
EE
unless otherwise stated.
Characteristics
Sym
Min
Typ
Max
Units
Test Conditions
1
Operating Temperature
T
O
-40
25
85
C
2
Supply Voltage
V
DD
-V
SS
V
DD
-V
EE
V
SS
-V
EE
5
5
0
5
10
5
15
15
10
V
V
V
3
Analog Input Voltage
V
INA
V
EE
V
DD
V
4
Digital Input Voltage
V
IN
V
SS
V
DD
V
DC Electrical Characteristics
-
Voltages are with respect to V
EE
=V
SS
=0V.
Characteristics
Sym
Min
Typ
Max
Units
Test Conditions
1
Quiescent Supply Current
I
DD
1
100
A
V
DD
=15V. All digital inputs at
V
IN
=V
SS
or V
DD
2
Off-state Leakage Current
(Any line to any junctor)
I
OFF
0.1
500
nA
V
DD
=13V, Switch is `Off'
IV
Ji
- V
Lj
I = V
DD
- V
EE
3
Input Logic "0" level
V
IL
3.0
1.5
V
V
V
DD
=10V
V
DD
=5V
V
INA
=V
DD
through 1k
4
Input Logic "1" level
V
IH
7.0
3.5
V
V
V
DD
=10V
V
DD
=5V
V
INA
=V
DD
through 1k
5
Maximum current through
Crosspoint Switch
I
MAX
8.0
mA
V
DD
=13V
DC Electrical Characteristics
-
Switch Resistance
- V
DC
is the external DC offset applied at the analog I/O pins.
Characteristics
Sym
25C
70C
85C
Units
Test Conditions
Min
Typ
Max
Typ
Typ
1 On-state
V
DD
=13V
Resistance V
DD
=10V
V
DD
= 5V
R
ON
60
90
105
290
108
160
650
105
120
320
110
125
325
V
SS
=V
EE
=0V,V
DC
=V
DD
/2,
IV
Ji
- V
Lj
I = 0.6V
2 Difference in on-state
resistance between
two switches
V
DD
=13V
V
DD
=10V
R
ON
20
30
20
30
20
30
V
SS
=V
EE
=0V,V
DC
=V
DD
/2,
IV
Ji
- V
Lj
I = 0.6V
CMOS
MT8804A
3-7
AC Electrical Characteristics are at ambient temperature (25C).
Typical figures are for design aid only; not guaranteed and not subject to production testing.
AC Electrical Characteristics are at ambient temperature (25C).
Typical figures are for design aid only; not guaranteed and not subject to production testing.
Note 1 R
L
= 10k
,
C
L
=50pF
Note 2 R
L
= 1k
,
C
L
=50pF
Digital Input rise time (tr) and fall time (tf) = 5ns.
AC Electrical Characteristics
- Crosspoint Performance
-V
DC
is the external DC offset applied at the analog
I/O pins. Voltages are with respect to V
DD
=10V, V
SS
=V
EE
=0V unless otherwise stated.
Characteristics
Sym
Min
Typ
Max
Units
Test Conditions
1
Switch Line Capacitance
C
IS
5
pF
2
Switch Junctor Capacitance
C
OS
20
pF
3
Feedthrough Capacitance
C
I
0.2
pF
4
Frequency Response
Channel "ON"
20LOG(V
OUT
/
V
INA
) = -3dB
F
3dB
40
MHz
Switch is "ON"; V
DC
=5V,
V
INA
=5Vpp sinewave
f= 1kHz; R
L
= 1k
5
Total Harmonic Distortion
V
DD
=15V/V
DC
=7.5V
V
DD
=10V/V
DC
=5V
V
DD
=5V/V
DC
=2.5V
THD
0.1
0.2
1.0
%
%
%
Switch is "ON"; V
EE=
V
SS
=0V
V
INA
=5Vpp sinewave
f= 1kHz;
R
L
= 10k
6
Feedthrough
Channel "OFF"
Feed.=20LOG (V
OUT
/
V
INA
)
FDT
-50
dB
All Switches "OFF"; V
INA
=
5Vpp sinewave f= 1MHz;
R
L
=
1k
.
V
DC
=5V
7
Crosstalk between any two
channels for switches Li - Ji and
Lj - Jj.
Li - Ji is "ON"
Lj - Jj is "OFF"
Xtalk=20LOG (V
Jj
/V
Li
).
X
talk
-40
-90
dB
dB
V
INA
=2Vpp sinewave
f= 1.0MHz; R
L
= 600
.
V
INA
=2Vpp sinewave
f= 3.4kHz; R
L
= 600
.
V
DC
= 5V
8
Propagation delay through
switch
t
PS
10
ns
C
L
=50pF
AC Electrical Characteristics
- Control and I/O Timings
- Voltages are with respect to V
SS
=V
EE
=0V unless
otherwise stated.
Characteristics
Sym
Min
Typ
Max
Units
Test Conditions
1
Digital Input Capacitance
C
DI
5
pF
V
DD
=10V
2
Setup Time D0-D3 to AE
t
DS
150
200
ns
ns
V
DD
=10V
V
DD
=5V
3
Hold Time D0-D3 to AE
t
DH
120
300
ns
ns
V
DD
=10V
V
DD
=5V
4
Setup Time Address to AE
t
AS
0
50
ns
ns
V
DD
=10V
V
DD
=5V
5
Hold Time Address to AE
t
AH
120
300
ns
ns
V
DD
=10V
V
DD
=5V
6
AE Pulse Width
t
AEW
100
250
ns
ns
V
DD
=10V
V
DD
=5V
7
AE to Switch Status Delay
t
PAE
200
650
300
900
ns
ns
V
DD
=10V
V
DD
=5V
8
DATA to Switch Status Delay
t
PLH
t
PHL
250
650
400
1000
ns
ns
V
DD
=10V
V
DD
=5V
9
MR to Switch Status Delay
t
MR
t
MRR
250
500
200
500
400
600
350
750
ns
ns
ns
ns
V
DD
=10V
V
DD
=5V
V
DD
=10V
V
DD
=5V
See Note 1
See Note 1
See Note 2
MT8804A
CMOS
3-8
Figure 6 - Control Memory Timing Diagram
Table 1 - Address Decode Truth Table
NOTES:
0 - Low Logic Level
1 - High Logic Level
X - Don't Care Condition
+ - Indicates Connection Between Junctor and Addressed Line
- Indicates No Connection Between Junctor and Addressed Line
Memory
Reset
MR
Address
Enable
AE
Address
Addressed
Line
Input Data To Control
Memory
Junctors Connected To
Addressed Line
A2
A1
A0
D3
D2
D1
D0
J3
J2
J1
J0
1
X
X
X
X
ALL
X
X
X
X
All Switches "OFF"
0
0
X
X
X
NONE
X
X
X
X
No Change of State
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
L0
L0
L0
L0
L0
L0
L0
L0
L0
L0
L0
L0
L0
L0
L0
L0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
0
0
1
1
0
0
0
0
1
1
L1
L1
0
1
0
1
0
1
0
1
+
+
+
+
0
0
1
1
0
0
1
1
0
0
L2
L2
0
1
0
1
0
1
0
1
+
+
+
+
0
0
1
1
0
0
1
1
1
1
L3
L3
0
1
0
1
0
1
0
1
+
+
+
+
0
0
1
1
1
1
0
0
0
0
L4
L4
0
1
0
1
0
1
0
1
+
+
+
+
0
0
1
1
1
1
0
0
1
1
L5
L5
0
1
0
1
0
1
0
1
+
+
+
+
0
0
1
1
1
1
1
1
0
0
L6
L6
0
1
0
1
0
1
0
1
+
+
+
+
0
0
1
1
1
1
1
1
1
1
L7
L7
0
1
0
1
0
1
0
1
+
+
+
+
t
AEW
t
AS
t
DH
t
PLH
/t
PHL
t
PAE
t
MR
t
MRR
t
PLH
/t
PHL
t
DS
t
AH
50%
50%
50%
50%
50%
50%
50%
50%
50%
MR
AE
ADDRESS
D0-D3
SWITCH
ON
OFF
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