5-11
Features
1200 baud BELL 202 and CCITT V.23
Frequency Shift Keying (FSK) demodulation
Compatible with Bellcore TR-NWT-000030 and
SR-TSV-002476
High input sensitivity: -36dBm
Simple serial 3-wire data interface eliminating
the need for a UART
Power down mode
Internal gain adjustable amplifier
Carrier detect status output
Uses 3.579545 MHz crystal or ceramic
resonator
Single 5V power supply
Low power CMOS technology
Applications
Calling Number Delivery (CND), Calling Name
Delivery (CNAM) and Calling Identity on Call
Waiting (CIDCW) features of Bellcore CLASS
SM
service
Feature phones
Phone set adjunct boxes
FAX machines
Telephone Answering machines
Database query systems
Description
The MT8841 Calling Number Identification Circuit
(CNIC) is a CMOS integrated circuit providing an
interface to various calling line information delivery
services that utilize 1200 baud BELL 202 or CCITT
V.23 FSK voiceband data transmission schemes.
The CNIC receives and demodulates the signal and
outputs data into a simple 3-wire serial interface.
Typically, the FSK modulated data containing
information on the calling line is sent before alerting
the called party or during the silent interval between
the first and second ring using either CCITT V.23
recommendations or Bell 202 specifications.
The CNIC accepts and demodulates both CCITT
V.23 and BELL 202 signals. Along with serial data
and clock, the CNIC provides a data ready signal to
indicate the reception of every 8-bit character sent
from the Central Office. The received data can be
processed externally by a microcontroller, stored in
memory, or displayed as is, depending on the
application.
Ordering Information
MT8841AE
16 Pin Plastic DIP
MT8841AS
16 Pin SOIC
MT8841AN
20 Pin SSOP
-40 C to +85 C
Figure 1 - Functional Block Diagram
CLASS
SM
is a service mark of Bellcore
GS
IN-
IN+
CAP
V
Ref
DATA
DR
DCLK
CD
PWDN
OSC1
OSC2
V
SS
V
DD
IC1
IC2
Receive
Bandpass
Filter
Bias
Generator
FSK
Demodulator
Data and Timing
Carrier
Detector
Clock
Generator
Recovery
to other
circuits
-
+
ISSUE 4
May 1995
MT8841
Calling Number Identification Circuit
CMOS
MT8841
5-12
Figure 2 - Pin Connections
Pin Description
Pin
#
Name
Description
16
20
1
1
IN+
Non-inverting Op-Amp (Input).
2
2
IN-
Inverting Op-Amp (Input).
3
3
GS
Gain Select (Output). Gives access to op-amp output for connection of feedback resistor.
4
4
V
Ref
Voltage Reference (Output). Nominally V
DD/2
. This is used to bias the op-amp inputs.
5
5
CAP
Capacitor. Connect a 0.1F capacitor to V
SS
.
6
7
OSC1 Oscillator (Input). Crystal or ceramic resonator connection. This pin can be driven directly
from an external clocking source.
7
9
OSC2 Oscillator (Output). Crystal or ceramic resonator connection. When OSC1 is driven by an
external clock, this pin should be left open.
8
10
V
SS
Power supply ground.
9
11
DCLK Data Clock (Output). Outputs a clock burst of 8 low going pulses at 1202.8Hz (3.5795MHz
divided by 2976). Every clock burst is initiated by the DATA stop bit start bit sequence. When
the input DATA is 1202.8 baud, the positive edge of each DCLK pulse coincides with the
middle of the data bits output at the DATA pin. No DCLK pulses are generated during the start
or stop bits. Typically, DCLK is used to clock the eight data bits from the 10 bit data word into a
serial-to-parallel converter.
10
12
DATA
Data (Output). Serial data output corresponding to the FSK input and switching at the input
baud rate. Mark frequency at the input corresponds to a logic high, while space frequency
corresponds to a logic low at the DATA output. With no FSK input, DATA is at logic high. This
output stays high until CD
has become active.
11
13
DR
Data Ready (Open Drain Output). This output goes low after the last DCLK pulse of each
word. This can be used to identify the data (8-bit word) boundary on the serial output stream.
Typically, DR is used to latch the eight data bits from the serial-to-parallel converter into a
microcontroller.
12
14
CD
Carrier Detect (Open Drain Output). A logic low indicates that a carrier has been present for
a specified time on the line. A time hysteresis is provided to allow for momentary discontinuity
of carrier.
13
15
PWDN Power Down (Input). Active high, Schmitt Trigger input. Powers down the device including the
input op-amp and the oscillator.
14
16
IC1
Internal Connection 1. Connect to V
SS
.
15
19
IC2
Internal Connection 2. Internally connected, leave open circuit.
16
20
V
DD
Positive power supply voltage.
6,8
17,
18
NC
No Connection.
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
IN+
IN-
GS
VRef
CAP
OSC1
OSC2
VSS
VDD
IC2
IC1
PWDN
CD
DR
DATA
DCLK
16 PIN PLASTIC DIP/SOIC
1
2
3
4
5
6
7
8
9
10
11
12
20
19
18
17
16
15
14
13
IN+
IN-
GS
VRef
CAP
NC
OSC1
NC
OSC2
VSS
20 PIN SSOP
VDD
IC2
NC
NC
PWDN
CD
DR
DATA
DCLK
IC1
MT8841
5-13
Functional Description
The MT8841 Calling Number Identification Circuit
(CNIC) is a device compatible with the Bellcore
proposal (TR-NWT-000030) on generic requirements
for transmitting asynchronous voiceband data to
Customer Premises Equipment (CPE) from a serving
Stored Program Controlled Switching System
(SPCS) or a Central Office (CO). This data
transmission technique is applicable in a variety of
services like Calling Number Delivery (CND), Calling
Name Delivery (CNAM) or Calling Identity Delivery
on Call Waiting (CIDCW) as specified in Custom
Local Area Signalling Service (CLASS
SM
) calling
information delivery features by Bellcore.
With CND, CNAM and CIDCW service, the called
subscriber has the capability to display or to store
the information on the calling party which is sent by
the CO and received by the CNIC.
In the CND service, information about a calling party
is embedded in the silent interval between the first
and second ring. During this period, the CNIC
receives and demodulates the 1200 baud FSK signal
(compatible with Bell-202 specification) and outputs
data into a 3-wire serial interface.
In the CIDCW service, information about a second
calling party is sent to the subscriber, while they are
engaged in another call. During this period, the CNIC
receives and demodulates the FSK signal as in the
CND case.
The CNIC is designed to provide the data
transmission interface required for the above service
Figure 3 - Differential Input Configuration
C1
R1
C2
R4
R3
R2
R5
IN+
IN-
GS
V
Ref
MT8841
DIFFERENTIAL INPUT AMPLIFIER
C1 = C2 = 10 nF
R1 = R4 = R5 = 100 k
R2 = 60k
, R3 = 37.5 k
R3 = (R2R5) / (R2 + R5)
VOLTAGE GAIN
(A
V
diff) = R5/R1
INPUT IMPEDANCE
(Z
IN
diff) = 2
R1
2
+ (1/
C)
2
Figure 4 - Single-Ended Input Configuration
at the called subscriber location either in the on-hook
case as in CND, or the off-hook case, as in
CIDCW. The functional block diagram of the CNIC
is shown in Figure 1. Note however, for CIDCW
applications, a separate CAS (CPE Alerting Signal)
detector is required.
In Europe, Caller ID and CIDCW services are being
proposed. These schemes may be different from
their North American counterparts. In most cases,
1200 baud CCITT V.23 FSK is used instead of Bell
202. Because the CNIC can also demodulate 1200
baud CCITT V.23 with the same performance, it is
suitable for these applications.
Although the main application of the CNIC is to
support CND and CIDCW service, it may also be
used in any application where 1200 baud Bell 202
and/or CCITT V.23 FSK data reception is required.
Input Configuration
The input arrangement of the MT8841 provides an
operational amplifier, as well as a bias source (V
Ref
)
which is used to bias the inputs at V
DD/2
. Provision is
made for connection of a feedback resistor to the op-
amp output (GS) for adjustment of gain. In a single-
ended configuration, the input pins are connected as
shown in Figure 4.
Figure 3 shows the necessary connections for a
differential input configuration.
User Interface
The CNIC provides a powerful 3-pin interface which
can reduce the external hardware and software
requirements. The CNIC receives the FSK signal,
demodulates it, and outputs the extracted data to the
DATA pin. For each received stop bit start bit
sequence, the CNIC outputs a fixed frequency clock
string of 8 pulses at the DCLK pin. Each clock rising
C
R
IN
IN+
IN-
GS
V
Ref
MT8841
VOLTAGE GAIN
(A
V
) = R
F
/ R
IN
R
F
MT8841
5-14
edge corresponds to the centre of each DATA bit cell
(providing the incoming baud rate matches the DCLK
rate). DCLK is not generated for the stop and start
bits. Consequently, DCLK will clock only valid data
into a peripheral device such as a serial to parallel
shift register or a micro-controller. The CNIC also
outputs an end of word pulse (data ready) at the DR
pin. The data ready signal indicates the reception of
every 10-bit word sent from the Central Office. This
output is typically used to interrupt a micro-controller.
The three outputs together, eliminate the need for a
UART (Universal Asynchronous Receiver
Transmitter) or the high software overhead of
performing the UART function (asynchronous serial
data reception).
Note that the 3-pin interface may also output data
generated by voice since these frequencies are in
the input frequency detection band of the device.
The user may choose to ignore these outputs when
FSK data is not expected, or force the CNIC into its
powerdown mode.
Power Down Mode
For applications requiring reduced power
consumption, the CNIC can be forced into power
down when it is not needed to receive FSK data.
This is done by pulling the PWDN pin high. In
powerdown mode, the crystal oscillator, op-amp and
internal circuitry are all disabled and the CNIC will
not react to the input signal. DATA and DCLK are at
logic high, and DR and CD
are at high impedance or
at logic high when pulled up with resistors.The CNIC
can be awakened for reception of the FSK signal by
pulling the PWDN pin to ground (see Figure 9).
Carrier Detect
The presence of the FSK signal is indicated by a
logic low at the carrier detect (CD) output. This
output has built in hysteresis to prevent toggling
when the received signal is shortly interrupted. Note
that the CD
output is also activated by voice since
these frequencies are in the input frequency
detection band of the device. The user may choose
to ignore this output when FSK data is not expected,
or force the CNIC into its powerdown mode.
Figure 5 - Common Crystal Connection
Crystal Oscillator
The CNIC uses a crystal oscillator as the master
timing source for filters and the FSK demodulator.
The crystal specification is as follows:
Frequency:
3.579545 MHz
Frequency tolerance:
0.1%(-40C+85C)
Resonance mode
:
Parallel
Load capacitance:
18 pF
Maximum series resistance
: 150 ohms
Maximum drive level (mW):
2 mW
e.g. CTS MP036S
A number of MT8841 devices can be connected as
shown in Figure 5 such that only one crystal is
required. The connection between OSC2 and OSC1
can be D.C. coupled as shown, or A.C. coupled
using 30pF capacitors. Alternatively, the OSC1
inputs on all devices can be driven from a CMOS
buffer (dc coupled) with the OSC2 outputs left
unconnected.
VRef and CAP Inputs
V
Ref
is the output of a low impedance voltage source
equal to V
DD/2
and is used to bias the input op-amp.
A 0.1F capacitor is required between CAP and V
SS
to suppress noise on V
Ref.
OSC1
OSC2
OSC1
OSC2
OSC1
OSC2
3.579545 MHz
MT8841
MT8841
MT8841
to the
next MT8841
MT8841
5-15
Applications
The circuit shown in Figure 6 illustrates the use of
the MT8841 device in a typical FSK receiver system.
Bellcore Special Report SR-TSV-002476 specifies
that the FSK receiver should be able to receive FSK
signal levels as follows:
Received Signal Level at 1200Hz:
-32dBm to -12dBm
Received Signal Level at 2200Hz:
-36dBm to -12dBm
This condition can be attained by choosing suitable
values of R1 and R2. The MT8841 configured in a
unity gain mode as shown in Fig. 6 meets the above
level requirements.
For applications requiring detection of lower FSK
signal level, the input op amp may be configured to
provide adequate gain.
Figure 6 - Application Circuit (Single-Ended Input)
C1
+5V
R1
R2
C2
X-tal
MT8841
IN +
IN -
GS
VRef
CAP
OSC1
OSC2
VSS
VDD
IC2
IC1
PWDN
CD
DR
DATA
DCLK
C3
R3
R4
To
Controller
Notes:
R1, R2 = 100 k
1%
R3, R4 = 100 k
10%
C1, C2, C3 = 0.1
F 20%
X-tal = 3.579545 MHz
MT8841
5-16
* Exceeding these values may cause permanent damage. Functional operation under these conditions is not implied.
DC Electrical Characteristics are over recommended operating conditions unless otherwise stated.
* Typical figures are at 25C and are for design aid only.
Absolute Maximum Ratings
* -
Voltages are with respect to V
SS
unless otherwise stated.
Parameter
Symbol
Min
Max
Units
1
DC Power Supply Voltage V
DD
to V
SS
V
DD
-0.3
6
V
2
Voltage on any pin
V
P
-0.3
V
DD
+0.3
V
3
Current at any pin (except V
DD
and V
SS
)
I
I/O
10
mA
4
Storage Temperature
T
ST
-65
+150
C
5
Package Power Dissipation
P
D
500
mW
Recommended Operating Conditions
- Voltages are with respect to ground (V
SS
) unless otherwise stated
Characteristics
Sym
Min
Typ
Max
Units
Test Conditions
1
DC Power Supply Voltage
V
DD
4.5
5.0
5.5
V
2
Clock Frequency
f
OSC
3.579545
MHz
3
Tolerance on Clock Frequency
fc
0.2
%
4
Operating Temperature
-40
+85
C
DC Electrical Characteristics
Characteristics
Sym
Min
Typ*
Max
Units
Test Conditions
1
S
U
P
P
L
Y
Standby Supply Current
I
DDQ
15
100
A
PWDN=V
DD
2
Operating Supply Current
I
DD
3
5
mA
PWDN=V
SS
3
Power Consumption
PO
28
mW
4
DATA
DCLK
Low Level Output Voltage
High Level Output Voltage
V
OL
V
OH
V
DD
-0.4
0.4
V
V
I
OL
=2.5mA
I
OH
=0.8mA
5
DR
CD
Sink Current
I
OL
2.5
mA
V
OL
=0.4V
6
PWDN
Low Level Input Voltage
High Level Input Voltage
V
IL
V
IH
V
DD
-1.2
1.2
V
V
7
Input Current
I
IN
10
A
V
SS
V
IN
V
DD
8
VRef
Output Voltage
V
Ref
2.45
2.5
2.55
V
V
DD
=5.0V
No Load
9
Output Resistance
R
Ref
2
k
MT8841
5-17
Electrical characteristics are over recommended operating conditions, unless otherwise stated.
Typical figures are at 25C and are for design aid only: not guaranteed and not subject to production testing.
AC Electrical Characteristics are over recommended operating conditions, unless otherwise stated.
Typical figures are at 25C and are for design aid only: not guaranteed and not subject to production testing.
Electrical Characteristics
- Gain Setting Amplifier
Characteristics
Sym
Min
Typ
Max
Units
Test Conditions
1
Input Leakage Current
I
IN
1
A
V
SS
V
IN
V
DD
2
Input Resistance
R
in
5
M
3
Input Offset Voltage
V
OS
25
mV
4
Power Supply Rejection Ratio
PSRR
30
40
dB
1kHz ripple on V
DD
5
Common Mode Rejection
CMRR
30
40
dB
V
CMmin
V
IN
V
CMmax
6
DC Open Loop Voltage Gain
A
VOL
30
32
dB
7
Unity Gain Bandwidth
f
C
.2
0.3
MHz
8
Output Voltage Swing
V
O
0.5
V
DD
-0.5
V
pp
Load
50k
9
Maximum Capacitive Load (GS)
C
L
100
pF
10 Maximum Resistive Load (GS)
R
L
50
k
11
Common Mode Range Voltage
V
CM
1.0
V
DD
-1.0
V
AC Electrical Characteristics
- FSK Detection
Characteristics
Sym
Min
Typ
Max
Units
Notes*
1
Input Detection Level
-36
12.3
-9
275
dBm
mV
1, 2, 3
1, 2, 3
2
Input Baud Rate
1188
1200
1212
baud
7
3
Input Frequency Detection
Bell 202 1 (Mark)
Bell 202 0 (Space)
CCITT V.23 1 (Mark)
CCITT V.23 0 (Space)
1188
2178
1280.5
2068.5
1200
2200
1300
2100
1212
2222
1319.5
2131.5
Hz
Hz
Hz
Hz
4
Input Noise Tolerance
20 log
(
SNR
20
dB
2, 3, 4, 5
}
7
BELL 202 Frequencies
}
7
CCITT V.23 Frequencies
)
signal
noise
MT8841
5-18
AC Electrical Characteristics are over recommended operating conditions unless otherwise stated.
Typical figures are at 25C and are for design aid only, not guaranteed and not subject to production testing.
*Notes:
1.
dBm=decibels above or below a reference power of 1mW into 600
.
2.
Using unity gain test circuit shown in Figure 6.
3.
Mark and Space frequencies have the same amplitude.
4.
Band limited random noise (200-3200Hz).
5.
Referenced to the minimum input detection level.
6.
FSK input data at 1200 12 baud.
7.
OSC1 at 3.579545 MHz 0.2%.
8.
10k to V
SS
, 50pF to V
SS.
9.
10k to V
DD
, 50pF to V
SS
.
10.
Function of signal condition.
11.
The device will stop functioning within this time, but more time may be required to reach I
DDQ
.
12.
For a repeating mark space sequence, the data stream will typically have equal 1 and 0 bit durations.
Figure 7 - DATA and DCLK Output Timing
Figure 8 - DR Output Timing
AC Electrical Characteristics
- Timing
Characteristics
Sym
Min
Typ
Max
Units
Notes*
1
PWDN
OSC1
Power-up time
t
PU
35
50
ms
2
Power-down time
t
PD
100
1000
s
11
3
CD
Input FSK to CD
low delay
t
IAL
25
ms
4
Input FSK to CD
high delay
t
IAH
8
ms
5
Hysteresis
8
ms
6
DATA
Rate
1188
1200
1212
bps
6,12
7
Input FSK to DATA delay
t
IDD
1
5
ms
8
DATA
DCLK
Rise time
t
R
200
ns
8
9
Fall time
t
F
200
ns
8
10
DATA to DCLK delay
t
DCD
6
416
s
6, 7, 10
11
DCLK to DATA delay
t
CDD
6
416
s
6, 7, 10
12
DCLK
Frequency
1200
1202.8
1205
Hz
7
13
High time
t
CH
415
416
417
s
7
14
Low time
t
CL
415
416
417
s
7
15
DCLK
DR
DCLK to DR delay
t
CRD
415
416
417
s
7
16
DR
Rise time
t
RR
10
s
9
17
Fall time
t
FF
200
ns
9
18
Low time
t
RL
415
416
417
s
7
DATA
DCLK
t
R
t
DCD
t
CDD
t
R
t
F
t
CL
t
CH
t
F
t
FF
t
RR
t
RL
DR
MT8841
5-19
Figure 9 - Input and Output Timing (Bellcore CND Service)
Figure 10 - Serial Data Interface Timing
First Ringing
Input FSK
Data
Second
Ringing
2 sec
channel seizure
Mark state
checksum
TIP/RING
PWDN
OSC2
CD *
DATA
DCLK
DR *
High (Input Idle)
* with external pull-up resistor
t
PU
500ms
(min)
t
IAL
200ms
(min)
t
PD
t
IAH
High (Input Idle)
TIP/RING
DATA
DCLK
DR *
stop
start
stop
start
stop
start
stop
start
b0 b1 b2 b3 b4 b5 b6 b7
b7
1
0
b0 b1 b2 b3 b4 b5 b6 b7
1
0
b0 b1 b2
1
0
b7
b0 b1 b2 b3 b4 b5 b6 b7
b0 b1 b2 b3 b4 b5 b6 b7
b0 b1 b2
stop
start
stop
start
t
IDD
t
CRD
* with external pull-up resistor
MT8841
5-20
NOTES:
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