4-11

MT8870D/MT8870D-1

Integrated DTMF Receiver

Features

Complete DTMF Receiver

Low power consumption

Internal gain setting amplifier

Adjustable guard time

Central office quality

Power-down mode

Inhibit mode

Backward compatible with
MT8870C/MT8870C-1

Applications

Receiver system for British Telecom (BT) or
CEPT Spec (MT8870D-1)

Paging systems

Repeater systems/mobile radio

Credit card systems

Remote control

Personal computers

Telephone answering machine

Description

The MT8870D/MT8870D-1 is a complete DTMF
receiver integrating both the bandsplit filter and
digital decoder functions. The filter section uses
switched capacitor techniques for high and low
group filters; the decoder uses digital counting
techniques to detect and decode all 16 DTMF tone-
pairs into a 4-bit code. External component count is
minimized by on chip provision of a differential input
amplifier, clock oscillator and latched three-state bus
interface.

Ordering Information

MT8870DE/DE-1

18 Pin Plastic DIP

MT8870DC/DC-1

18 Pin Ceramic DIP

MT8870DS/DS-1

18 Pin SOIC

MT8870DN/DN-1

20 Pin SSOP

MT8870DT/DT-1

20 Pin TSSOP

-40 °C to +85 °C

Figure 1 - Functional Block Diagram

PWDN

IN +

IN -

OSC1

OSC2

St/GT

ESt

STD

TOE

VDD

VSS

VRef

INH

Bias

Circuit

Dial

Tone
Filter

High Group

Filter

Low Group

Filter

Digital

Detection
Algorithm

Code

Converter
and Latch

St
GT

Steering
Logic

Chip

Power

Chip
Bias

VRef
Buffer

Zero Crossing
Detectors

to all
Chip
Clocks

ISSUE 3

May1995

ISO

-CMOS

MT8870D/MT8870D-1

ISO

-CMOS

4-12

Figure 2 - Pin Connections

Pin Description

Pin #

Name

Description

IN+

Non-Inverting Op-Amp (Input).

IN-

Inverting Op-Amp (Input).

Gain Select. Gives access to output of front end differential amplifier for connection of
feedback resistor.

Ref

Reference Voltage (Output). Nominally V

/2 is used to bias inputs at mid-rail (see Fig. 6

and Fig. 10).

INH

Inhibit (Input). Logic high inhibits the detection of tones representing characters A, B, C
and D. This pin input is internally pulled down.

PWDN

Power Down (Input). Active high. Powers down the device and inhibits the oscillator. This
pin input is internally pulled down.

OSC1

Clock (Input).

OSC2

Clock (Output). A 3.579545 MHz crystal connected between pins OSC1 and OSC2
completes the internal oscillator circuit.

Ground (Input). 0V typical.

TOE

Three State Output Enable (Input). Logic high enables the outputs Q1-Q4. This pin is
pulled up internally.

11-

12-

Q1-Q4

Three State Data (Output). When enabled by TOE, provide the code corresponding to the
last valid tone-pair received (see Table 1). When TOE is logic low, the data outputs are high
impedance.

StD

Delayed Steering (Output).Presents a logic high when a received tone-pair has been
registered and the output latch updated; returns to logic low when the voltage on St/GT falls
below V

TSt

ESt

Early Steering (Output). Presents a logic high once the digital algorithm has detected a
valid tone pair (signal condition). Any momentary loss of signal condition will cause ESt to
return to a logic low.

St/GT

Steering Input/Guard time (Output) Bidirectional. A voltage greater than V

TSt

detected at

St causes the device to register the detected tone pair and update the output latch. A
voltage less than V

TSt

frees the device to accept a new tone pair. The GT output acts to

reset the external steering time-constant; its state is a function of ESt and the voltage on St.

Positive power supply (Input). +5V typical.

No Connection.

1
2
3
4
5
6
7
8
9

18
17
16
15
14
13
12
11

IN+

IN-

VRef

INH

PWDN

OSC1
OSC2

VSS

VDD
St/GT
ESt
StD
Q4
Q3
Q2
Q1
TOE

18 PIN CERDIP/PLASTIC DIP/SOIC

1
2
3
4
5
6
7
8
9

20
19
18
17
16
15
14
13

IN+

IN-

VRef

INH

PWDN

OSC1
OSC2

VSS

20 PIN SSOP/TSSOP

VDD
St/GT
ESt
StD

Q4
Q3
Q2
Q1
TOE

ISO

-CMOS

MT8870D/MT8870D-1

4-13

Functional Description

The MT8870D/MT8870D-1 monolithic DTMF
receiver offers small size, low power consumption
and high performance. Its architecture consists of a
bandsplit filter section, which separates the high and
low group tones, followed by a digital counting
section which verifies the frequency and duration of
the received tones before passing the corresponding
code to the output bus.

Filter Section

Separation of the low-group and high group tones is
achieved by applying the DTMF signal to the inputs
of two sixth-order switched capacitor bandpass
filters, the bandwidths of which correspond to the low
and high group frequencies. The filter section also
incorporates notches at 350 and 440 Hz for
exceptional dial tone rejection (see Figure 3). Each
filter output is followed by a single order switched
capacitor filter section which smooths the signals
prior to limiting. Limiting is performed by high-gain
comparators which are provided with hysteresis to
prevent detection of unwanted low-level signals. The
outputs of the comparators provide full rail logic
swings at the frequencies of the incoming DTMF
signals.

Decoder Section

Following the filter section is a decoder employing
digital counting techniques to determine the
frequencies of the incoming tones and to verify that
they correspond to standard DTMF frequencies. A
complex averaging algorithm protects against tone
simulation by extraneous signals such as voice while

Figure 4 - Basic Steering Circuit

providing tolerance to small frequency deviations
and variations. This averaging algorithm has been
developed to ensure an optimum combination of
immunity to talk-off and tolerance to the presence of
interfering frequencies (third tones) and noise. When
the detector recognizes the presence of two valid
tones (this is referred to as the "signal condition" in
some industry specifications) the "Early Steering"
(ESt) output will go to an active state. Any
subsequent loss of signal condition will cause ESt to
assume an inactive state (see "Steering Circuit").

Steering Circuit

Before registration of a decoded tone pair, the
receiver checks for a valid signal duration (referred
to as character recognition condition). This check is
performed by an external RC time constant driven by
ESt. A logic high on ESt causes v

(see Figure 4) to

rise as the capacitor discharges. Provided signal

St/GT

ESt

StD

MT8870D/

MT8870D-1

GTA

=(RC)In(V

TSt

)

GTP

=(RC)In[V

/(V

-V

TSt

)]

Figure 3 - Filter Response

AAA

AAAA

AAA

ATTENUATION

(dB)

A B

1kHz

PRECISE
DIAL TONES

X=350 Hz
Y=440 Hz

DTMF TONES

A=697 Hz
B=770 Hz
C=852 Hz
D=941 Hz
E=1209 Hz
F=1336 Hz
G=1477 Hz
H=1633 Hz

FREQUENCY (Hz)

MT8870D/MT8870D-1

ISO

-CMOS

4-14

condition is maintained (ESt remains high) for the
validation period (t

GTP

), v

reaches the threshold

TSt

) of the

steering logic to register the tone pair,

latching its corresponding 4-bit code (see Table 1)
into the output latch. At this point the GT output is
activated and drives v

to V

. GT continues to drive

high as long as ESt remains high. Finally, after a
short delay to allow the output latch to settle, the
delayed steering output flag (StD) goes high,
signalling that a received tone pair has been
registered. The contents of the output latch are made
available on the 4-bit output bus by raising the three
state control input (TOE) to a logic high. The
steering circuit works in reverse to validate the
interdigit pause between signals. Thus, as well as
rejecting signals too short to be considered valid, the
receiver will tolerate signal interruptions (dropout)
too short to be considered a valid pause. This facility,
together with the capability of selecting the steering
time constants externally, allows the designer to
tailor performance to meet a wide variety of system
requirements.

Guard Time Adjustment

In many situations not requiring selection of tone
duration and interdigital pause, the simple steering
circuit shown in Figure 4 is applicable. Component
values are chosen according to the formula:

REC

GTP

GTA

The value of t

is a device parameter (see Figure

11) and t

REC

is the minimum signal duration to be

recognized by the receiver. A value for C of 0.1 µF is

Figure 5 - Guard Time Adjustment

St/GT

ESt

a) decreasing t

GTP

; (t

GTP

GTA

)

GTP

=(R

)In[V

/(V

-V

TSt

)]

GTA

=(R

)In(V

TSt

)

=(R

)/(R

)

St/GT

ESt

GTP

=(R

)In[V

/(V

-V

TSt

)]

GTA

=(R

)In(V

TSt

)

=(R

)/(R

)

b) decreasing t

GTA

; (t

GTP

GTA

)

Table 1. Functional Decode Table

L=LOGIC LOW, H=LOGIC HIGH, Z=HIGH IMPEDANCE
X = DON`T CARE

recommended for most applications, leaving R to be
selected by the designer.

Different steering arrangements may be used to
select independently the guard times for tone
present (t

GTP

) and tone absent (t

GTA

). This may be

necessary to meet system specifications which place
both accept and reject limits on both tone duration
and interdigital pause. Guard time adjustment also
allows the designer to tailor system parameters
such as talk off and noise immunity. Increasing t

REC

improves talk-off performance since it reduces the
probability that tones simulated by speech will
maintain signal condition long enough to be
registered. Alternatively, a relatively short t

REC

with

a long t

would be appropriate for extremely noisy

environments where fast acquisition time and
immunity to tone drop-outs are required. Design
information for guard time adjustment is shown in
Figure 5.

Digit

TOE

INH

ESt

ANY

undetected, the output code
will remain the same as the
previous detected code

ISO

-CMOS

MT8870D/MT8870D-1

4-15

Power-down and Inhibit Mode

A logic high applied to pin 6 (PWDN) will power down
the device to minimize the power consumption in a
standby mode. It stops the oscillator and the
functions of the filters.

Inhibit mode is enabled by a logic high input to the
pin 5 (INH). It inhibits the detection of tones
representing characters A, B, C, and D. The output
code will remain the same as the previous detected
code (see Table 1).

Differential Input Configuration

The input arrangement of the MT8870D/MT8870D-1
provides a differential-input operational amplifier as
well as a bias source (V

Ref

) which is used to bias the

inputs at mid-rail. Provision is made for connection of
a feedback resistor to the op-amp output (GS) for
adjustment of gain. In a single-ended configuration,
the input pins are connected as shown in Figure 10
with the op-amp connected for unity gain and V

Ref

biasing the input at

. Figure 6 shows the

differential configuration, which permits the
adjustment of gain with the feedback resistor R

Crystal Oscillator

The internal clock circuit is completed with the
addition of an external 3.579545 MHz crystal and is
normally connected as shown in Figure 10 (Single-
Ended Input Configuration). However, it is possible
to configure several MT8870D/MT8870D-1 devices
employing only a single oscillator crystal. The
oscillator output of the first device in the chain is
coupled through a 30 pF capacitor to the oscillator
input (OSC1) of the next device. Subsequent devices
are connected in a similar fashion. Refer to Figure 7
for details. The problems associated with
unbalanced loading are not a concern with the
arrangement shown, i.e., precision balancing
capacitors are not required.

Figure 6 - Differential Input Configuration

Figure 7 - Oscillator Connection

Table 2. Recommended Resonator Specifications

Note: Qm=quality factor of RLC model, i.e., 1/2

R1C1.

Parameter

Unit

Resonator

Ohms

10.752

.432

4.984

37.915

896.37

±0.2%

IN+

IN-

Ref

MT8870D/
MT8870D-1

Differential Input Amplifier
C

=10 nF

=100 k

=60k

, R

=37.5 k

All resistors are

1% tolerance.

All capacitors are

5% tolerance.

VOLTAGE GAIN (A

diff)=

INPUT IMPEDANCE

INDIFF

) = 2

OSC1

OSC2

OSC1

X-tal

To OSC1 of next

MT8870D/MT8870D-1

C=30 pF
X-tal=3.579545 MHz

Ð­Ð»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: MT8870DN

ÐÐ»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: MT8870DN