3-51
Features
32 bidirectional CMOS "T" switches in an 8
4
non-blocking array
Break-before-make switching configuration
Fast setup & hold times for switch programming
3dB bandwidth of 200MHz
Low feedthrough and crosstalk, better than -80dB
at 5MHz
Very low differential gain and phase errors
12Vpp bipolar signal capability
On-state resistance 75
(max) for V
DD
=+5V,
V
EE
=-7V
Switch control through 2-stage latches
Orthogonal Xi and Yi pin connections for
optimized PCB layout
Latch readback capability for monitoring
Applications
High-end video routing and switching
Medical instrumentation
Automatic test equipment (ATE)
Multi-media communication
Description
The MT88V32 is a digitally programmable (TTL levels)
8
4 crosspoint switch that is designed to control wide-
band analog (video) signal.
Each of the 32 nodes of the switching matrix has a T-
switch, see Fig.1. This grounds the nodes of all open
connections, which greatly reduces feedthrough
noise. In order to reduce crosstalk, individual analog
signal lines are isolated by interleaving them with
ground lines.
The two stage programmable latch system allows
the state of all switching nodes to be updated
simultaneously. The next state of the switch is written
into the first stage of the latches through individual
write cycles. These changes will not affect the
current state of the switch. The STROBE2
control
input is used to load the state of all first stage latches
to the second stage latches, which updates the
complete matrix. Therefore, all 32 switching nodes
are updated simultaneously.
The MT88V32 supports separate analog (V
EE
) and
digital (V
DD
) voltage references. This allows the user
to select an optimum analog signal bias point.
Ordering Information
MT88V32AP
44 Pin PLCC
-40 to 85C
Figure 1 - Functional Block Diagram
Y0-Y7
VDD
VSS
X0
GND
MR
STROBE2
STROBE1
AX0-AX1
8x4
"T" Switch Array
VEE
2nd Stage Latches
1st Stage Latches
Address Decode
AY0-AY2
I/O
Logic
Control
X1
X2
X3
R/W
DATA
CS
Yi
Xi
GND
T-Switch Configuration
ISSUE 1
August 1993
MT88V32
8 x 4 High Performance Video Switch Array
Preliminary Information
MT88V32
Preliminary Information
3-52
Figure 2 - Pin Connections
Pin Description
Pin #*
Name
Description
1, 3, 4, 6,
8, 10,
12, 14,
16, 18,
20, 39,
41, 43
GND
Analog Ground. Connect to system ground for crosstalk noise isolation. Pins 3 and 39
are not bonded internally.
2, 44,
42, 40
X0, X1,
X2, X3
Analog Lines (input/output).
5, 7,
9, 11,
13, 15,
17, 19
Y0, Y1,
Y2, Y3
Y4, Y5,
Y6, Y7
Analog Lines (input/output).
21
V
EE
Negative Analog Power Supply.
22
IC
Internal Connection.
23
V
DD
Positive Power Supply.
24
V
SS
Digital Ground Reference.
25, 26
AX1,AX0
X0-X3 I/O Address Select (inputs).
27, 30,31
AY2-AY0
Y0-Y7 I/O Address Select (inputs).
28, 29
NC
No Connection.
32
DATA
DATA (input/output). When input, a logic high will close the selected switch and a logic
low will open the selected switch. When output, a logic high indicates a closed switch
and a logic low indicates an opened switch.
33
CS
Chip Select (input). Active low.
34
R/W
READ/WRITE Control (input). When high the DATA pin is an output (for reading from
second stage latch); when low the DATA pin is an input (for writing to first stage latch).
35
STROBE1 STROBE 1 (input). Modifies memory content of first stage latch as determined by the
addess and data lines, but does not change the switch array configuration of entire
switch array. Active low.
36
STROBE2 STROBE 2 (input). Transfers memory content of first stage latch to the second stage
latch and hence, changes the configuration of entire switch array. Active low.
37
MR
MASTER RESET (input). Used to reset the first and second stage latches. Active low.
38
NC
No Connection.
Y1
GND
Y2
GND
Y3
GND
Y4
GND
Y5
GND
Y6
GND
Y7
GND
VE
E
IC
*
VS
S
AX
1
AX
0
AY
2
NC
VDD
1
6 5 4 3 2
44 43 42 41 40
7
8
9
10
11
12
13
14
15
16
39
38
37
36
35
34
33
32
31
30
23
18 19 20 21 22
24 25 26 27 28
17
29
GND
NC
MR
STROBE2
STROBE1
R/W
CS
DATA
AY0
AY1
NC
X3
GND
X2
GND
X1
GND
X0
GND
GND
Y0
GND
* Connects toV
EE
Preliminary Information
MT88V32
3-53
Functional Description
The state of the MT88V32 8 X 4 switching matrix is
updated through a simple parallel processor
interface. This interface provides access to 32 two
stage latches, which determines the state (open/
close) of each switching array node. Each latch (or
node) is addressed by the AX0-AX1 and AY0-AY2
inputs as per Table 2, and the DATA input will
determine if the connection is to be made (DATA=1)
or opened (DATA=0).
The second stage of the two stage latches controls
the current state of each switching node. The value
held in the first stage is the input to the second
stage. This allows the device to be programmed in
two ways. That is, individual switching nodes may be
updated one at a time, or all nodes may be updated
at once.
To update one node at a time the STROBE2 input
should be held low. This makes the second stage
latches transparent and the matrix immediately
reflects the state of the first stage latches. A write
cycle example follows:
1)
STROBE2
is low,
2)
CS
and R/W are low, MR
is high,
3)
AX0-AX1 and AY0-AY2 as per Table 2,
4)
DATA input high to close or low to open, and
5)
STROBE1
toggled from high-to-low-to-high.
These steps (one write cycle) may be repeated for
each switch state change. This can also be
accomplished by holding STROBE1
low and toggling
STROBE2. See Figure 14 for timing.
To update all nodes simultaneously all switch state
changes must be written into the first stage latches.
This is accomplished by holding STROBE2
high and
performing steps 2) through 5) above for each
switching node that is to be changed. Writing to the
first stage latches only will not affect the switching
state of the matrix. When the changes have been
made all the switches of the matrix may be updated
simultaneously by toggling the STROBE2
input from
high-to-low-to high.
When STROBE2
is used to update the state of the
MT88V32 all switch "breaks" are completed before
any switch "makes" occur. There is approximately
10ns delay between "breaks" and "makes".
Both the first and second stage latches will be
cleared when the master reset (MR) is taken from
high-to-low. This will open all the switch nodes. The
operation of MR
is independent of
CS, AX0-AX1,
AY0-AY2 and R/W.
The status of each switching array node (second
stage latch) can be read through the bidirectional
DATA pin. A read cycle example follows:
1) CS
is low, R/W and MR
are high,
2) AX0-AX1 and AY0-AY2 as per Table 2, and
3) DATA output high for closed or low for open.
Note:
x = don't care, 0 = logic "0" state, 1 = logic "1" state
A logic 1 on DATA input closes a connection.
A logic 0 on DATA input opens a connection.
MR
R/W
CS
DATA
STROBE1
STROBE2
DATA
1
1
0
0
1
0
0
1
1
0
1
0
1
1
No Change to 1st stage latch.
1st stage latch is loaded with data.
1
1
0
0
0
0
0
1
0
1
0
0
1
1
1st stage latch is transparent.
Selected latch is cleared and set again (i.e.,
output follows input).
1
1
0
0
0
x
1
x
0
1
1
1
1
0
1st stage latch output is frozen.
Output of 1st stage latch is transferred to
output of 2nd stage latches.
1
1
0
0
x
0
x
x
1
0
0
1
0
2nd stage latch output is frozen.
Both 1st stage and 2nd stage latches are
transparent.
1
0
1
1
0
1
0
1
x
1
x
1
DATA becomes an output and reflects the
contents of the 2nd stage latch addressed
by AX0-AX1 and AY0-AY2.
All crosspoints opened (data in 1st and 2nd
stage latches are cleared).
T
able 1 - Truth Tables
MT88V32
Preliminary Information
3-54
It should be noted that the STROBE1
function is
disabled during a read cycle. See Fig. 15 for timing.
The MT88V32 can operate from a dual rail power
supply (V
DD
and V
EE
) or a single rail power supply
(V
SS
=V
EE
=0V) as per the recommended operating
conditions. For minimum on-state resistance the
supply voltages should be V
DD
=5.0 V
DC
, V
SS
=0 V
DC
and V
EE
=-7 V
DC
. The analog input signal should be
biased at -2.0 V
DC
to achieve minimum differential
phase and gain error (see AC Electrical
Characteristics - Crosspoint Performance).
Applications
Figure 3 illustrates examples of how to connect the
signal lines of the MT88V32 to various interfaces.
Input buffers allow the incoming signals to be scaled
and biased to the optimum operating range of the
MT88V32 (i.e., differential phase error, differential
gain error and R
ON
). Buffers will also allow a more
precise input impedance to be implemented. For low
grade video applications, signal lines may be
connected directly, as long as the ultimate source
and terminating impedances are matched.
Output buffers may be used to provide signal gain
and impedance matching for external connections.
Additionally, they may be used to isolate parasitic
device capacitance in multiple stage switching
applications where high frequency roll-off is critical.
Crosstalk, as well as differential phase and gain error
can be minimized by designing a low source
impedance (e.g., 10 ohms), and a high terminating
impedance (e.g., 10k) at each stage. If successive
switching stages are not buffered, then a resistor to
ground (R) should be present between the switches.
Selection of R is based on the following compromise:
1) as R is decreased to approach the source and
terminating resistance values signal loss will
increase and crosstalk will decrease, and
2) as R increases signal loss will decrease and
crosstalk will increase.
It is recommended that the power supply rails of the
MT88V32 be decoupled with 0.1F ceramic Z5U and
10F dipped tantalum capacitors. These capacitors
should be as close to the device as possible. The
signal pins of the MT88V32 are interleaved with
analog ground lines. This allows the circuit designer
to run ground tracks on both sides of each signal line
to improve crosstalk immunity.
The 8x4 bidirectional CMOS T-switch configuration is
a modular switching element in a convenient
package size. The inherent flexibility of this device
permits the designer to build large switching
matrices, see analog switch application notes.
A
5
A
4
A
3
A
2
A
1
A
0
D
0
Function
0
0
0
1
0
1
0
1
0
1
0
1
1/0
1/0
Y0 to X0
Y7 to X3
1
X
X
X
X
0
X
MR
1
X
X
X
X
1
X
STB2
Table 3 - Address Decoding for the Processor
Interfaces
Note: x = undefined, 1/0 -1 = make, 0 = break
AX1
AX0
AY2
AY1
AY0
Switch Connections
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
Y0 to X0
Y1 to X0
Y2 to X0
Y3 to X0
Y4 to X0
Y5 to X0
Y6 to X0
Y7 to X0
0
0
1
1
0
1
0
1
0
1
Y0 to X1
Y7 to X1
1
1
0
0
0
1
0
1
0
1
Y0 to X2
Y7 to X2
1
1
1
1
0
1
0
1
0
1
Y0 to X3
Y7 to X3
T
able 2 - Address Decode Truth Table
Preliminary Information
MT88V32
3-55
Figures 4, 5 and 6 show methods of interfacing the
MT88V32 to Motorola and Intel microcontrollers. The
address decoding for these configurations is in Table
3.
Video Signal Terminology
1) Component Video - separate red (R), blue (B),
green (G), and synchronization signals.
2) Composite Video - contains luminance
(brightness), chrominance (colour), and
synchronization signal components in a single
waveform.
3) Synchronization signal - horizontal sync pulses
are negative going excursions of the composite
video signal that occur every 63.5 sec. Their
function is to align the horizontal sweep.
Vertical synchronization is achieved during the
vertical blanking interval, which is about 1200
sec or 20 horizontal scan intervals long. It
consists of a number of vertical synchronization
and equalization pulses.
4) Luminance - is the black to white brightness
component of a composite video signal. Its range
is from reference white (maximum amplitude) to
reference black (minimum amplitude).
5) Chrominance - rides on the luminance signal and
determines the hue (phase) and brightness
(amplitude) of the colour component of a
composite video signal.
6) Colour burst - is about 9 (minimum 8) cycles of a
3.578545 MHz reference signal, which is
transmitted with every horizontal sweep of the
composite video signal. A phase comparison
Figure 3 - High Frequency Switching Applications
75
75
75
Wideband
Input Buffers
X0
X1
X2
X3
Y0
Y1
Y2
Y3
Y4
Y5
Y6
Y7
MT88V32
Control Interface
10k
10k
10k
Wideband
Output Buffers
75
75
75
10k
10k
10k
Wideband
Output Buffers
R
To next
switching
stage
MT88V32
Preliminary Information
3-56
Figure 4 - Motorola Non-multiplexed Processor Interface
Figure 5 - Motorola Multiplexed Processor Interface
MC6800/
6802/6809
2
VMA
A
5
-A
15
A
0
-A
4
D0
R/W
MT88V32
STB1
STB2
MR
CS
AY0-AY1
AX0-AX2
DATA
R/W
5
11
A0
A5 + A0 + VMA
A5 + A0 + VMA
A5 +VMA
Notes: for the MC6802
2 will be E.
for the MC6809
2 will be E and VMA will be the OR'ed product of Q and E.
MC6801/
6803/68HC11
(PC) AD
0
-AD
4
(PC) AD
5
-AD
7
(PB) A
8
-A
15
AS
E
R/W
MT88V32
DATA
AY0
AY1
AY2
AX0
AX1
CS
STB2
MR
STB1
R/W
3
74HCT574
D
1
Q
1
D
2
Q
2
D
3
Q
3
D
4
Q
4
D
5
Q
5
D
6
Q
6
D
7
Q
7
D
8
Q
8
CLK OC
A5 + A0
A5
A5 + A0
5
AD0
8
AD0
Preliminary Information
MT88V32
3-57
Figure 6 - Intel Processor Interface
Figure 7 - Typical On-state Resistance (R
ON
) vs. DC Bias (Vdc) @ V
DD
=+5V, V
EE
=-7V
8031/8051
8085
(P0) AD
0
-AD
4
(P0) AD
5
-AD
7
(P2) A
8
-A
15
ALE
WR
RD
MT88V32
DATA
AY0
AY1
AY2
AX0
AX1
CS
STB2
MR
STB1
R/W
3
74HCT574
D
1
Q
1
D
2
Q
2
D
3
Q
3
D
4
Q
4
D
5
Q
5
D
6
Q
6
D
7
Q
7
D
8
Q
8
CLK OC
A5 + A0
A5
A5 + A0
5
AD0
8
AD0
MT88V32
Preliminary Information
3-58
Figure 8 - Single Channel Feedthrough (all crosspoints open)
Figure 9 - Single Channel Crosstalk (one crosspoint closed)
Figure 10 - All Channel Crosstalk (all crosspoints closed)
Preliminary Information
MT88V32
3-59
between this reference signal and the
chrominance signal determines colour hue.
7) Differential Phase Error - (measured in degrees)
is a phase change in the chrominance signal due
to a change in luminance amplitude.
8) Differential Gain Error - (measured in
percentage) is a change in amplitude of the
chrominance signal due to a change in
luminance amplitude.
Figure 11 - 3dB Frequency Response
MT88V32
Preliminary Information
3-60
Figure 12 - Typical Differential Phase vs. Ramp Voltage
Figure 13 - Typical Differential Gain vs. Ramp Voltage
Preliminary Information
MT88V32
3-61
* Exceeding these values may cause permanent damage. Functional operation under these conditions is not implied.
DC Electrical Characteristics are over recommended temperature range & recommended power supply voltages.
Typical figures are at 25C and are for design aid only; not guaranteed and not subject to production testing.
DC Electrical Characteristics are over recommended temperature range & recommended power supply voltages.
Typical figures are at 25C and are for design aid only; not guaranteed and not subject to production testing.
Absolute Maximum Ratings
*
- Voltages are with respect to V
SS
unless otherwise stated.
Parameter
Symbol
Min
Max
Units
1
Supply Voltage
V
DD
to V
SS
V
DD
to V
EE
V
SS
to V
EE
GND to V
SS
-0.3
-0.3
-0.3
V
EE
-0.3
15
15
15
V
DD
+0.3
V
V
V
V
2
Analog Input Voltage
V
IN
V
EE
-0.3
V
DD
+0.3
V
3
Digital Input Voltage
V
IND
V
SS
-0.3
V
DD
+0.3
V
4
Continuous Current (any analog I/O terminal)
15
mA
5
Storage Temperature
-65
+150
C
6
Operating Temperature
-40
+85
C
7
Package Power Dissipation
600
mW
Recommended Operating Conditions
- Voltages are with respect to 0V unless otherwise stated.
Characteristics
Sym
Min
Typ
Max
Units
Test Conditions
1
Supply Voltage
V
DD
-V
EE
V
EE
-V
SS
V
DD
V
EE
4.5
-8.5
4.5
-8.5
12
5.0
-7.0
13.2
0
13.2
0
V
V
V
V
V
EE
=V
SS
=0V
V
DD
=4.5V, V
SS
=0V
2
Analog Input Voltage
V
IN
V
EE
V
DD
V
3
Digital Input Voltage
V
IND
V
SS
V
DD
V
4
Analog Ground
GND
V
EE
0
V
DD
V
DC Electrical Characteristics
-
Analog Switch Characteristics
Voltages are with respect to V
DD
=+5V, V
EE
=-7V, V
SS
=0V unless otherwise stated.
25C
85C
Test
Characteristics
Sym
Typ
Max
Max
Units
Conditions
1
On-state Resistance
V
EE
=-7V
V
EE
=-5V
V
EE
=0V
R
ON
50
60
140
65
75
185
75
85
220
V
IN
=V
DC
=(V
DD
+V
EE
)/2
IV
Xi
-V
Yj
I = 0.4V
See Figure 7.
2
Difference in on-state resistance
between switches
R
ON
6
10
10
IV
Xi
-V
Yj
I = 0.4V
V
IN
=V
DC
=(V
DD
+V
EE
)/2
3
Off-state leakage current
I
OFF
10
200
nA
V
IN
=V
DD
or V
EE
4
On-state leakage current
I
ON
10
200
nA
V
IN
=V
DD
or V
EE
DC Electrical Characteristics
-
Power Supplies
- Voltages are with respect to V
DD
=+5V, V
EE
=-7V, V
SS
=0V,
MR = 0.8V unless otherwise stated.
Characteristics
Sym
Min
Typ
Max
Units
Test Conditions
1
Positive Supply Current
I
DD
1
0.4
5
100
1.5
15
A
mA
mA
V
IND
=V
DD
or V
SS
V
IND
=2.4V
V
DD
=12V, V
SS
=V
EE
=0V,
V
IND
=3.4V
2
Negative Supply Current
I
EE
1
1
1
100
100
100
A
A
A
V
IND
=V
DD
or V
SS
V
IND
=2.4V
V
DD
=12V, V
SS
=V
EE
=0V,
V
IND
=3.4V
MT88V32
Preliminary Information
3-62
DC Electrical Characteristics are over recommended temperature range and recommended power supply voltages.
Typical figures are at 25C and are for design aid only; not guaranteed and not subject to production testing.
Algebraic convention is adopted in this data sheet where the most negative value is a minimum and the most positive value is a
maximum.
Timing is over recommended temperature range.
Typical figures are at 25C and are for design aid only; not guaranteed and not subject to production testing.
Notes:
Q
Valid for V
EE
=-7V, V
DD
=+5V and V
DC
=-2.0V. Error will increase slightly if input is biased differently.
Input test signal: 700mV ramp biased @ -2.0Vdc with a superimposed video signal of 285Vrms @ 3.58 MHz.
R
Guaranteed by design and characterization and not subject to production testing.
DC Electrical Characteristics
- Digital Input/Output
Voltages are with respect to V
DD
=5V, V
EE
=-7V, V
SS
=0V, unless otherwise stated.
Characteristics
Sym
Min
Typ
Max
Units
Test Conditions
1
Input logic "1" level
V
IH
2
V
V
IH
3.3
V
V
EE
=V
SS
=0, V
DD
=12V
2
Input logic "0" level
V
IL
0.8
V
V
IL
0.8
V
V
EE
=V
SS
=0, V
DD
=12V
3
Input leakage (digital pins)
I
LEAK
1
10
A
V
IND
=V
DD
or V
SS
4
Data output high voltage
V
OH
2.4
V
DD
V
I
OH
=7mA@V
OH
=2.4V
5
Data output high current
I
OH
7
20
mA
source V
OH
=2.4V
6
Data output low voltage
V
OL
V
SS
0.4
V
I
OL
=2mA@V
OL
=0.4V
7
Data output low current
I
OL
2
5
mA
sink V
OL
=0.4V
8
Data high impedance leakage
I
OZ
1
10
A
V
O
=0 to V
DD
AC Electrical Characteristics
- Crosspoint Performance
- Voltages are with respect to V
DD
=+5V, V
DC
=0,
V
EE
=-7V, V
SS
=0V, unlesss otherwise stated. Also applicable for V
EE
=V
SS
=0, V
DD
=+12V, V
DC
=(V
DD
+V
EE
)/2.
Characteristics
Sym
Min
Typ
Max
Units
Test Conditions
1
On-state Xi capacitance
Q
C
Xi (on)
56
pF
1 Xi to 1 Yi
2
On-state Yi capacitance
R
C
Yi (on)
56
pF
1 Yi to 1 Xi
3
Off-state Xi capacitance
R
C
Xi (off)
30
pF
4
Off-state Yi capacitance
R
C
Yi (off)
15
pF
5
Break-before-Make interval
t
open
10
ns
6
Single channel feedthrough
(all crosspoints open)
(see Fig. 8)
FDT
-80
-62
dB
dB
R
S
= R
L
=75
V
IN
=0.6Vpp @ 5MHz
V
IN
=0.6Vpp @ 15MHz
7
Single channel feedthrough
(all crosspoints closed)
(See Fig. 9)
X
talk
(sc)
-85
-68
dB
dB
R
IN
= 10
,
R
L
= 10k
V
IN
=0.6Vpp @ 5MHz
V
IN
=0.6Vpp @ 15MHz
X
talk
(sc)
-70
-50
dB
dB
R
IN
= 75
,
R
L
= 10k
V
IN
=0.6Vpp @ 5MHz
V
IN
=0.6Vpp @ 15MHz
8
All channel crosstalk
(all crosspoints closed)
(See Fig. 10)
X
talk
(ac)
-55
dB
R
IN
= 10
,
R
L
= 10k
V
IN
=0.6Vpp @ 5MHz
9
Frequency Response
(see Fig.11)
f
3dB
200
MHz
R
S
= R
L
=50
10
Differential Phase Error
DP
0.05
o
See Note
Q
, R
S
= 50
,
R
L
= 75
11
Differential Gain Error
DG
0.11
%
See Note
Q
, R
S
= 50
,
R
L
= 75
Preliminary Information
MT88V32
3-63
Timing is over recommended temperature range with V
IH
=5V, V
IL
=0V, V
OH
=2.4V, V
OL
=0.8V, R
L
=3k
(DATA) and R
L
=1k
(analog).
Typical figures are at 25C and are for design aid only; not guaranteed and not subject to production testing.
AC Electrical Characteristics
- Timing Characteristics
- Voltages are with respect to V
DD
=+5V, V
EE
=-7V,
V
SS
=0V, R
L
=1k
, C
L
=50pF unlesss otherwise stated. Also applicable for V
EE
=V
SS
=0, V
DD
=+12V.
Characteristics
Sym
Min
Typ
Max
Units
Test Conditions
1
DATA to STROBE1 setup
t
ds1
20
ns
2
DATA to STROBE1 hold
t
dh1
10
ns
3
CS to STROBE1 setup
t
css1
20
ns
4
CS to STROBE1 hold
t
csh1
20
ns
5
ADDRESS to STROBE1 setup
t
ass1
20
ns
6
ADDRESS to STROBE1 hold
t
ash1
20
ns
7
STROBE1 pulse width
t
spw1
75
ns
8
STROBE2 pulse width
t
spw2
75
ns
9
R/W to STROBE1 setup
t
rwss1
20
ns
10
R/W to STROBE1 hold
t
rwsh1
10
ns
11
RESET pulse width
t
rpw
75
ns
12
CS to High Z
t
rpw
10
ns
13
CS to DATA output valid
t
csov
200
ns
14
STROBE2 to STROBE1 setup
t
s2s1
0
ns
15
STROBE1 to STROBE2 setup
t
s1s2
0
ns
16
MR to switch OPEN delay
50% MR to10% Output
t
rst
300
ns
17
R/W to DATA output valid
t
rwov
150
ns
18
Address to DATA output valid
t
aov
200
ns
19
R/W to High Z
t
rwz
10
ns
20
Address to High Z
t
az
10
ns
21
STROBE2 to switch status delay
50% strobe to10% output change
tstrobe2(on)
tstrobe2(off)
t
son
t
soff
100
100
300
300
ns
ns
MT88V32
Preliminary Information
3-64
Figure 14 - Write Cycle Timing Diagram
Figure 15 - Read Cycle Timing Diagram
t
css1
t
csh1
t
rpw
t
spw1
t
ass1
t
dh1
t
son
t
rst
t
ds1
CS
STROBE1
ADDRESS
DATA
SWITCH
on
off
MR
t
ash1
t
s1s2
t
s2s1
R/W
t
rwss1
t
rwsh1
t
spw2
STROBE2
STATUS
t
soff
t
rwz
t
aov
t
az
CS
ADDRESS
DATA
High Z
R/W
t
csov
t
rwov
High Z
Data Valid
t
csz
Note: STROBE1 is disabled when R/W is at logic "1".
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