8-3

Features

Supports up to 10 independent conferences for
up to 32 PCM Voice Channels

ST-BUS compatible 2.048 Mb/s PCM Serial
Interface (also supports 1.536 Mb/s and 1.544
Mb/s data rates)

Per channel digital gain control (0/-3/-6 dB)

Parallel microprocessor port for device control

Programmable noise suppression

External Tone Input

Pin selectable A/

-Law format

Low power CMOS technology

Available in 24 Pin PDIP and SOIC packages

Applications

Digital PBX / KTS

Conference bridges

Digital C.O. switches

Description

The MT8924 is designed to provide conference call
capability in digital switching systems. It allows up to
10 independent conferences to be set for up to 32
PCM voice channels.

-Law companded data from the PCM input port is

converted to linear format, processed by a dedicated
arithmetic unit, re-converted to companded format
and then sent to the PCM output port.The PCM
output signal contains all the information of each
channel connected in conference except its own.

Programmable attenuation and noise suppression
are provided for channels connected in conference
or transparent mode. Additionally, an input for an
external tone is featured that can be used as a signal
to indicate to connected parties that they are on a
conference call.

Figure 1 - Functional Block Diagram

ISSUE 1

April 1994

Parallel-to-Serial

Conversion

Linear

/A-Law

Linear

Attenuation/Noise Suppression

Channel RAM

Serial-to-Parallel

DSTo

DSTi

Cki

F0i

Cko

D0-D7

RESET

C/D

Overflow

and

Adder

Timebase

PCM Tone

Control

Ordering Information

MT8924AE

24 Pin Plastic DIP

MT8924AS

24 Pin SOIC

C to +70

Generator

PCM Mode

Control

MT8924

PCM Conference Circuit (PCC)

Preliminary Information

MT8924

Preliminary Information

8-4

Figure 2 - Pin Connections

Pin Description

Pin #

Name

Description

Tone Duration (Input). When TD is High, a PCM-coded tone is sent out to all channels of
the enabled conferences instead of PCM data. TD is latched by frame pulse F0i so that all
channels have the same tone during the same frame number. When TD is Low, normal
operation is enabled.

Tone Frequency (Input). This input is connected to an external squarewave generator. TF
is strobed by frame pulse F0i so that all channels have the same tone frequency during the
same number of frames. The PCM-coded tone level corresponds to 1/10th of the full scale
value, and is activated when TD is High.

RESET

Master RESET (Input). This input is used for system initialization after power up, or when
the companding law format has been changed. The RESET pin is strobed by the rising edge
of clock Cki. Complete circuit initialization takes two frame periods. Initialization disables the
output drivers of the microprocessor interface and DSTo.

Overflow Signalling (Output). When OS is Low, a conference is in the overflow condition.
This signal is delayed by half of a timeslot relative to the beginning of the output channel of
the conference in overflow (see Figure 9).

DST

ST-BUS Serial Output. This pin is the output for the PCM signal. It is enabled upon
channel selection, otherwise it is placed in a high impedance state. Maximum bit rate is
2.048 Mb/s.

6-13

D7 to D0 Data Bus I/O Port. These are bidirectional data pins over which data and instructions are

transferred to and from the microprocessor (where D0 is the least significant bit). The bus is
in a high impedance state when RESET is Low and/or CS is High.

Positive Supply Voltage. Nominally 5 volts.

C/D

Control/Data Select (Input). The signal on this input defines whether the information on the
data bus should be interpreted as opcode or data. During a write operation a Low signal
defines the bus content as data, while a High signal defines it as opcode. During a read
operation this input differentiates overflow status between the first eight channels for C/D
being LOW, and the last two channels for C/D being HIGH (see Instruction 4). This input also
allows status monitoring (see Instruction 6) during a read operation.

Chip Select (Input). This active low input selects the device for microprocessor read/write
operations. When CS is Low, data and instructions can be transferred to or from the
microprocessor, and when CS is High, the data bus is in a high impedance state.

Read (Input). This active low input is for the read signal on the microprocessor interface.
The data bus is updated on the falling edge of RD.

Write Input. This active low input is for the write signal on the microprocessor interface. The
data bus is strobed on the rising edge of WR.

1
2
3
4
5
6
7
8
9

10
11
12

24
23
22
21
20
19
18
17

RESET

D7
D6

D4
D3
D2
D1

VSS
A/

DSTi
Cko
Cki
F0i
WR
RD
CS
C/D
VDD
D0

DSTo

Preliminary Information

MT8924

8-5

F0i

Frame Pulse (Input). This is an 8 kHz active low input used for frame synchronization of the
PCM bit stream. The first falling edge of Cki following the falling edge of frame pulse F0i
determines the start of a new frame and must correspond to the first bit of the first channel.
When PCM frames of 1544 kbit/s are used, the rising edge of F0i must correspond to the
Extra (193rd) bit.

Cki

Clock (Input). This signal is the timing reference used for all internal operations. The PCM
bit cell boundaries lie on the alternate falling edges of this clock. The maximum allowable
clock frequency is 4096 kHz.

Cko

Clock (Output). This pin provides the master clock for a digital crosspoint switch (e.g.,
MT898x series, or the MT9080, MT9085 combination). Normally the signal on this pin is
identical to Cki. When Extra bit operating mode is selected (see Instruction 5), the first two
cycles of the master clock are suppressed (see Figure 10). This feature allows the MT8924
to operate in 1544 kbit/s systems.

DST

ST-BUS Serial Input. This pin accepts the serial PCM input stream at a maximum allowable
bit rate of 2048 kbit/s. In normal operation the first bit of the first channel is defined by the
rising edge of Cki following the falling edge of frame pulse F0i. When Extra bit operating
mode is selected, the first bit of the first channel defines the extra bit.

- Law Select Input. When A/

is High, A-Law is selected, and when A/

is Low,

-Law is

selected. The companding law selection must be done before initializing the device using
the RESET pin.

Negative Power Supply Voltage. Nominally 0 Volts.

Pin Description (continued)

Pin #

Name

Description

Functional Description

The MT8924 is a device designed to provide
conferencing in a digital switching system in any
combination for up to all 32 channels of a 2048 kbit/s
ST-BUS stream (see Figure 3).

The information of channel N, frame M is first
converted to Linear PCM and then added to the
signal from other conferencees during the first half of

Microcontroller

MT8980/81/82
Digital Switch

MT8924

Circuit (PCC)

PCM Conference

STi0

STix-1

STix

STo0

STox-1

STox

Figure 3 -Typical Conference Connection

.
.
.
.

channel N+1, frame M and subtracted during the
second half of channel N-1, frame M+1. After Linear-
to-PCM conversion the subtraction result goes to the
parallel-to-serial converter, and appears at the
output on the N+1 channel, M+1 frame with respect
to the corresponding sending party information (see
Figure 4).

To a microprocessor the MT8924 appears as a
memory mapped peripheral device that can be
controlled by a set of six instructions. These
commands can be used to establish or cancel
conferences between the PCM channels and also to
transmit control messages on specific operating
modes. The microprocessor can initiate and receive
status messages or check conference connections
that are currently in operation.

Figure 4 - Input/Output Channel Relationship

MT8924

DSTi

DSTo

Input Channels

Output Channels

Input

Output

Frame M

Frame M+1

Information

B+C A+C A+B

N+2 N+3

N+1

N+2

N+1

MT8924

Preliminary Information

8-6

Table 1 - PCM Noise Suppression Threshold Levels

Noise

Threshold

PCM Byte

+ve input

-ve input

B7 - B0

A-Law

1/4096

1000 0000

0000 0000

9/4096

1000 0100

0000 0100

16/4096

1000 1000

0000 1000

32/4096

1000 1111

0000 1111

-Law

1/8159

1111 1111

0111 1111

9/8159

1111 1011

0111 1011

16/8159

1111 0111

0111 0111

32/8159

1111 0000

0111 0000

Table 2 - PCM Byte Format

B7 (sign bit) is the MSB and B0 is the LSB
F1-F0 corresponds to the D5-D4 bits of the control byte of Operating Mode Instruction 5

Comments

+ Full Scale

No Inversion

+ 0 Level

- 0 Level

- Full Scale

+ Full Scale

Even Bit Inversion

+ 0 Level

- 0 Level

- Full Scale

+ Full Scale

Odd Bit Inversion

+ 0 Level

- 0 Level

- Full Scale

+ Full Scale

Bit Inversion

+ 0 Level

- 0 Level

- Full Scale

Overflow Detection / Input Channel Attenuation

If the sum of the channels involved in one
conference exceeds the full scale value of the
accumulator, an overflow condition is generated
which can be monitored specifically by reading the
status of the overflow register. If an overflow
condition occurs, then each channel in a conference
can be independently attenuated if desired.

Alternatively, a conference in the overflow condition
can be detected using the OS signal in conjunction
with frame pulse F0i. OS will be low during the
second half of a general output channel slot time N,
if channel N belongs to a conference in overflow (see
Figure 11). This information can be used to control
input channel attenuation through software control.

Preliminary Information

MT8924

8-7

Noise Suppression

When noise suppression is enabled for a specific
input channel then the PCM bytes for this channel,
when below the selected threshold level, are
converted to PCM bytes corresponding to the
minimum PCM code level before being added to the
conference sum.

The four threshold levels available correspond to the
first, fifth, ninth and sixteenth step of the first
segment. These are 1/4096, 9/4096, 16/4096, and
32/4096 with respect to full scale A-Law, and 1/8159,
9/8159, 16/8159, and 32/8159 with respect to full
scale

-Law (see Table 1).

PCM Format Selection

PCM digital code assignment is register
programmable and achieved through the use of
Instruction 5 (see Table 2). The available formats are
CCITT G.711 A-Law or

-Law, with true-sign

Alternate Digit Inversion or true-sign/Inverted
Magnitude coding.

Output clock Cko provides a reference time base for
a digital time/space crosspoint switch. Normally this
signal is identical to the master clock input Cki.
When operating with the extra bit selection, through
Instruction 5, Cko is low for two clock periods, which
allows operation of the MT8924 with the 1.544 MHz
PCM frame format (see Figure 10).

Transparent Mode

The MT8924 can operate in transparent mode. In
this case the PCM input (DSTi) is passed unmodified
through the MT8924 to the output (DSTo) with a
delay of one frame and one channel. This feature
allows attenuation of specific channels that are not
connected to a conference.

Tone Insertion

The MT8924 provides for tone insertion into PCM
output channels by using the two input pins TD and
TF. An externally generated square wave tone
applied to the TF input will generate a level
corresponding to 1/10 of the full scale accumulator
value when TD is High. Only channels connected in
a conference with the insertion tone bit (IT) active
will have the PCM coded tone at their output (see
Instruction 1).

Testing and Diagnostic Feature

For testing and diagnostic purposes, a status
instruction has been provided that indicates
conference location and attenuation level for each
channel requested. This data appears on the
databus upon status request.

Programmable Control

Instruction 1 : Conference Mode Connection

This function connects a PCM channel to a
conference. The control information from the
microprocessor consists of two data bytes and one
control byte. The first byte contains the conference
number (bits D0-D3) and the Start bit S (D4). When
S is High, the accumulator registers connected to a
conference are initialized. S set to High is only
required in Instruction 1 of the first channel
connected to a new conference, otherwise S is set
LOW to bring other channels into the conference.
The second byte contains the number of the
channel to be connected (D0-D4), and the Insert
Tone Enable bit IT (D5). When IT and TD are both
High all the channels belonging to that conference
are enabled using the insert tone function. The
third byte contains a four bit opcode (D0-D3) plus
information about the attenuation level and noise
suppression to be applied to the specific channel.

Instruction 2 : Transparent Mode Connection

This function sets up a PCM channel for
transparent mode operation. The control
information from the microprocessor consists of
one data byte and one control byte.

The first byte contains the channel number, and
the second byte contains a four bit opcode (D0-D3)
and information about attenuation and noise
suppression levels to be applied to the specific
channel. PCM data on this channel is not added to
any conference, but is transferred to the PCM
output after a full frame pulse plus one channel
delay. It is not affected by the tone control pins (TF,
TD).

Instruction 3 : Disconnection

This function disconnects a PCM channel from a
conference. The control information from the
microprocessor consists of one data byte and one

MT8924

Preliminary Information

8-8

control byte. The data byte contains the number of

the channel to be disconnected. The second byte
contains the opcode (D0-D3). One frame pulse
must pass between disconnection and
reconnection of the same channel.

Instruction 4 : Overflow Status Monitoring

This function extracts overflow status information
on all existing conferences and transfers it to the
microprocessor data bus. This instruction consists
of two control bytes which are differentiated by the
C/D control signal. C/D set Low reads the status of
the first eight conferences, while C/D set High
reads the status of the remaining two conferences.
A conference is in overflow when the
corresponding status bit is high.

Instruction 5 : PCM Mode Select

This function is used to set the PCM format. The
control byte from the microprocessor consists of
one data byte. It contains the Extra Bit E (D6), the
Format Bits F1-F0 (D5, D4), and the opcode (D0-
D3). The E bit must be high when the PCM frame
contains an extra bit (i.e. 1.544 Mb/s). Normally E
is Low. Bits F1-F0 are used to select the PCM byte
format, according to Table 2. After RESET the
default values correspond to F1 at Low and F0 at
High if A-Law is selected, and F1 at High and F0 at
High if

-Law is selected. All channels must be

disconnected when the PCM mode select
instruction is sent. They must remain disconnected
for at least two frame pulses after the instruction is
sent. It is recommended that this instruction be
used immediately following a system reset (see
RESET pin description).

Instruction 6 : Status Monitoring

This function is a read operation which consists of
a data byte, a control byte, and a status byte. It
extracts information for test and diagnostic
purposes and transfers it to the microprocessor
bus. The first byte contains the channel number,
while the second byte contains the opcode (D0-
D3). The third byte contains the status information
about the operating mode of the channel (D4-D7);
the attenuation level (D2-D3); and the noise
suppression level (D0-D1).

Preliminary Information

MT8924

8-9

Conference Start Bit

T1-T0:

Channel Noise Suppression

P3-P0:

Conference Number (1-10)

T1/T0

A-Law

-Law

IT:

Insertion Tone Function Enable (IT=1)

no noise suppression

C4-C0:

Channel Number (0-31)

9/4096

9/8159

A1-A0:

Channel Attenuation

16/4096

16/8159

00 = -0dB

32/4096

32/8159

01 = -3dB
10 = -6dB

T1-T0: see noise suppression description given for Instruction 1

CF10 - CF1 : Conference is in overflow when bit is HIGH

Note : as long as RD remains LOW, the overflow status of the conference selected by C/D can be monitored in real time

Instruction 1 : Channel Connection in Conference Mode

Control Signals

Data Bus

Comments

C/D

Conference Number

PCM Channel Number and
Insertion Tone control

Opcode, Attenuation, and
Noise Suppression control

Instruction 2 : Channel Connection in Transparent Mode

Control Signals

Data Bus

Comments

C/D

PCM Channel Number

Opcode and Attenuation

Instruction 3 : Channel Disconnection

Control Signals

Data Bus

Comments

C/D

PCM Channel Number

Opcode

Instruction 4: Overflow Status Monitoring

Control Signals

Data Bus

Comments

C/D

Conferences 1 to 8

Conferences 9 to 10

MT8924

Preliminary Information

8-10

Extra bit insertion (active when E=1)

F1 - F0:

PCM byte format selection (see Table 1)
00 = no bit inverted
01 = even bit (B0, B2, B4, B6) inverted
10 = odd bit (B1, B3, B5) inverted
11 = all bits (B0, B1, B2, B3, B4, B5, B6) inverted

P3 - P0:

channel mode operation information

A1 - A0:

see channel attenuation description

0000 = no connection

for Instruction 1

1111 = transparent mode

T1 - T0:

see noise suppression description

1010 - 0001 = conference mode

for Instruction 1

P3 - P0 provides conference number

Note:

Instruction 6 enables the data bus to read the status until reset by C/D=0, WR=1, and CS=0

Instruction 5 : PCM Operating Mode Selection

Control Signals

Data Bus

Comments

C/D

see Table 1

Instruction 6 : Status Monitoring

Control Signals

Data Bus

Comments

C/D

Preliminary Information

MT8924

8-11

Exceeding these figures may cause permanent damage. Functional operation under these conditions is not guaranteed.

Typical figures are at 25

C and are for design aid only; not guaranteed and not subject to production testing.

All DC characterisitics are valid 250

s after V

and C4i have been applied.

Absolute Maximum Ratings*

Parameter

Symbol

Min

Max

Units

Supply Voltage

- V

- 0.3

Voltage on any I/O pin

I/O

- 0.3

+ 0.3

Current on any I/O pin

I/O

Storage Temperature

- 65

+ 150

Power Dissipation (plastic package)

500

Recommended Operating Conditions

Characteristics

Sym

Min

Typ*

Max

Units

Test Conditions

Supply Voltage

4.75

5.25

Ambient Operating Temp. Range

+70

Input Voltage High

2.4

for 400mv noise
margin

Input Voltage Low

0.8

DC Characteristics: Clocked operation

=0 to 70

C; V

=5V±5%)

Characteristics

Sym

Min

Typ

Max

Units

Test Conditions

Input Low Level

0.8

Pins 1-3, 6-13, 15-20, 22-23

Input High Level

2.0

Pins 1-3, 6-13, 15-20, 22-23

Output Low Level

0.4

Pins 4, 6-13; I

=4 mA

Output High Level

2.4

Pins 4, 6-13; I

=4 mA

Output Low Level

0.4

Pins 5, 21; I

=8 mA

Input Leakage Current

Pins 1-3, 6-13, 15-20, 22-23;
V

=0 to V

Data Bus Leakage Current

±10

Pins 6-13; V

=0 to V

;

CS=V

Supply Current

Pin 14; Cki=4.096 MHz

AC Electrical Characteristics - Capacitances

Characteristics

Sym

Min

Typ

Max

Units

Test Conditions

Input Capacitance

frequency=1MHz; T

to 70

unused pins tied to V

;

=5V±5%

I/O Capacitance (Bidirectional)

I/O

Output Capacitance

MT8924

Preliminary Information

8-12

* All AC characteristics are valid 250

s after V

and the clock have been applied. C

is the max. capacitive load and R

is the test pull up

resistor. With Extra Bit Insert operating mode these times are 80ns longer.

** With Extra Bit Insert operating mode this time becomes 3t

Figure 5 - Clock Timing

AC Electrical Characteristics - Clocked Timing*

=0 to 70

C; V

=5V±5%)

Characteristics

Sym

Min

Typ

Max

Units

Test Conditions

Clock period

230

Clock low level width

WLCK

100

Clock high level width

WHCK

100

Clock rise time

RCK

Clock fall time

FCK

Sync. low setup time

SLSY

Sync. low level hold time

HLSY

Sync. high setup time

SHSY

Sync. high width

WHSY

OS propagation delay from rising
edge of Clock

PDOS

100

=50pF

Cko propagation delay to Clock
edges

PDEC

=50pF

TD setup time

STD

TD hold time

HTD

TD setup time

STF

TD hold time

HTD

WHCK

WLCK

SLSY

RCK

FCK

HLSY

SHSY

PDEC

PDOS

STF

HTF

STD

WHSY

Cki

F0i

Cko

Preliminary Information

MT8924

8-13

*All AC characteristics are valid 250

s after V

and the clock have been applied. C

is the max. capacitive load and R

s the test pull up

resistor.

**With Extra Bit Insert operating mode these times are 80ns longer.

Figure 6 - PCM Timing

* All AC characteristics are valid 250

s after V

and the clock have been applied. C

is the max. capacitive load and R

is the test pull up

resistor.

Figure 7 - Reset Timing

AC Electrical Characteristics - PCM Timing*

=0 to 70

C; V

=5V±5%)

Characteristics

Sym

Min

Typ

Max

Units

Test Conditions

Input PCM setup time

SPCM

Input PCM hold time

HPCM

Output PCM propagation delay

125

=150pF, R

=1K

in 2.048MHz mode **

AC Electrical Characteristics - RESET Timing*

=0 to 70

C; V

=5V±5%)

Characteristics

Sym

Min

Typ

Max

Units

Test Conditions

RESET low setup time

SLRES

100

RESET low hold time

HLRES

RESET high setup time

SHRES

RESET high level width

WHRES

AAAA

AAA

AAAA

Cki

F0i

DSTo

DSTi

MSB

SPCM

HPCM

AAAA

MSB

Cki

RESET

SLRES

HLRES

SHRES

WHRES

MT8924

Preliminary Information

8-14

Figure 8 - Write Timing Characteristics

AC Electrical Characteristics - Write Timing

=0 to 70

C; V

=5V±5%)

Characteristics

Sym

Min

Typ

Max

Units

Test Conditions

Write Pulse low width

WLWR

150

Write Pulse high width

WHWR

200

Repetition Interval between active Write
Pulses

REPWR

500

Read high setup time to active Write
Pulse

SHRD

Read high hold time from active Write
Pulse

HHRD

Write Pulse rise time

RWR

Write Pulse fall time

FWR

CS low setup time to WR falling edge

SLCSWR

Active case

CS low hold time from WR falling edge

HLCSWR

Active case

CS high setup time to WR rising edge

SHCSWR

CS high hold time from WR rising edge

HHCSWR

C/D setup time to Write Pulse end

SC/DWR

130

C/D hold time from Write Pulse end

HCDWR

Input setup time to Write Pulse end

SDWR

130

Input hold time from Bus Write Pulse
end

HDWR

C/D

WLWR

SHRD

WHWR

HHRD

RWR

REPWR

FWR

SHCSWR

SLCSWR

HLCSWR

HHCSWR

SCDWR

HCDWR

SDWR

HDWR

DIN

Preliminary Information

MT8924

8-15

Figure 9 - Read Timing Characteristics

AC Electrical Characteristics - Read Timing

=0 to 70

C; V

=5V±5%)

Characteristics

Sym

Min

Typ

Max

Units

Test Conditions

Read Pulse low width

WLRD

180

Read Pulse high width

WHRD

200

Repetition Interval between active Read
Pulses

REPRD

500

Write high setup time to active Read
Pulse

SHWR

Write high hold time from active Read
Pulse

HHWR

Read Pulse rise time

RRD

Read Pulse fall time

FRD

Low setup time to RD falling edge

SLCSRD

Active case

Low hold time from RD falling edge

HLCSRD

Active case

High setup time to RD falling edge

SHCSRD

Active case

High hold time from RD rising edge

HHCSRD

Active case

C/D setup time to RD Pulse start

SCDRD

Hold time from Read Pulse end

HCDRD

Propagation delay from falling edge of
Read Pulse

PDD

120

Read; C

=200pF

Propagation delay from rising edge of
Read Pulse to high impedance state

Write; C

=200pF

C/D

WLRD

SHWR

WHRD

HHWR

RRD

REPRD

FRD

SHCSRD

SLCSRD

HLCSRD

HHCSRD

SCDRD

HCDRD

DOUT

PDD

MT8924

Preliminary Information

8-16

Figure 10 - CKo Timing with Extra Bit Insertion Mode

Figure 11 - OS Timing with Output PCM Channel belonging to a Conference in Overflow

AAAA

Cki

F0i

PDEC

Extra Bit

Bit 0 Channel 0

Bit 1 Channel 0

Cko

Cki

Channel N

Channel N+1

Channel N-1

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