Features

Provides T1 clock at 1.544 MHz locked to an 8
kHz reference clock (frame pulse)

Provides CEPT clock at 2.048 MHz and ST-BUS
clock and timing signals locked to an internal or
external 8 kHz reference clock

Typical inherent output jitter (unfiltered)= 0.07
UI peak-to-peak

Typical jitter attenuation at: 10 Hz=23 dB,100
Hz=43 dB, 5 to 40 kHz

64 dB

Jitter-free "FREE-RUN" mode

Uncommitted two-input NAND gate

Low power CMOS technology

Applications

Synchronization and timing control for T1
and CEPT digital trunk transmission links

ST- BUS clock and frame pulse source

Description

The MT8941B is a dual digital phase-locked loop
providing the timing and synchronization signals for
the T1 or CEPT transmission links and the ST-BUS.
The first PLL provides the T1 clock (1.544 MHz)
synchronized to the input frame pulse at 8 kHz. The
timing signals for the CEPT transmission link and the
ST-BUS are provided by the second PLL locked to an
internal or an external 8 kHz frame pulse signal.

The MT8941B offers improved jitter performance
over the MT8940. The two devices also have some
functional differences, which are listed in the section
on "Differences between MT8941B and MT8940".

Ordering Information

MT8941BE

24 Pin Plastic DIP (600 mil)

MT8941BP

28 Pin PLCC

-40

C to +85

Figure 1 - Functional Block Diagram

F0i

C12i

MS0

MS1

MS2

MS3

C8Kb

C16i

RST

CVb

ENCV

F0b

C4b

C4o

ENC4o

C2o

ENC2o

2:1 MUX

Variable

Clock

Control

Mode

Selection

Logic

DPLL #2

Input

Selector

Clock

Generator

Frame Pulse

Control

4.096 MHz

Clock

Control

2.048 MHz

Clock

Control

DPLL #1

DS5186

ISSUE 1

June 1999

MT8941B

Advanced T1/CEPT Digital Trunk PLL

CMOS ST-BUS

FAMILY

MT8941B

CMOS

Figure 2 - Pin Connections

Pin Description

Pin #

Name

Description

DIP

PLCC

Variable clock enable (TTL compatible input) - This input directly controls the three states
of CV (pin 22) under all modes of operation. When HIGH, enables CV and when LOW, puts
it in high impedance condition. It also controls the three states of CVb signal (pin 21) if MS1
is LOW. When ENCV is HIGH, the pin CVb is an output and when LOW, it is in high
impedance state. However, if MS1 is HIGH, CVb is always an input.

MS0

Mode select `0' input (TTL compatible) - This input in conjunction with MS1 (pin 4) selects
the major mode of operation for both DPLLs. (Refer to Tables 1 and 2.)

C12i

12.352 MHz Clock input (TTL compatible) - Master clock input for DPLL #1.

MS1

Mode select-1 input (TTL compatible) - This input in conjunction with MS0 (pin 2) selects
the major mode of operation for both DPLLs. (Refer to Tables 1 and 2.)

F0i

Frame pulse input (TTL compatible) - This is the frame pulse input at 8 kHz. DPLL #1
locks to the falling edge of this input to generate T1 (1.544 MHz) clock.

F0b

Frame pulse Bidirectional (TTL compatible input and Totem-pole output) - Depending
on the minor mode selected for DPLL #2, it provides the 8 kHz frame pulse output or acts as
an input to an external frame pulse.

MS2

Mode select-2 input (TTL compatible) - This input in conjunction with MS3 (pin 17) selects
the minor mode of operation for DPLL #2. (Refer to Table 3.)

C16i

16.384 MHz Clock input (TTL compatible) - Master clock input for DPLL #2.

C4o

Enable 4.096 MHz clock (TTL compatible input) - This active high input enables C4o (pin
11) output. When LOW, the output C4o is in high impedance condition.

C8Kb

Clock 8 kHz Bidirectional (TTL compatible input and Totem-pole output) - This is the 8
kHz input signal on the falling edge of which the DPLL #2 locks during its NORMAL mode.
When DPLL #2 is in SINGLE CLOCK mode, this pin outputs an 8 kHz internal signal
provided by DPLL #1 which is also connected internally to DPLL #2.

C4o

Clock 4.096 MHz (Three state output) - This is the inverse of the signal appearing on pin
13 (C4b) at 4.096 MHz and has a rising edge in the frame pulse (F0b) window. The high
impedance state of this output is controlled by ENC4o (pin 9).

Ground (0 Volt)

28 PIN PLCC

24 PIN PDIP

1
2
3
4
5
6
7
8
9

10
11
12

24
23
22
21
20
19
18
17

ENVC

MS0
C12i
MS1

F0i

F0b

MS2
C16i

ENC4o

C8Kb

C4o

VSS

VDD
RST
CV
CVb

Yo
Bi
Ai
MS3
ENC2o
C2o
C2o
C4b

5
6
7
8
9
10
11

25
24
23
22
21
20
19

NC
CVb
Yo
Bi
Ai
MS3
ENC2o

MS1

F0i

F0b

MS2
C16i

ENC4o

C2o

C12i

MS0

ENCV

VDD

RST

C8Kb

C4o

VSS

C4b

C2o

CMOS

MT8941B

C4b

Clock 4.096 MHz- Bidirectional (TTL compatible input and Totem-pole output) - When
the mode select bit MS3 (pin 17) is HIGH, it provides the 4.096 MHz clock output with the
falling edge in the frame pulse (F0b) window. When pin 17 is LOW, C4b is an input to an
external clock at 4.096 MHz.

C2o

Clock 2.048 MHz (Three state output) - This is the divide by two output of C4b (pin 13) and
has a falling edge in the frame pulse (F0b) window. The high impedance state of this output
is controlled by EN

C2o

(pin 16).

C2o

Clock 2.048 MHz (Three state output) - This is the divide by two output of C4b (pin 13) and
has a rising edge in the frame pulse (F0b) window. The high impedance state of this output is
controlled by EN

C2o

(pin 16).

C2o

Enable 2.048 MHz clock (TTL compatible input) - This active high input enables both C2o
and C2o outputs (pins 14 and 15). When LOW, these outputs are in high impedance
condition.

MS3

Mode select 3 input (TTL compatible) - This input in conjunction with MS2 (pin 7) selects
the minor mode of operation for DPLL #2. (Refer to Table 3.)

18,

21,

Ai, Bi

Inputs A and B (TTL compatible) -These are the two inputs of the uncommitted NAND
gate

Output Y (Totem pole output) - Output of the uncommitted NAND gate.

CVb

Variable clock Bidirectional (TTL compatible input and Totem-pole output) - When
acting as an output (MS1-LOW) during the NORMAL mode of DPLL #1, this pin provides the
1.544 MHz clock locked to the input frame pulse F0i (pin 5). When MS1 is HIGH, it is an
input to an external clock at 1.544 MHz or 2.048 MHz to provide the internal signal at 8 kHz
to DPLL #2.

Variable clock (Three state output) - This is the inverse output of the signal appearing on
pin 21, the high impedance state of which is controlled by EN

(pin 1).

RST

Reset (Schmitt trigger input) - This input (active LOW) puts the MT8941B in its reset state.
To guarantee proper operation, the device must be reset after power-up. The time constant
for a power-up reset circuit (see Figures 9-13) must be a minimum of five times the rise time
of the power supply. In normal operation, the RST pin must be held low for a minimum of
60nsec to reset the device.

(+5V) Power supply.

4,
5,

18,
25

No Connection.

Pin Description (continued)

Pin #

Name

Description

DIP

PLCC

MT8941B

CMOS

Functional Description

The MT8941B is a dual digital phase-locked loop
providing the timing and synchronization signals to
the interface circuits for T1 and CEPT (30+2)
Primary Multiplex Digital Transmission links. As
shown in the functional block diagram (see Figure 1),
the MT8941B has two digital phase-locked loops
(DPLLs), associated output controls and the mode
selection logic circuits. The two DPLLs, although
similar in principle, operate independently to provide
T1 (1.544 MHz) and CEPT (2.048 MHz) transmission
clocks and ST-BUS timing signals.

The principle of operation behind the two DPLLs is
shown in Figure 3. A master clock is divided down to
8 kHz where it is compared with the 8 kHz input, and
depending on the output of the phase comparison,
the master clock frequency is corrected.

Figure 3 - DPLL Principle

The MT8941B achieves the frequency correction in
both directions by using three methods; speed-up,
slow-down and no-correction.

As shown in Figure 4, the falling edge of the 8 kHz
input signal (C8Kb for DPLL #2 or F0i for DPLL # 1)
is used to sample the internally generated 8 kHz
clock and the correction signal (CS) once in every
frame (125

s). If the sampled CS is "1", then the

DPLL makes a speed-up or slow-down correction
depending upon the sampled value of the internal 8
kHz signal. A sampled "0" or "1" causes the
frequency correction circuit to respectively stretch or
shrink the master clock by half a period at one
instant in the frame. If the sampled CS is "0", then
the DPLL makes no correction on the master clock
input. Note that since the internal 8 kHz signal and
the CS signal are derived from the master clock, a
correction will cause both clocks to stretch or shrink
simultaneously by an amount equal to half the period
of the master clock.

Once in synchronization, the falling edge of the
reference signal (C8Kb or F0i) will be aligned with
either the falling or the rising edge of CS. It is aligned
with the rising edge of CS when the reference signal
is slower than the internal 8 kHz signal. On the other
hand, the falling edge of the

Figure 4 - Phase Comparison

reference signal will be aligned with the falling edge
of CS if the reference signal is faster than the
internal 8 kHz signal.

Input-to-Output Phase Relationship

The no-correction window size is 324 ns for DPLL #1
and 32

s for DPLL #2. It is possible for the relative

phase of the reference signal to swing inside the no-
correction window depending on its jitter and the
relative drift of the master clock. As a result, the
phase relationship between the input signal and the
output clocks (and frame pulse in case of DPLL #2)
may vary up to a maximum of window size. This
situation is illustrated in Figure 4. The maximum
phase variation for DPLL #1 is 324 ns and for DPLL
#2 it is 32

s. However, this phase difference can be

absorbed by the input jitter buffer of Mitel's T1/CEPT
devices.

The no-correction window acts as a filter for low
frequency jitter and wander since the DPLL does not
track the reference signal inside it. The size of the
no-correction window is less than or equal to the size
of the input jitter buffer on the T1 and CEPT devices
to guarantee that no slip will occur in the received
T1/CEPT frame.

The circuit will remain in synchronization as long as
the input frequency is within the lock-in range of the
DPLLs (refer to the section on "Jitter Performance
and Lock-in Range" for further details). The lock-in
range is wide enough to meet the CCITT line rate
specification (1.544 MHz

32 ppm and 2.048 MHz

50 ppm) for the High Capacity Terrestrial Digital

Service.

The phase sampling is done once in a frame (8 kHz)
for each DPLL. The divisions are set at 8 and 193 for
DPLL #1, which locks to the falling edge of the input

Master clock

(12.352 MHz /

16.384 MHz)

Frequency

Correction

Output

(1.544 MHz /

2.048 MHz)

Input

(8 kHz)

Phase

Comparison

193 /

256

C8Kb (DPLL #2)
or F0i (DPLL #1)

sampling edge

Interna

8 kHz

correction

speed-up

region

slow-down

region

CSF

no-correction

F0b
(DPLL #2)

DPLL #1

DPLL #2:

CSF

= 766

P16

where, T

P12

is the 12.352 MHz master clock oscillator period

for DPLL #1 and T

P16

is the 16.384 MHz master clock period

for DPLL #2.

= 4

P12

0.5

P12

= 512

P16

0.5

P16

CMOS

MT8941B

at 8 kHz to generate T1 (1.544 MHz) clock. For
DPLL #2, the divisions are set at 8 and 256 to
provide the CEPT/ST-BUS clock at 2.048 MHz
synchronized to the falling edge of the input signal (8
kHz). The master clock source is specified to be
12.352 MHz for DPLL #1 and 16.384 MHz for DPLL
#2 over the entire temperature range of operation.

The inputs MS0 to MS3 are used to select the
operating mode of the MT8941B, see Tables 1 to 4.
All the outputs are controlled to the high impedance
condition by their respective enable controls. The
uncommitted NAND gate is available for use in
applications involving Mitel's MT8976/ MH89760 (T1
Interfaces) and MT8979/MH89790 (CEPT
Interfaces).

Modes of Operation

The operation of the MT8941B is categorized into
major modes and minor modes. The major modes
are defined for both DPLLs by the mode select pins
MS0 and MS1. The minor modes are selected by
pins MS2 and MS3 and are applicable only to DPLL
#2. There are no minor modes for DPLL #1.

Major modes of DPLL #1

DPLL #1 can be operated in three major modes as
selected by MS0 and MS1 (Table 1). When MS1 is
LOW, it is in NORMAL mode, which provides a T1
(1.544 MHz) clock signal locked to the falling edge
of the input frame pulse F0i (8 kHz). DPLL #1
requires a master clock input of 12.352 MHz (C12i).
In the second and third major modes (MS1 is HIGH),
DPLL #1 is set to DIVIDE an external 1.544 MHz or
2.048 MHz signal applied at CVb (pin 21). The
division can be set by MS0 to be either 193 (LOW) or
256 (HIGH). In these modes, the 8 kHz output at
C8Kb is connected internally to DPLL #2, which
operates in SINGLE CLOCK mode.

Major modes of DPLL #2

There are four major modes for DPLL #2 selectable
by MS0 and MS1, as shown in Table 2. In all these
modes DPLL #2 provides the CEPT PCM30 timing,
and the ST-BUS clock and framing signals.

In NORMAL mode, DPLL #2 provides the CEPT/ST-
BUS compatible timing signals locked to the falling
edge of the 8 kHz input signal (C8Kb). These
signals are 4.096 MHz (C4o and

C4b) and 2.048

MHz (C2o and C2o) clocks, and the 8 kHz frame
pulse (F0b) derived from the 16.384 MHz master
clock. This mode can be the same as the FREE-
RUN mode if the C8Kb pin is tied to V

or V

Note:

X: indicates don't care

Table 1. Major Modes of DPLL #1

Table 2. Major Modes of DPLL #2

Table 3. Minor Modes of DPLL #2

In FREE-RUN mode, DPLL #2 generates the stand-
alone CEPT and ST-BUS timing and framing signals
with no external inputs except the master clock set at
16.384 MHz. The DPLL makes no correction in this
configuration and provides the timing signals without
any jitter.

Mode of

Operation

Function

NORMAL

Provides the T1 (1.544 MHz) clock
synchronized to the falling edge of
the input frame pulse (F0i).

DIVIDE-1

DPLL #1 divides the CVb input by
193. The divided output is
connected to DPLL #2.

DIVIDE-2

DPLL #1 divides the CVb input by
256. The divided output is
connected to DPLL #2.

Mode of

Operation

Function

NORMAL

Provides CEPT/ST-BUS timing
signals locked to the falling edge of
the 8 kHz input signal at C8Kb.

FREE-RUN

Provides CEPT/ST-BUS timing and
framing signals with no external
inputs, except the master clock.

SINGLE

CLOCK-1

Provides CEPT/ST-BUS timing
signals locked to the falling edge of
the 8 kHz internal signal provided by
DPLL #1.

SINGLE

CLOCK-2

Provides CEPT/ST-BUS timing
signals locked to the falling edge of
the 8 kHz internal signal provided by
DPLL #1.

Functional Description

Provides CEPT/ST-BUS 4.096 MHz and 2.048
MHz clocks and 8kHz frame pulse depending on
the major mode selected.

Provides CEPT/ST-BUS 4.096 MHz & 2.048 MHz
clocks depending on the major mode selected
while F0b acts as an input. However, the input on
F0b has no effect on the operation of DPLL #2
unless it is in FREE-RUN mode.

Overrides the major mode selected and accepts
properly phase related external 4.096 MHz clock
and 8 kHz frame pulse to provide the ST-BUS
compatible clock at 2.048 MHz.

Overrides the major mode selected and accepts a
4.096 MHz external clock to provide the ST-BUS
clock and frame pulse at 2.048 MHz and 8 kHz,
respectively.

MT8941B

CMOS

The operation of DPLL #2 in SINGLE CLOCK-1
mode is identical to SINGLE CLOCK-2 mode,
providing the CEPT and ST-BUS compatible timing
signals synchro-nized to the internal 8 kHz signal
obtained from DPLL#1 in DIVIDE mode. When
SINGLE CLOCK-1 mode is selected for DPLL #2, it
automatically selects the DIVIDE-1 mode for DPLL
#1, and thus, an external 1.544 MHz clock signal
applied at CVb (pin 21) is divided by DPLL #1 to
generate the internal signal at 8 kHz on to which
DPLL #2 locks. Similarly when SINGLE CLOCK-2
mode is selected, DPLL #1 is in DIVIDE-2 mode,
with an external signal of 2.048 MHz providing the
internal 8 kHz signal to DPLL #2. In both these
modes, this internal signal is available on C8Kb (pin

10) and DPLL #2 locks to the falling edge to provide
the CEPT and ST-BUS compatible timing signals.
This is in contrast to the Normal mode where these
timing signals are synchronized with the falling edge
of the 8 kHz signal on C8Kb.

Minor modes of DPLL #2

The minor modes for DPLL #2 depends upon the
status of the mode select bits MS2 and MS3 (pins 7
and 17).

Table 4. Summary of Modes of Operation - DPLL #1 and #2

Mode

M
S

Operating Modes

DPLL #1

DPLL #2

NORMAL MODE:
Provides the T1 (1.544 MHz) clock
synchronized to the falling edge of the input
frame pulse (F0i).

Properly phase related External 4.096 MHz
clock and 8 kHz frame pulse provide the ST-
BUS clock at 2.048 MHz.

NORMAL MODE

NORMAL MODE:
F0b is an input but has no function in this mode.

NORMAL MODE

External 4.096 MHz provides the ST-BUS clock
and Frame Pulse at 2.048 MHz and 8 kHz,
respectively.

NORMAL MODE

NORMAL MODE:
Provides the CEPT/ST-BUS compatible timing
signals locked to the 8 kHz input signal (C8Kb).

DIVIDE-1 MODE

Same as mode `0'.

DIVIDE-1 MODE

SINGLE CLOCK-1 MODE
F0b is an input but has no function in this mode.

DIVIDE-1 MODE

Same as mode 2.

DIVIDE-1 MODE:
Divides the CVb input by 193. The divided
output is connected to DPLL #2.

SINGLE CLOCK-1 MODE:
Provides the CEPT/ST-BUS compatible timing
signals locked to the 8 kHz internal signal
provided by DPLL #1.

NORMAL MODE

Same as mode `0'.

NORMAL MODE

F0b is an input and DPLL #2 locks on to
it only if it is at 16 kHz to provide the ST-BUS
control signals.

NORMAL MODE

Same as mode 2.

NORMAL MODE

FREE-RUN MODE:
Provides the ST-BUS timing signals with no
external inputs except the master clock.

DIVIDE-2 MODE

Same as mode `0'.

DIVIDE-2 MODE

SINGLE CLOCK-2 MODE:
F0b is an input but has no function in this mode.

DIVIDE-2 MODE

Same as mode 2.

DIVIDE-2 MODE:
Divides the CVb input by 256. The divided
output is connected to DPLL#2.

SINGLE CLOCK-2 MODE:
Provides the CEPT/ST-BUS compatible timing
signals locked to the 8 kHz internal signal
provided by DPLL #1.

CMOS

MT8941B

When MS3 is HIGH, DPLL #2 operates in any of the
major modes selected by MS0 and MS1. When MS3
is LOW, it overrides the major mode selected and
DPLL#2 accepts an external clock of 4.096 MHz on
C4b (pin 13) to provide the 2.048 MHz clocks (C2o
and C2o) and the 8 kHz frame pulse (F0b)
compatible with the ST-BUS format. The mode select
bit MS2 controls the direction of the signal on F0b
(pin 6).

When MS2 is LOW, the F0b pin is an 8 kHz frame
pulse input. This input is effective only when MS3 is
also LOW and pin C4b is fed by a 4.096 MHz clock,
which has a proper phase relationship with the
signal on F0b (refer Figure 18). Otherwise, the input
on pin F0b will have no bearing on the operation of
DPLL #2, unless it is in FREE-RUN mode as
selected by MS0 and MS1. In FREE-RUN mode,
the input on F0b is treated the same way as the
C8Kb input is in NORMAL mode. The frequency of
the signal on F0b should be 16 kHz for DPLL #2 to
lock and generate the ST-BUS compatible clocks at
4.096 MHz and 2.048 MHz.

When MS2 is HIGH, the F0b pin provides the frame
pulse output compatible with the ST-BUS format and
locked to the internal or external input signal as
determined by the other mode select pins.

Table 4 summarizes the modes of the two DPLL. It
should be noted that each of the major modes
selected for DPLL #2 can have any of the minor
modes, although some of the combinations are

Table 5. Functions of the Bidirectional Signals

in Each Mode

Notes:

: Input

: Output

: "don't care" input. Connect to V

or V

SS.

functionally similar. The required operation of both
DPLL #1 and DPLL #2 must be considered when
determining MS0-MS3.

The direction and frequency of each of the
bidirectional signals are listed in Table 5 for each of
the given modes in Table 4.

Jitter Performance and Lock-in Range

The output jitter of a DPLL is composed of the
intrinsic jitter, measured when no jitter is present at
the input, and the output jitter resulting from jitter on
the input signal. The spectrum of the intrinsic jitter
for both DPLLs of the MT8941B is shown in Figure 5.
The typical peak-to-peak value for this jitter is
0.07UI. The transfer function, which is the ratio of
the output jitter to the input jitter (both measured at a
particular frequency), is shown in Figure 6 for DPLL
#1 and Figure 7 for DPLL #2. The transfer function is
measured when the peak-to-peak amplitude of the
sinusoidal input jitter conforms to the following:

10 Hz - 100 Hz : 13.6

100 Hz - 10 kHz : 20 dB/decade roll-off
> 10 kHz : 97.2 ns

The ability of a DPLL to phase-lock the input signal
to the reference signal and to remain locked depends
upon its lock-in range. The lock-in range of the DPLL
is specified in terms of the maximum frequency
variation in the 8 kHz reference signal. It is also
directly affected by the oscillator frequency
tolerance. Table 6 lists different values for the lock-in
range and the corresponding oscillator frequency
tolerance for DPLL #1 and DPLL #2. The smaller
the tolerance value, the larger the lock-in range.

The T1 and CEPT standards specify that, for free
running equipment, the output clock tolerance must
be less than or equal to

32ppm and

50ppm

respectively. This requirement restricts the

Table 6. Lock-in Range vs. Oscillator Frequency

Tolerance

* Please refer to the section on "Jitter Performance and Lock-in
Range" for recommended oscillator tolerances for DPLL #1 & #2.

Mode

F0b

(kHz)

C4b

(MHz)

C8Kb

(kHz)

CVb

(MHz)

i:8

i:4.096

i:X

o:1.544

i:X

o:4.096

i:8

o:1.544

o:8

i:4.096

i:X

o:1.544

o:8

o:4.096

i:8

o:1.544

i:8

i:4.096

i:X

i:1.544

i:X

o:4.096

o:8

i:1.544

o:8

i:4.096

i:X

i:1.544

o:8

o:4.096

o:8

i:1.544

i:8

i:4.096

i:X

o:1.544

i:16

o:4.096

i:X

o:1.544

o:8

i:4.096

i:X

o:1.544

o:8

o:4.096

i:X

o:1.544

i:8

i:4.096

i:X

i:2.408

i:X

o:4.096

o:8

i:2.408

o:8

i:4.096

i:X

i:2.408

o:8

o:4.096

o:8

i:2.408

Oscillator Clock*

Tolerance (

ppm)

Lock-in Range (

Hz)

DPLL #1

DPLL #2

2.55

1.91

2.51

1.87

2.43

1.79

2.33

1.69

2.19

1.55

100

1.79

1.15

150

1.39

.75

175

1.19

.55

CMOS

MT8941B

oscillators of DPLL #1 and DPLL #2 to have
maximum tolerances of

32ppm and

50ppm

respectively.

However, if DPLL #1 and DPLL #2 are daisy-chained
as shown in Figures 9 and 10, the output clock
tolerance of DPLL #1 will be equal to that of the
DPLL #2 oscillator when DPLL #2 is free-running. In
this case, the oscillator tolerance of DPLL #1 has no
impact on its output clock tolerance. For this reason,

it is recommended to use a

32 ppm oscillator for

DPLL #2 and a

100 ppm oscillator for DPLL #1.

Differences between MT8941B and
MT8940

The MT8941B and MT8940 are pin and mode
compatible for most applications. However, the user
should take note of the following differences between
the two parts.

Figure 8 - Application Differences between the MT8940 and MT8941B

a) Distributed Timing

MT8940

8 kHz Reference Signal

Line Card 1

Clocks

Line Card n

Clocks

Data Bus

Line Card 1

Line Card n

MT8941B

8 kHz Reference Signal

Clocks

b) Centralized Timing

Data Bus

MT8941B

CMOS

Besides the improved jitter performance, the
MT8941B differs from the MT8940 in three other
areas:

1. Input pins on the MT8941B do not incorporate

internal pull-up or pull-down resistors. In
addition, the output configuration of the
bidirectional C8Kb pin has been converted from
an open drain output to a Totem-pole output.

2. The MT8941B includes a no-correction window

to filter out low frequency jitter and wander as
illustrated in Figure 4. Consequently, there is no
constant phase relationship between reference
signal F0i of DPLL # 1 or C8Kb of DPLL #2 and
the output clocks of DPLL #1 or DPLL #2.
Figure 4 shows the new phase relationship
between C8Kb and the DPLL #2 output clocks.
Figure 8 illustrates an application where the
MT8941B cannot replace the MT8940 and
suggests an alternative solution.

3. The MT8941B must be reset after power-up in

order to guarantee proper operation, which is not
the case for the MT8940.

4. For the MT8941B, DPLL #2 locks to the falling

edge of the C8Kb reference signal. DPLL#2 of
the MT8940 locks on to the rising edge of C8Kb.

5. While the MT8940 is available only in a 24 pin

plastic DIP, the MT8941B has an additional 28
pin PLCC package option.

Applications

The following figures illustrates how the MT8941B
can be used in a minimum component count
approach in providing the timing and synchro-
nization signals for the Mitel T1 or CEPT interfaces,
and the ST-BUS. The hardware selectable modes
and the independent control over each PLL adds
flexibility to the interface circuits. It can be easily
reconfigured to provide the timing and control signals
for both the master and slave ends of the link.

Synchronization and Timing Signals for the T1
Transmission Link

Figures 9 and 10 show examples of how to generate
the timing signals for the master and slave ends of a
T1 link. At the master end of the link (Figure 9),
DPLL #2 is the source of the ST-BUS signals derived
from the crystal clock. The frame pulse output is
looped back to DPLL #1 (in NORMAL mode), which
locks to it to generate the T1 line clock. The timing
relationship between the 1.544 MHz T1 clock and the
2.048 MHz ST-BUS clock meets the requirements of
the MH89760/760B. The crystal clock at 12.352
MHz is used by DPLL #1 to generate the 1.544 MHz
clock, while DPLL #2 (in FREE-RUN mode) uses the
16.384 MHz crystal oscillator to generate the ST-
BUS clocks for system timing. The generated ST-
BUS signals can be used to synchronize the system
and the switching equipment at the master end.

Figure 9 - Synchronization at the Master End of the T1 Transmission Link

Crystal Clock

(16.384 MHz)

Crystal Clock

(12.352 MHz)

MT8941B

MS0

MS1

MS2

MS3

F0i
C12i

C8Kb

C16i

C4o

C2o

CVb

C4b

C2o

F0b

RST

MH89760B

C1.5i

C2i

F0i

DSTi

DSTo

CSTi

CSTo

TxT

TxR

RxT

RxR

MT8980/81

ST-BUS

SWITCH

LINK

(1.544 Mbps)

TRANSMIT

RECEIVE

Mode of Operation for the MT8941B

DPLL #1 - NORMAL (MS0 = X; MS1 = 0)

DPLL #2 - FREE-RUN (MS0=1; MS2=1; MS3=1)

CMOS

MT8941B

Figure 10 - Synchronization at the Slave End of the T1 Transmission Link

Figure 11 - Synchronization at the Master End of the CEPT Digital Transmission Link

Crystal Clock

(16.384 MHz)

Crystal Clock

(12.352 MHz)

MT8941B

MS0

MS1

MS2

MS3

F0i
C12i

C8Kb

C16i

C4o

C2o

CVb

C4b

C2o

F0b

RST

MH89760B

C1.5i

C2i

F0i

DSTi

DSTo

CSTi

CSTo

TxT

TxR

RxT

RxR

MT8980/81

ST-BUS

SWITCH

LINK

(1.544 Mbps)

TRANSMIT

RECEIVE

Mode of Operation for the MT8941B

DPLL #1 - NORMAL ( MS1=0)

DPLL #2 - NORMAL (MS0=0; MS1=0; MS2=1; MS3=1)

E8Ko

Crystal Clock

(16.384 MHz)

MT8941B

MS0

MS1

MS2

MS3

F0i
C12i

C8Kb

C16i

C4o

C2o

C4b

C2o

F0b

RST

TRANSMIT

RECEIVE

MT8980/81

ST-BUS

SWITCH

MH89790B

C2i

F0i

DSTi

DSTo

CSTi0

CSTo

RxT

RxR

Mode of Operation for the MT8941B

DPLL #1 - NOT USED
DPLL #2 - FREE-RUN (MS0=1; MS1=0; MS2=1; MS3=1)

CSTi1

OUTA

OUTB

CEPT

PRIMARY

MULTIPLEX

DIGITAL

LINK

At the slave end of the link (Figure 10) both the
DPLLs are in NORMAL mode, with DPLL #2
providing the ST-BUS timing signals locked to the 8
kHz frame pulse (E8Ko) extracted from the received
signal on the T1 line. The regenerated frame pulse
is looped back to DPLL #1 to provide the T1 line
clock, which is the same as the master end.

The 12.352 MHz and 16.384 MHz crystal clock
sources are necessary for DPLL #1 and #2,
respectively.

Synchronization and Timing Signals for the
CEPT Transmission Link

The MT8941B can be used to provide the timing and
synchronization signals for the MH89790/790B,
Mitel's CEPT (30+2) Digital Trunk Interface Hybrid.
Since the operational frequencies of the ST-BUS and
the CEPT primary multiplex digital trunk are the
same, only DPLL #2 is required.

MT8941B

CMOS

Figure 12 - Synchronization at the Slave End of the CEPT Digital Transmission Link

Crystal Clock

(16.384 MHz)

MT8941B

MS0

MS1

MS2

MS3

F0i
C12i

C8Kb

C16i

C4o

C2o

C4b

C2o

F0b

RST

MH89790B

C2i

F0i

DSTi

DSTo

CSTi0

CSTo

RxT

RxR

CSTi1

OUTA

OUTB

MT8980/81

ST-BUS

SWITCH

TRANSMIT

RECEIVE

Mode of Operation for the MT8941B

DPLL #1 - NOT USED
DPLL #2 - NORMAL (MS0=0; MS1=0; MS2=1; MS3=1)

CEPT

PRIMARY

MULTIPLEX

DIGITAL

LINK

E8Ko

Figures 11 and 12 show how the MT8941B can be
used to synchronize the ST-BUS to the CEPT
transmission link at the master and slave ends.

Generation of ST-BUS Timing Signals

The MT8941B can source the properly formatted ST-
BUS timing and control signals with no external
inputs except the crystal clock. This can be used as
the standard timing source for ST-BUS systems or
any other system with similar clock requirements.

Figure 13 shows two such applications using DPLL
#2. In one case, the MT8941B is in FREE-RUN
mode with an oscillator input of 16.384 MHz. In the
other case, it is in NORMAL mode with the C8Kb
input tied to V

. For these applications, DPLL #2

does not make any corrections and therefore, the
output signals are free from jitter. DPLL #1 is
completely free.

Figure 13 - Generation of the ST-BUS Timing Signals

Crystal Clock

(16.384 MHz)

MT8941B

MS0

MS1

MS2

MS3

F0i
C12i

C8Kb

C16i

C4o

C2o

C4b

RST

C4o

C2o

F0b

ST-BUS

TIMING

SIGNALS

DPLL #1 - NOT USED
DPLL #2 - NORMAL MODE
(MS0=0; MS1=0;
MS2=1; MS3=1)

MT8941B

MS0

MS1

MS2

MS3

F0i
C12i

C8Kb

C16i

C4o

C2o

C4b

RST

C4o

C2o

F0b

DPLL #1 - NOT USED
DPLL #2 - FREE-RUN MODE
(MS0=1; MS1=0;MS2=1;
MS3=1)

Crystal Clock

(16.384 MHz)

ST-BUS

TIMING

SIGNALS

CMOS

MT8941B

* Exceeding these values may cause permanent damage. Functional operation under these conditions is not implied.

Typical figures are at 25

C and are for design aid only: not guaranteed and not subject to production testing.

Typical figures are at 25

C and are for design aid only: not guaranteed and not subject to production testing.

Absolute Maximum Ratings*

- Voltages are with respect to ground (V

) unless otherwise stated.

Parameter

Symbol

Min

Max

Units

Supply Voltage

-0.3

7.0

Voltage on any pin

-0.3

+0.3

Input/Output Diode Current

IK/OK

Output Source or Sink Current

DC Supply or Ground Current

Storage Temperature

-55

125

Package Power Dissipation

Plastic DIP
PLCC

1200

600

mW
mW

Recommended Operating Conditions

- Voltages are with respect to ground (V

) unless otherwise stated.

Characteristics

Sym

Min

Typ

Max

Units

Test Conditions

Supply Voltage

4.5

5.0

5.5

Input HIGH Voltage

2.0

Input LOW Voltage

0.8

Operating Temperature

-40

DC Electrical Characteristics

- Voltages are with respect to ground (V

) unless otherwise stated.

=5.0V

5%; V

=0V; T

=-40 to 85

Characteristics

Sym

Min

Typ

Max

Units

Test Conditions

S
U
P

Supply Current

Under clocked condition, with the
inputs tied to the same supply
rail as the corresponding pull-up
/down resistors.

Input HIGH voltage (For all the
inputs except pin 23)

2.0

Positive-going threshold
voltage (For pin 23)

3.0

4.0

Input LOW voltage (For all the
inputs except pin 23)

0.8

Negative-going threshold
voltage (For pin 23)

1.0

1.5

O
U

Output current HIGH

-4

=2.4 V

Output current LOW

=0.4 V

Leakage current on bidirect-
ional pins and all inputs except
C12i, C16i, RST, MS1, MS0

-100

-30

Leakage current on pins MS1,
MS0

120

Leakage current on all three-
state outputs and C12i, C16i,
RST inputs

-10

+10

I/O

or V

MT8941B

CMOS

Timing is over recommended temperature & power supply voltages.
Typical figures are at 25

C and are for design aid only: not guaranteed and not subject to production testing.

Figure 14 - Timing Information for DPLL #1 in NORMAL Mode

Timing is over recommended temperature & power supply voltages.
Typical figures are at 25

C and are for design aid only: not guaranteed and not subject to production testing.

AC Electrical Characteristics

Voltages are with respect to ground (V

) unless otherwise stated.

(Refer to Figure 14)

Characteristics

Sym

Min

Typ

Max

Units

Test Conditions

L
L

CVb output (1.544 MHz) rise
time

r1.5

85 pF Load

CVb output (1.544 MHz) fall
time

f1.5

85 pF Load

CVb output (1.544 MHz) clock
period

P15

607

648

689

CVb output (1.544 MHz) clock
width (HIGH)

W15H

318

324

CVb output (1.544 MHz) clock
width (LOW)

W15L

277

363

CV delay (HIGH to LOW)

15HL

CV delay (LOW to HIGH)

15LH

-7

AC Electrical Characteristics

Voltages are with respect to ground (V

) unless otherwise stated.

(Refer to Figure 15)

Characteristics

Sym

Min

Typ

Max

Units

Test Conditions

L
L

C8Kb output (8kHz) delay
(HIGH to HIGH)

C8HH

85 pF Load

C8Kb output (8 kHz) delay
(LOW to LOW )

C8LL

85 pF Load

C8Kb output duty cycle

66
50

%
%

In Divide -1 Mode
In Divide - 2 Mode

Inverted clock output delay
(HIGH to LOW )

ICHL

Inverted clock output delay
(LOW to HIGH)

ICLH

CVb

f1.5

15HL

15LH

r1.5

P15

W15H

W15L

MT8941B

CMOS

Timing is over recommended temperature & power supply voltages.
Typical figures are at 25

C and are for design aid only: not guaranteed and not subject to production testing.

AC Electrical Characteristics

-Voltages are with respect to ground (V

) unless otherwise stated.

(Refer to Figure 16)

Characteristics

Sym

Min

Typ

Max

Units

Test Conditions

L
L

C4b output clock period

P4o

213

244

275

85 pF Load

C4b output clock width (HIGH)

W4oH

159

C4b output clock width (LOW)

W4oL

116

122

C4b output clock rise time

rC4

85 pF Load

C4b clock output fall time

fC4

85 pF Load

Frame pulse output delay
(HIGH to LOW) from C4b

FPL

85 pF Load

Frame pulse output delay
(LOW to HIGH) from C4b

FPH

85 pF Load

Frame pulse (F0b) width

WFP

225

245

C4o delay - LOW to HIGH

4oLH

C4o delay - HIGH to LOW

4oHL

C4b to C2o delay (LOW to
HIGH)

42LH

C4b to C2o delay (HIGH to
LOW)

42HL

C2o clock period

P2o

457

488

519

85 pF Load

C2o clock width ( HIGH )

W2oH

207

280

C2o clock width ( LOW )

W2oL

238

244

C2o clock rise time

rC2

85 pF Load

C2o clock fall time

fC2

85 pF Load

C2o delay - LOW to HIGH

2oLH

-5

C2o delay - HIGH to LOW

2oHL

CMOS

MT8941B

Timing is over recommended temperature & power supply voltages.
Typical figures are at 25

C and are for design aid only: not guaranteed and not subject to production testing.

* Please review the section on "Jitter Performance and Lock-in Range".

Figure 17 - Master Clock Inputs

Timing is over recommended temperature & power supply voltages.
Typical figures are at 25

C and are for design aid only: not guaranteed and not subject to production testing.

Figure 18 - External Inputs on C4b and F0b for the DPLL #2

AC Electrical Characteristics

- Voltages are with respect to ground (V

) unless otherwise stated.

(Refer to Figure 14)

Characteristics

Sym

Min

Typ

Max

Units

Test Conditions

C
L
O
C
K
S

Master clocks input rise time

Master clocks input fall time

Master clock period
(12.352MHz)*

P12

80.943

80.958

80.974

For DPLL #1, while operating to
provide the T1 clock signal.

Master clock period
(16.384MHz)*

P16

61.023

61.035

61.046

For DPLL #2, while operating to
provide the CEPT and ST-BUS
timing signals.

Duty Cycle of master clocks

Lock-in Range

DPLL #1

DPLL #2

-2.33
-1.69

+2.33
+1.69

With the Master frequency
tolerance at

32 ppm.

AC Electrical Characteristics

- Voltages are with respect to ground (V

) unless otherwise stated.

(Refer to Figure 18)

Characteristics

Sym

Min

Typ

Max

Units

Test Conditions

F0b input pulse width (LOW)

WFP

244

C4b input clock period

P4o

244

Frame pulse (F0b) setup time

Frame pulse (F0b) hold time

Master clock

inputs

2.4 V
1.5 V
0.4 V

P12

or t

P16

F0b

C4b

WFP

P4o

MT8941B

CMOS

Timing is over recommended temperature & power supply voltages.
Typical figures are at 25

C and are for design aid only: not guaranteed and not subject to production testing.

Figure 19 - Three State Outputs and Enable Timings

Timing is over recommended temperature & power supply voltages.
Typical figures are at 25

C and are for design aid only: not guaranteed and not subject to production testing.

AC Electrical Characteristics

- Voltages are with respect to ground (V

) unless otherwise stated.

(Refer to Figure 19)

Characteristics

Sym

Min

Typ

Max

Units

Test Conditions

Delay from Enable to Output
(HIGH to THREE STATE)

PHZ

85 pF Load

Delay from Enable to Output
(LOW to THREE STATE)

PLZ

85 pF Load

Delay from Enable to Output
(THREE STATE to HIGH)

PZH

85 pF Load

Delay from Enable to Output
(THREE STATE to LOW)

PZL

85 pF Load

AC Electrical Characteristics

- Uncommitted NAND Gate

Voltages are with respect to ground (V

) unless otherwise stated.

Characteristics

Sym

Min

Typ

Max

Units

Test Conditions

Propagation delay (LOW to
HIGH), input Ai or Bi to output

PLH

85 pF Load

Propagation delay (HIGH to
LOW), input Ai or Bi to output

PHL

85 pF Load

Enable
Input

Output
LOW to
OFF

Output
HIGH
to OFF

10%

90%

1.3 V

Outputs

Enabled

Outputs

Enabled

Outputs

Disabled

PLZ

PHZ

PZL

PZH

6 ns

3.0 V

2.7 V
1.3 V
0.3 V

Package Outlines

Plastic J-Lead Chip Carrier - P-Suffix

Dim

20-Pin

28-Pin

44-Pin

68-Pin

84-Pin

Min

Max

Min

Max

Min

Max

Min

Max

Min

Max

0.165

(4.20)

0.180

(4.57)

0.165

(4.20)

0.180

(4.57)

0.165

(4.20)

0.180

(4.57)

0.165

(4.20)

0.200

(5.08)

0.165

(4.20)

0.200

(5.08)

0.090

(2.29)

0.120

(3.04)

0.090

(2.29)

0.120

(3.04)

0.090

(2.29)

0.120

(3.04)

0.090

(2.29)

0.130

(3.30)

0.090

(2.29)

0.130

(3.30)

D/E

0.385

(9.78)

0.395

(10.03)

0.485

(12.32)

0.495

(12.57)

0.685

(17.40)

0.695

(17.65)

0.985

(25.02)

0.995

(25.27)

1.185

(30.10)

1.195

(30.35)

0.350

(8.890)

0.356

(9.042)

0.450

(11.430)

0.456

(11.582)

0.650

(16.510)

0.656

(16.662)

0.950

(24.130)

0.958

(24.333)

1.150

(29.210)

1.158

(29.413)

0.290

(7.37)

0.330

(8.38)

0.390

(9.91)

0.430

(10.92)

0.590

(14.99)

0.630

(16.00)

0.890

(22.61)

0.930

(23.62)

1.090

(27.69)

1.130

(28.70)

0.004

0.026

(0.661)

0.032

(0.812)

0.026

(0.661)

0.032

(0.812)

0.026

(0.661)

0.032

(0.812)

0.026

(0.661)

0.032

(0.812)

0.026

(0.661)

0.032

(0.812)

0.013

(0.331)

0.021

(0.533)

0.013

(0.331)

0.021

(0.533)

0.013

(0.331)

0.021

(0.533)

0.013

(0.331)

0.021

(0.533)

0.013

(0.331)

0.021

(0.533)

0.050 BSC

(1.27 BSC)

0.050 BSC

(1.27 BSC)

0.050 BSC

(1.27 BSC)

0.050 BSC

(1.27 BSC)

0.050 BSC

(1.27 BSC)

0.020

(0.51)

0.020

(0.51)

0.020

(0.51)

0.020

(0.51)

0.020

(0.51)

Notes:
1) Not to scale
2) Dimensions in inches
3) (Dimensions in millimeters)
4) For D & E add for allowable Mold Protrusion 0.010"

e: (lead coplanarity)

General-10

Package Outlines

Plastic Dual-In-Line Packages (PDIP) - E Suffix

NOTE: Controlling dimensions in parenthesis ( ) are in millimeters.

DIM

8-Pin

16-Pin

18-Pin

20-Pin

Plastic

Min

Max

Min

Max

Min

Max

Min

Max

0.210 (5.33)

0.115 (2.92)

0.195 (4.95)

0.115 (2.92)

0.195 (4.95)

0.115 (2.92)

0.195 (4.95)

0.115 (2.92)

0.195 (4.95)

0.014 (0.356)

0.022 (0.558)

0.014 (0.356)

0.022 (0.558)

0.014 (0.356)

0.022 (0.558)

0.014 (0.356)

0.022 (0.558)

0.045 (1.14)

0.070 (1.77)

0.045 (1.14)

0.070 (1.77)

0.045 (1.14)

0.070 (1.77)

0.045 (1.14)

0.070 (1.77)

0.008

(0.203)

0.014 (0.356)

0.008 (0.203)

0.014(0.356)

0.008 (0.203)

0.014 (0.356)

0.008 (0.203)

0.014 (0.356)

0.355 (9.02)

0.400 (10.16)

0.780 (19.81)

0.800 (20.32)

0.880 (22.35)

0.920 (23.37)

0.980 (24.89)

1.060 (26.9)

0.005 (0.13)

0.300 (7.62)

0.325 (8.26)

0.300 (7.62)

0.325 (8.26)

0.300 (7.62)

0.325 (8.26)

0.300 (7.62)

0.325 (8.26)

0.240 (6.10)

0.280 (7.11)

0.240 (6.10)

0.280 (7.11)

0.240 (6.10)

0.280 (7.11)

0.240 (6.10)

0.280 (7.11)

0.100 BSC (2.54)

0.300 BSC (7.62)

0.115 (2.92)

0.150 (3.81)

0.115 (2.92)

0.150 (3.81)

0.115 (2.92)

0.150 (3.81)

0.115 (2.92)

0.150 (3.81)

0.430 (10.92)

0.060 (1.52)

n-2 n-1 n

Notes:
1) Not to scale
2) Dimensions in inches
3) (Dimensions in millimeters)

General-8

Package Outlines

Plastic Dual-In-Line Packages (PDIP) - E Suffix

DIM

22-Pin

24-Pin

28-Pin

40-Pin

Plastic

Min

Max

Min

Max

Min

Max

Min

Max

0.210 (5.33)

0.250 (6.35)

0.125 (3.18)

0.195 (4.95)

0.125 (3.18)

0.195 (4.95)

0.125 (3.18)

0.195 (4.95)

0.125 (3.18)

0.195 (4.95)

0.014 (0.356)

0.022 (0.558)

0.014 (0.356)

0.022 (0.558)

0.014 (0.356)

0.022 (0.558)

0.014 (0.356)

0.022 (0.558)

0.045 (1.15)

0.070 (1.77)

0.030 (0.77)

0.070 (1.77)

0.030 (0.77)

0.070 (1.77)

0.030 (0.77)

0.070 (1.77)

0.008 (0.204)

0.015 (0.381)

0.008 (0.204)

0.015 (0.381)

0.008 (0.204)

0.015 (0.381)

0.008 (0.204)

0.015 (0.381)

1.050 (26.67)

1.120 (28.44)

1.150 (29.3)

1.290 (32.7)

1.380 (35.1)

1.565 (39.7)

1.980 (50.3)

2.095 (53.2)

0.005 (0.13)

0.390 (9.91)

0.430 (10.92)

0.600 (15.24)

0.670 (17.02)

0.600 (15.24)

0.670 (17.02)

0.600 (15.24)

0.670 (17.02)

0.290 (7.37)

.330 (8.38)

0.330 (8.39)

0.380 (9.65)

0.485 (12.32)

0.580 (14.73)

0.485 (12.32)

0.580 (14.73)

0.485 (12.32)

0.580 (14.73)

0.246 (6.25)

0.254 (6.45)

0.100 BSC (2.54)

0.400 BSC (10.16)

0.600 BSC (15.24)

0.300 BSC (7.62)

0.430 (10.92)

0.115 (2.93)

0.160 (4.06)

0.115 (2.93)

0.200 (5.08)

0.115 (2.93)

0.200 (5.08)

0.115 (2.93)

0.200 (5.08)

n-2 n-1 n

Notes:
1) Not to scale
2) Dimensions in inches
3) (Dimensions in millimeters)

Shaded areas for 300 Mil Body Width 24 PDIP only

TECHNICAL DOCUMENTATION - NOT FOR RESALE

World Headquarters - Canada

Tel: +1 (613) 592 2122

Fax: +1 (613) 592 6909

North America

Asia/Pacific

Europe, Middle East,

Tel: +1 (770) 486 0194

Tel: +65 333 6193

and Africa (EMEA)

Fax: +1 (770) 631 8213

Fax: +65 333 6192

Tel: +44 (0) 1793 518528

Fax: +44 (0) 1793 518581

http://www.mitelsemi.com

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liability for errors that may appear in this publication, or for liability otherwise arising from the application or use of any such information, product or service or for any infringement of
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