2-17

Features

Mitel ST-BUS compatible

4-line x 32-channel inputs

4-line x 32-channel outputs

128 ports non-blocking switch

Single power supply (+5 V)

Low power consumption: 30 mW Typ.

Microprocessor-control interface

Three-state serial outputs

Description

This VLSI ISO-CMOS device is designed for
switching PCM-encoded voice or data, under
microprocessor control, in a modern digital
exchange, PBX or Central Office. It provides
simultaneous connections for up to 128 64 kbit/s
channels. Each of the four serial inputs and outputs
consist of 32 64 kbit/s channels multiplexed to form a
2048 kbit/s ST-BUS stream. In addition, the MT8981
provides microprocessor read and write access to
individual ST-BUS channels.

Figure 1 - Functional Block Diagram

AAA

STo0

STo1

STo2

STo3

Serial

Parallel

Converter

Data

Memory

Frame

Counter

Control Register

Control Interface

Output

MUX

Connection

Memory

Parallel

Serial

Converter

CS R/W A5/

DTA D7/

C4i

F0i

ODE

STi0

STi1

STi2

STi3

ISSUE 6

May 1995

MT8981D

Digital Switch

ISO-CMOS ST-BUS

FAMILY

Ordering Information

MT8981DC

40 Pin Ceramic DIP

MT8981DE

40 Pin Plastic DIP

MT8981DP

44 PLCC

MT8981DL

44 Pin QFP

-40°C to +85°C

MT8981D

ISO-CMOS

2-18

Figure 2 - Pin Connections

Pin Description

Pin #

Name

Description

DIP

PLCC

QFP

DTA

Data Acknowledgement (Open Drain Output). This is the data acknowledgement
on the microprocessor interface. This pin is pulled low to signal that the chip has
processed the data. A 909

, 1/4W, resistor is recommended to be used as a pullup.

2-4

3-5

41-

STi0-

STi2

ST-BUS Input 0 to 2 (Inputs). These are the inputs for the 2048 kbit/s ST-BUS input
streams.

STi3

ST-BUS Input 3 (Input). These are the inputs for the 2048 kbit/s ST-BUS input
streams.

6-9

8-11

2-5

Internal Connections. Must be connected to V

Power Input. Positive Supply.

F0i

Framing 0-Type (Input). This is the input for the frame synchronization pulse
for the 2048 kbit/s ST-BUS streams. A low on this input causes the internal counter
to reset on

the next negative transition of C4i.

7
8
9
10
11
12
13
14
15
16

39
38
37
36
35
34
33
32
31
30

STi3

IC
IC
IC
IC

VDD

F0i

C4i

A0
A1

STo3
IC
IC
IC
IC
VSS
D0
D1
D2
D3
D4

STi

ODE

44 PIN PLCC

DTA
STi0
STi1
STi2
STi3

IC
IC
IC
IC

VDD

F0i

C4i

A0
A1
A2
A3
A4
A5

IC
ODE
STo0
STo1
STo2
STo3
IC
IC
IC
IC
VSS
D0
D1
D2
D3
D4
D5
D6
D7
CS

2
3
4
5
6
7
8
9

10
11
12
13
14
15
16
17
18
19
20

R/W

40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21

40 PIN CERDIP/PLASTIC DIP

STi

STo

2
3
4
5
6
7
8
9
10

33
32
31
30
29
28
27
26
25
24

44 PIN QFP

STi3

IC
IC
IC
IC

VDD

F0i

C4i

A0
A1
A2

STo3
IC
IC
IC
IC
VSS
D0
D1
D2
D3
D4

STi

STo

ISO-CMOS

MT8981D

2-19

C4i

4.096 MHz Clock (Input). ST-BUS bit cell boundaries lie on the alternate falling
edges of this clock.

13-

15-

9-11

A0-A2 Address 0 to 2 (Inputs). These are the inputs for the address lines on the

microprocessor interface.

16-

19-

13-

A3-A5 Address 3 to 5 (Inputs). These are the inputs for the address lines on the

microprocessor interface

Data Strobe (Input). This is the input for the active high data strobe on the
microprocessor interface.

R/W

Read or Write (Input). This is the input for the read/write signal on the
microprocessor interface - high for read, low for write.

Chip Select (Input). This is the input for the active low chip select on the
microprocessor interface.

22-

25-

19-

D7-D5 Data 7 to 5 (Three-state I/O Pins). These are the bidirectional data pins on the

microprocessor interface.

25-

29-

23-

D4-D0 Data 4 to 0 (Three-state I/O Pins). These are the bidirectional data pins on the

microprocessor interface.

Power Input. Negative Supply (Ground).

31-

35-

29-

Internal Connections. Leave pins disconnected.

STo3 ST-BUS Output 3 (Three-state Outputs). These are the pins for the four 2048 kbit/s

ST-BUS output streams.

36-

41-

35-

STo2-

STo0

ST-BUS Output 2 to 0 (Three-state Outputs). These are the pins for the four 2048
kbit/s ST-BUS output streams.

ODE

Output Drive Enable (Input). If this input is held high, the STo0-STo3 output drivers
function normally. If this input is low, the STo0-STo3 output drivers go into their high
impedance state. NB: Even when ODE is high, channels on the STo0-STo3 outputs
can go high impedance under software control.

Internal Connection. Leave pin disconnected.

Pin Description (continued)

Pin #

Name

Description

DIP

PLCC

QFP

MT8981D

ISO-CMOS

2-20

Functional Description

In recent years, there has been a trend in telephony
towards digital switching, particularly in association
with software control. Simultaneously, there has
been a trend in system architectures towards
distributed processing or multi-processor systems.

In accordance with these trends, MITEL has devised
the ST-BUS (Serial Telecom Bus). This bus
architecture can be used both in software-controlled
digital voice and data switching, and for
interprocessor communications. The uses in
switching and in interprocessor communications are
completely integrated to allow for a simple general
purpose architecture appropriate for the systems of
the future.

The serial streams of the ST-BUS operate
continuously at 2048 kbit/s and are arranged in 125
µs wide frames which contain 32 8-bit channels.
MITEL manufactures a number of devices which
interface to the ST-BUS; a key device being the
MT8981 chip.

The MT8981 can switch data from channels on ST-
BUS inputs to channels on ST-BUS outputs, and
simultaneously allows its controlling microprocessor
to read channels on ST-BUS inputs or write to
channels on ST-BUS outputs (Message Mode). To
the microprocessor, the MT8981 looks like a memory
peripheral. The microprocessor can write to the
MT8981 to establish switched connections between
input ST-BUS channels and output ST-BUS
channels, or to transmit messages on output ST-
BUS channels. By reading from the MT8981, the
microprocessor can receive messages from ST-BUS
input channels or check which switched connections
have already been established.

By integrating both switching and interprocessor
communications, the MT8981 allows systems to use
distributed processing and to switch voice or data in
an ST-BUS architecture.

Hardware Description

Serial data at 2048 kbit/s is received at the four ST-
BUS inputs (STi0 to STi3), and serial data is
transmitted at the four ST-BUS outputs (STo0 to
STo3). Each serial input accepts 32 channels of
digital data, each channel containing an 8-bit word
which may represent a PCM-encoded analog/voice
sample as provided by a codec (e.g., MITEL's
MT8964).

This serial input word is converted into parallel data
and stored in the 128 X 8 Data Memory. Locations in
the Data Memory are associated with particular
channels on particular ST-BUS input streams.
These locations can be read by the microprocessor
which controls the chip.

Locations in the Connection Memory, which is split
into high and low parts, are associated with
particular ST-BUS output streams. When a channel
is due to be transmitted on an ST-BUS output, the
data for the channel can either be switched from an
ST-BUS input or it can originate from the
microprocessor. If the data is switched from an
input, then the contents of the Connection Memory
Low location associated with the output channel is
used to address the Data Memory. This Data
Memory address corresponds to the channel on the
input ST-BUS stream on which the data for switching
arrived. If the data for the output channel originates
from the microprocessor (Message Mode), then the
contents of the Connection Memory Low location
associated with the output channel are output
directly, and this data is output repetitively on the
channel once every frame until the microprocessor
intervenes.

The Connection Memory data is received, via the
Control Interface, at D7 to D0. The Control Interface
also receives address information at A5 to A0 and
handles the microprocessor control signals CS,
DTA, R/W and DS. There are two parts to any
address in the Data Memory or Connection
Memory. The higher order bits come from the

Figure 3 - Address Memory Map

HEX ADDRESS

LOCATION

0
1
1

·
·
·

0
0

·
·
·

0
0

·
·
·

0
0

·
·
·

0
0

·
·
·

0
1

·
·
·

00 - 1F

20
21

·
·
·

Control Register *

Channel 0

Channel 1

·
·
·

Channel 31

* Writing to the Control Register is the only fast transaction.
Memory and stream are specified by the contents of the Control Register.

ISO-CMOS

MT8981D

2-21

Control Register, which may be written to or read
from via the Control Interface. The lower order bits
come from the address lines directly.

The Control Register also allows the chip to
broadcast messages on all ST-BUS outputs (i.e., to
put every channel into Message Mode), or to split the
memory so that reads are from the Data Memory and
writes are to the Connection Memory Low. The
Connection Memory High determines whether
individual output channels are in Message Mode,
and allows individual output channels to go into a
high-impedance state, which enables arrays of
MT8981s to be constructed. It also controls the
CSTo pin.

All ST-BUS timing is derived from the two
signals C4i and F0i.

Software Control

The address lines on the Control Interface give
access to the Control Register directly or, depending
on the contents of the Control Register, to the High
or Low sections of the Connection Memory or to the
Data Memory.

If address line A5 is low, then the Control Register is
addressed regardless of the other address lines (see
Fig. 3). If A5 is high, then the address lines A4-A0
select the memory location corresponding to channel
0-31 for the memory and stream selected in the
Control Register.

The data in the Control Register consists of mode
control bits, memory select bits, and stream address
bits (see Fig. 4). The memory select bits allow the
Connection Memory High or Low or the Data
Memory to be chosen, and the stream address bits
define one of the ST-BUS input or output streams.

Bit 7 of the Control Register allows split memory
operation - reads are from the Data Memory and
writes are to the Connection Memory Low.

The other mode control bit, bit 6, puts every output
channel on every output stream into active Message
Mode; i.e., the contents of the Connection Memory
Low are output on the ST-BUS output streams once
every frame unless the ODE pin is low. In this mode
the chip behaves as if bits 2 and 0 of every
Connection Memory High location were 1, regardless
of the actual values.

Figure 4 - Control Register Bits

BIT

NAME

DESCRIPTION

Split

Memory

When 1, all subsequent reads are from the Data Memory and writes are to the Connection
Memory Low, except when the Control Register is accessed again. When 0, the Memory
Select bits specify the memory for subsequent operations. In either case, the Stream
Address Bits select the subsection of the memory which is made available.

Message

Mode

When 1, the contents of the Connection Memory Low are output on the Serial Output
streams except when the ODE pin is low. When 0, the Connection Memory bits for each
channel determine what is output.

(unused)

4-3

Memory

Select Bits

0-0 - Not to be used
0-1 - Data Memory (read only from the microprocessor port)
1-0 - Connection Memory Low
1-1 - Connection Memory High

(unused)

Must be a 0.

1-0

Stream

Address

Bits

The number expressed in binary notation on these bits refers to the input or output ST-
BUS stream which corresponds to the subsection of memory made accessible for
subsequent operations.

Mode

Control

Bits

(unused)

Memory

Select

Bits

Stream

Address

Bits

(unused)

MT8981D

ISO-CMOS

2-22

Figure 5 - Connection Memory High Bits

Figure 6 - Connection Memory Low Bits

BIT

NAME

DESCRIPTION

Message

Channel

When 1, the contents of the corresponding location in Connection Memory Low are
output on the location's channel and stream. When 0, the contents of the corresponding
location in Connection Memory Low act as an address for the Data Memory and so
determine the source of the connection to the location's channel and stream.

Unused

Output
Enable

If the ODE pin is high and bit 6 of the Control Register is 0, then this bit enables the
output driver for the location's channel and stream. This allows individual channels on
individual streams to be made high-impedance, allowing switching matrices to be
constructed. A 1 enables the driver and a 0 disables it.

BIT

NAME

DESCRIPTION

(Unused)

Must be a 0.

6-5*

Stream

Address

Bits*

The number expressed in binary notation on these 2 bits is the number of the ST-BUS
stream for the source of the connection. Bit 6 is the most significant bit. e.g., if bit 6 is 1,
and bit 5 is 0, then the source of the connection is a channel on STi2.

4-0*

Channel
Address

Bits*

The number expressed in binary notation on these 5 bits is the number of the channel
which is the source of the connection (The ST-BUS stream where the channel lies is
defined by bits 6 and 5.). Bit 4 is the most significant bit. e.g., if bit 4 is 1, bit 3 is 0, bit 2 is
0, bit 1 is 1 and bit 0 is 1, then the source of the connection is channel 19.

*If bit 2 of the corresponding Connection High location is 1 or if bit 6 of the Control Register is 1, then these entire
8 bits are output on the channel and stream associated with this location. Otherwise, the bits are used as
indicated to define the source of the connection which is output on the channel and stream associated with this
location.

No Corresponding Memory
- These bits give 0s if read.

Per Channel

Control Bits

(unused)

Stream

Address

Bits

Channel
Address

Bits

ISO-CMOS

MT8981D

2-23

If bit 6 of the Control Register is 0, then bits 2 and 0
of each Connection Memory High location function
normally (see Fig. 5). If bit 2 is 1, the associated ST-
BUS output channel is in Message Mode; i.e., the
byte in the corresponding Connection Memory Low
location is transmitted on the stream at that channel.
Otherwise, one of the bytes received on the serial
inputs is transmitted and the contents of the
Connection Memory Low define the ST-BUS input
stream and channel where the byte is to be found
(see Fig. 6).

If the ODE pin is low, then all serial outputs are high-
impedance. If it is high and bit 6 in the Control
Register is 1, then all outputs are active. If the ODE
pin is high and bit 6 in the Control Register is 0, then
the bit 0 in the Connection Memory High location
enables the output drivers for the corresponding
individual ST-BUS output stream and channel. Bit
0=1 enables the driver and bit 0=0 disables it (see
Fig. 5).

Applications

Use in a Simple Digital Switching System

Fig. 7 and 8 show how MT8981s can be used with
MT8964s to form a simple digital switching system.
Fig. 7 shows the interface between the MT8981s and
the filter/codecs. Fig. 8 shows the position of these
components in an example architecture.

The MT8964 filter/codec in Fig. 7 receives and
transmits digitised voice signals on the ST-BUS input
D

, and ST-BUS output D

, respectively. These

signals are routed to the ST-BUS inputs and outputs
on the top MT8981, which is used as a digital speech
switch.

The MT8964 is controlled by the ST-BUS input D

originating from the bottom MT8981, which
generates the appropriate signals from an output
channel in Message Mode. This architecture
optimises the messaging capability of the line circuit
by building signalling logic, e.g., for on-off hook
detection, which communicates on an ST-BUS
output. This signalling ST-BUS output is monitored
by a microprocessor (not shown) through an ST-BUS
input on the bottom MT8981.

Fig. 8 shows how a simple digital switching system
may be designed using the ST-BUS architecture.
This is a private telephone network with 128
extensions which uses a single MT8981 as a speech
switch and a second MT8981 for communication with
the line interface circuits.

A larger digital switching system may be designed by
cascading a number of MT8981s. Fig. 9 shows how
four MT8981s may be arranged in a non-blocking
configuration which can switch any channel on any
of the ST-BUS inputs to any channel on the ST-BUS
outputs.

Figure 7 - Example of Typical Interface between 8981s and 8964s for Simple Digital Switching System

8981 used

speech

switch

MT8981

STo0
STi0

MT8981

8981 used

in message

mode for

control and

signalling

MT8964

Filter/Codec

Signalling

Logic

Line Driver

and

2- to 4-

Wire

Converter

Line Interface Circuit with 8964 Filter/Codec

MT8981D

ISO-CMOS

2-24

Figure 8 - Example Architecture of a Simple Digital Switching System

Controlling

Micro-

Processor

Speech

Switch

8981

Control &

Signalling

8981

STo0-3

STi0-3

STo0-3

Line Interface Circuit

with Codec (e.g. 8964)

Line 1

Line 128

Line Interface Circuit

with Codec (e.g. 8964)

·
·
·

Repeated for Lines

2 to 127

·
·
·

Repeated for Lines

2 to 127

STi0-3

Application Circuit with 6802 Processor

Fig. 10 shows an example of a complete circuit
which may be used to evaluate the chip.

For convenience, a 4 MHz crystal oscillator has been
used rather than a 4.096 MHz clock, as both are
within the limits of the chip's specifications. The RC
delay used with the 393 counters ensures a
sufficient hold time for the FP signal, but the values
used may have to be changed if faster 393 counters
become available.

The chip is shown as memory mapped into the
MEK6802D3 system. Chip addresses 00-3F
correspond to processor addresses 2000-203F.
Delay through the address decoder requires the
VMA signal to be used twice to remove glitches. The
MEK6802D3 board uses a 10K

pullup on the MR

pin, which would have to be incorporated into the
circuit if the board was replaced by a processor.

Figure 9 - Four 8981s Arranged in a Non-Blocking 8 x 8 Configuration

IN 0/3

IN 4/7

8981

STi0/3 STo0/3

8981

STi0/3 STo0/3

8981

STi0/3 STo0/3

8981

STi0/3 STo0/3

OUT 0/3

OUT 4/7

ISO-CMOS

MT8981D

2-25

Figure 10 - Application Circuit with 6802

MEK6802D3
System

D7-D0

A15-A0

R/W

VMA

A15
A14
A13

0V
0V

VMA

A12
A11
A10

0V
0V

A9
A8
A7
0V
0V

VMA

0V
0V
0V

1
2
3
4
5

6
7
8

16
15
14
13
12

11
10
9

1
2
3
4
5

6
7
8

16
15
14
13
12

11
10
9

1
2
3
4
5
6
7
8

16
15
14
13
12
11
10
9

1
2
3
4
5
6
7
8

16
15
14
13
12
11
10
9

1
2
3
4
5

6
7
8

20
19
18
17
16

15
14
13

9
10

12
11

HCT

138

HCT

138

HCT

138

HCT

138

HCT

240

DTA

C4i

F0i

5V
0V
MR

4 MHz

1
2
3
4
5
6
7

14
13
12
11
10
9
8

C4i
0V

HCT

393

HCT

393

909

1/4W

8981

DTA

STi0
STi1
STi2
STi3

VDD

F0i

C4i

A0
A1
A2
A3
A4
A5

R/W

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20

CSTo
ODE
STo0
STo1
STo2
STo3

VSS
D0
D1
D2
D3
D4
D5
D6
D7
CS

39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21

510

100pF

1
2
3
4
5
6
7

14
13
12
11
10
9
8

MT8981D

ISO-CMOS

2-26

* Exceeding these values may cause permanent damage. Functional operation under these conditions is not implied.

Typical figures are at 25°C and are for design aid only: not guaranteed and not subject to production testing.

Figure 11 - Output Test Load

Absolute Maximum Ratings*

Parameter

Symbol

Min

Max

Units

- V

-0.3

Voltage on Digital Inputs

-0.3

+0.3

Voltage on Digital Outputs

-0.3

+0.3

Current at Digital Outputs

Storage Temperature

-65

+150

°C

Package Power Dissipation

Recommended Operating Conditions

- Voltages are with respect to ground (V

) unless otherwise stated.

Characteristics

Sym

Min

Typ

Max

Units

Test Conditions

Operating Temperature

-40

+85

°C

Positive Supply

4.75

5.25

Input Voltage

DC Electrical Characteristics

- Voltages are with respect to ground (V

) unless otherwise stated.

Characteristics

Sym

Min

Typ

Max

Units

Test Conditions

N
P
U

T
S

Supply Current

Outputs unloaded

Input High Voltage

2.0

Input Low Voltage

0.8

Input Leakage

between V

and V

Input Pin Capacitance

T
P

T
S

Output High Voltage

2.4

= 10 mA

Output High Current

Sourcing. V

=2.4V

Output Low Voltage

0.4

= 5 mA

Output Low Current

Sinking. V

= 0.4V

High Impedance Leakage

between V

and V

Output Pin Capacitance

Output

Pin

Test Point

S1 is open circuit except

when testing output levels
or high impedance states.

S2 is switched to V

when testing output

levels or high impedance
states.

ISO-CMOS

MT8981D

2-27

Timing is over recommended temperature & power supply voltages
Typical figures are at 25°C and are for design aid only: not guaranteed and not subject to production testing.
* Contents of Connection Memory are not lost if the clock stops, however, ST-BUS outputs go into the high impedance state.
NB: Frame Pulse is repeated every 512 cycles of C4i.

Figure 12 - Frame Alignment

Figure 13 - Clock Timing

AC Electrical Characteristics

- Clock Timing (Figures 12 and 13)

Characteristics

Sym

Min

Typ

Max

Units

Test Conditions

N
P
U

T
S

Clock Period*

CLK

220

244

300

Clock Width High

122

150

Clock Width Low

110

122

150

Clock Transition Time

CTT

Frame Pulse SetupTime

FPS

200

Frame Pulse Hold Time

FPH

0.020

Frame Pulse Width

FPW

244

CLK

CTT

CHL

CTT

FPH

FPS

FPH

FPS

FPW

C4i

F0i

2.0V

0.8V

2.0V

0.8V

C4i

F0i

BIT
CELLS

Channel 31

Bit o

Channel 0

Bit 7

MT8981D

ISO-CMOS

2-28

Timing is over recommended temperature & power supply voltages
Typical figures are at 25°C and are for design aid only: not guaranteed and not subject to production testing.
* High Impedance is measured by pulling to the appropriate rail with R

, with timing corrected to cancel time taken to discharge C

AC Electrical Characteristics

- Serial Streams (Figures 11, 14, 15 and 16)

Characteristics

Sym

Min

Typ

Max

Units

Test Conditions

O
U

T
P

T
S

STo0/3 Delay - Active to High Z

SAZ

=1 K

, C

=150 pF

STo0/3 Delay - High Z to Active

SZA

125

=150 pF

STo0/3 Delay - Active to Active

SAA

125

=150 pF

STo0/3 Hold Time

SOH

=150 pF

Output Driver Enable Delay

OED

125

=1 K

, C

=150 pF

External Control Hold Time

XCH

=150 pF

External Control Delay

XCD

110

=150 pF

Serial Input Setup Time

SIS

-40

-20

Serial Input Hold Time

SIH

Figure 14 - Serial Outputs and External Control

C4i

2.0V

0.8V

STo0
to
STo3

2.4V

0.4V

STo0
to
STo3

2.4V

0.4V

STo0
to

2.4V

0.4V

Bit Cell Boundary

STo3

SOH

SAZ

SZA

SOH

SAA

Figure 15 - Output Driver Enable

Figure 16 - Serial Inputs

Bit Cell Boundaries

C4i

2.0V

0.8V

2.0V

0.8V

SIS

SIH

STi0
to
STi3

ODE

2.0V

0.8V

STo0
to
STo3

2.4V

0.4V

OED

ISO-CMOS

MT8981D

2-29

Timing is over recommended temperature & power supply voltages.
Typical figures are at 25°C and are for design aid only: not guaranteed and not subject to production testing.
* High Impedance is measured by pulling to the appropriate rail with R

, with timing corrected to cancel time taken to discharge C

Processor accesses are dependent on the C4i clock, and so some timings are expressed as multiples of the C4i clock period.

Figure 17 - Processor Bus

AC Electrical Characteristics

- Processor Bus (Figures 11 and 17)

Characteristics

Sym

Min

Typ

Max

Units

Test Conditions

Chip Select Setup Time

CSS

Read/Write Setup Time

RWS

Address Setup Time

ADS

Acknowledgement Delay Fast

Slow

AKD

100

=150 pF

AKD

2.7

7.2

cycles

C4i cycles

Fast Write Data Setup Time

FWS

Slow Write Data Delay

SWD

2.0

1.7

cycles

C4i cycles

Read Data Setup Time

RDS

0.5

cycles

C4i cycles

, C

= 150 pF

Data Hold Time

Read

Write

DHT

=1 K

, C

=150 pF

DHT

Read Data To High Impedance

RDZ

=1 K

, C

=150 pF

Chip Select Hold Time

CSH

Read/Write Hold Time

RWH

Address Hold Time

ADH

Acknowledgement Hold Time

AKH

=1 K

, C

=150 pF

2.0V

0.8V

2.0V

0.8V

2.0V

0.8V

2.0V

0.8V

2.4V

0.4V

2.4V (Read) 2.0V (Write)

0.8V (Read 0.8V (Write)

R/W

DTA

CSS

RWS

ADS

AKD

RDS

SWD

FWS

CSH

RWH

ADH

AKH

DHT

RDZ

to
A0

to
D0

Ð­Ð»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: MT8981D

ÐÐ»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: MT8981D