5-15

MT90732

E2/E3 Framer (E2/E3F)

Features

Framer for CCITT Recommendations

- G.742 (8448 kbit/s)

- G.745 (8448 kbit/s)

- G.751 (34368 kbit/s)

- G.753 (34368 kbit/s)

Line side interface

- Dual rail or NRZ

HDB3 codec for dual rail I/O

Terminal side interface

- Nibble-parallel

- Bit-serial

Transmit reference generator for bit-serial I/O

Microprocessor or control leads

I/O port for service bits

Applications

Line terminals

Wideband data or video transport

Test equipment

Multiplexer systems

Description

The MT90732 E2/E3 Framer (E2/E3F) is a CMOS
VLSI device that provides the functions needed to
frame a wideband payload to one of four CCITT
Recommendations. G.742, G.745, G.751, or G.753.
The E2/E3 Framer interfaces to line circuitry with
either dual rail or NRZ signals. On the terminal side,
the interface can be either nibble-parallel or bit-
serial.

The MT90732 can be operated with or without a
microprocessor. When interfaced with a
microprocessor, the E2/E3 Framer provides an 8-
byte memory map for control, performance counters
and alarm status. The MT90732 provides a transmit
and receive interface port for accessing the
overhead bits from each of the four
recommendations. The overhead bits can also be
accessed by the microprocessor via the memory
map.

Ordering Information

MT90732AP 68 Pin PLCC

-40°C to +85°C

Figure 1 - Functional Block Diagram

RP/RDL

RCK/RCKL

TCK/TCKL

RNIB3
RNIB2
RNIB1
RNIB0
RNC
RNF

AD7

SEL
ALE
RD
WR
RDY

XNIB3
XNIB2
XNIB1

XNIB0

XCK
XNF
XNC

TP/TDL

Framer

Interpreter

Output

Micro-

Input

G.7XX

Send

Line

Encoder

Control

RSD
TDOUT
TCG
TFOUT

RSC
RSF
RCG

N.C.

SERIAL

PARALLEL

XSF

TCIN
XSD

XCK

TCOUT

Data

Clock

Frame

Framing

AD6
AD5
AD4
AD3
AD2
AD1
AD0

processor

I/O

Transmit

Reference

Generator

Line

Decoder

RAIS

RLOC

BIP-4E

RLOF

ROD
ROC

ROF

NRZ LINE

BIP-4

M0
M1

MICRO

SER

TLBK

PLBK

TAIS

LPT

TLOC

FORCEFE

TOD
TOC

TOF

RESET

TCKL

TDL

RDL
RCKL

DAIS

Line Side

Terminal Side

TLCINV

ISSUE 1

May 1995

U.S. Patent Number 5040170

Advance Information

CMOS

MT90732

CMOS

Advance Information

5-16

Figure 2 - Pin Connections

Pin Description

Note: I = Input; O = Output; P = Power

Power Supply and Ground

Pin #

Name

I/O/P

Description

1,17,35,51

VDD

VDD. 5-volt supply voltage, +/- 5%

18,34,52,68

GND

Ground.

Line Side Receive

Pin #

Name

I/O/P

Description

RP/RDL

Receive Positive Rail/Receive NRZ Data. Receive positive rail/NRZ data
generated from line interface circuit.

Receive Negative Rail Data. Receive negative rail data generated from line
interface circuit.

RCK/RCKL

Receive Clock Rail/Receive Clock NRZ. The receive clock is used for clock-
ing in the rail/NRZ data signals.

ROC

ROF

NRZLINE

BIP-4

VDD

GND

MICRO

SER

TLBK

PLBK

TAIS

LPT

TLOC

FORCEFE

BIP-4E

XNC/TCOUT

XNF

XCK

XNIB0/XSD

XNIB1/TCIN

XNIB2

XNIB3/XSF

GND

VDD

TLCINV

DAIS

RDY

ALE

SEL

RLO

RCK

/RCK

/RDL

RNC/RS

RNIB

/RS

RNF

/RS

RCG

/
T

/
TC

Advance Information

CMOS

MT90732

5-17

Note: I = Input; O = Output; P = Power

Line Side Transmit

Pin #

Name

I/O/P

Description

TP/TDL

Transmit Positive Rail/Transmit NRZ Data. Transmit positive rail/NRZ data
sent out of E2/E3 Framer.

TCK/TCKL

Transmit Clock Rail/Transmit Clock NRZ. The transmit clock is used for
clocking out the dual rail/NRZ data signals. The TCK/TCKL clock signal is
derived from the XCK clock.

Transmit Negative Rail Data. Transmit negative rail data sent out of E2/E3
Framer.

Terminal Interface

Pin #

Name

I/O/P

Description

RCG

Receive Clock Gapped. An active low signal indicates the receive framing
and service bit locations in the serial mode only.

RNF/RSF

Receive Framing Pulse. Framing pulse is synchronous with the last nibble for
the nibble-parallel interface, and with the first bit in the frame for the bit-serial
interface.

RNIB3/RSD

Receive Nibble Bit 3/Receive Serial Data. Bit 3 is the most significant bit in
the nibble and corresponds to the first bit received in the nibble. The framing
pattern, service bits, and BIP-4 nibble are not provided as parallel data. In the
serial mode receive data signal consists of all bits, including the framing pat-
tern and service bits.

RNIB2/TDO

Receive Nibble Bit 2/Transmit Reference Generator Data Output. In the
nibble-parallel mode, it is Bit 2 of the received nibble.The reference generator
is enabled in the serial mode. The output data signal (TDOUT) consists of all
ones in place of the framing bits and zeros elsewhere in the frame.

RNIB1/TCG

Receive Nibble Bit 1/Transmit Reference Generator Clock Gap Signal. In
the nibble-parallel mode, it is Bit 1 of the received nibble. The active low TCG
signal indicates the location of the framing pattern and the service bits in the
frame.

RNIB0/TFO

Receive Nibble Bit 0/Transmit Reference Generator Framing Pulse. Bit 0
is the least significant bit in the nibble and is the last bit received. The active
low TFOUT signal is synchronous with the first bit in the frame.

RNC/RSC

Receive Nibble Clock/Receive Serial Clock. The nibble and serial clocks are
derived from the line side dual rail/NRZ clock signal (RCK/RCKL). RNC is
gapped during framing pattern, service bit and BIP-4 bit times.

XNIB3/XSF

Transmit Nibble Bit 3/Transmit Serial Framing Pulse. In the nibble-parallel
mode, bit 3 is the most significant bit in the nibble and corresponds to the first
bit transmitted in the nibble. When the terminal interface is serial, the negative
framing pulse is synchronous with the first bit in the frame.

XNIB2

Transmit Nibble Bit 2. Bit 2 in the 4-bit nibble.

XNIB1/TCI

Transmit Nibble Bit 1/Transmit Reference Generator Clock In. Bit 1 in the
transmit nibble. For a serial interface, the TCIN is used to derive the clock out
(TCOUT), data signal (TDOUT), framing pulse (TFOUT), and gapped clock
signal (TCG).The reference generator signals are provided for multiplexing the
external payload data into the serial frame.

MT90732

CMOS

Advance Information

5-18

Note: I = Input; O = Output; P = Power

XNIB0/XSD

Transmit Nibble Bit 0/Transmit Serial Data. In the nibble-parallel mode, bit 0
is the least significant bit in the nibble. For a serial interface, the input must
consist of all the bits in the frame.

XCK

Transmit Clock. For the terminal side nibble-parallel interface, the XCK is
used for all transmit timing functions, including deriving the nibble output clock
(XNC) and framing pulse (XNF).For the serial interface, this clock may be
derived from the transmit reference generator clock output (TCOUT).

XNF

Transmit Nibble Framing Pulse. The XNF and clock signal (XNC) are pro-
vided for multiplexing nibble data into the E2/E3 Framer from external circuitry.
The negative framing pulse identifies the first bit in the frame.

XNC/TCOU

Transmit Nibble Clock/Transmit Reference Generator Clock Out. The
XNC is derived from the transmit clock (XCK) and is used as a time base for
clocking data out of the external multiplexer and into the E2/E3 Framer. XNC is
gapped during the framing pattern, service bit and BIP-4 bit times. TCOUT is
derived from the input clock (TCIN), and has the same duty cycle.

Service Bit Interface

Pin #

Name

I/O/P

Description

ROD

Receive Service Data Bits. These service bits are clocked out of E2/E3
Framer on positive transitions of clock signal (ROC).

ROC

Receive Service Bits Clock. A gapped clock that clocks out the service bits.
The clock is active only for clocking out the receive service data bits(ROD).

ROF O

Receive Service Bits Framing Pulse. A positive framing pulse that is syn-
chronous with the first bit in the frame.

TOD

Transmit Service Data Bits. The service bits are clocked into E2/E3 Framer
on positive transitions of clock signal (TOC).

TOC

Transmit Service Bits Clock. A gapped clock that clocks in the service bits.
The clock is active only for clocking in the transmit service data bits (TOD).

TOF

Transmit Service Bits Framing Pulse. A positive framing pulse that is syn-
chronous with the first bit in the frame.

Microprocessor Interface

Pin #

Name

I/O/P

Description

36-43

AD(7-0)

I/O

Address/Data Bus. These leads constitute the time-multiplexed address and
data bus for accessing the registers which reside in the E2/E3F.

SEL

Select. A low enables the microprocessor to access the E2/E3F memory map
for control, status, and alarm information.

ALE

Address Latch Enable. An active high signal generated by the microproces-
sor. Used by the microprocessor to hold an address stable during a read/write
bus cycle.

Read. An active low signal generated by the microprocessor for reading the
registers which reside in the memory map.

Terminal Interface

Pin #

Name

I/O/P

Description

Advance Information

CMOS

MT90732

5-19

Note: I = Input; O = Output; P = Power

Write. An active low signal generated by the microprocessor for writing to the
registers which reside in the memory map.

RDY

Ready. An active high signal indicating an E2/E3F acknowledgment to the
microprocessor that the addressed memory map location can complete the
data transfer.

Control Interface

Pin #

Name

I/O/P

Description

NRZLINE

Non-Return to Zero Line Selection. A high enables an NRZ line input (RP
and TP), and causes the HDB3 decoder/encoder to be bypassed. When low
enables the dual rail interface (RP/RN and TP/TN) and the HDB3
decoder/encoder.

BIP-4

Bit Interleaved Parity - 4. A high enables the BIP-4 function. In the transmit
direction, the BIP-4 is calculated for data nibbles only, and is sent as the last
nibble in the frame format. In the receive direction, the BIP-4 is calculated for
the data bits only and compared against the received value which is present in
the last four bits of the frame. An output indication (BIP-4E) occurs when one
or more columns do not match.

16
15

M1
M0

Mode Control. The two controls select the operating rate of the E2/E3F
according to the table given below.

MICRO

Microprocessor Mode. A high enables the microprocessor interface. When
the microprocessor is enabled, the following hardware control leads are dis-
abled. BIP-4, Mode (M0 and M1), Serial I/O (SER), and transmit AIS (TAIS).
Bits are provided in the memory map for controlling these functions.

SER

Serial Interface. A high selects the bit-serial interface for the terminal side
interface. A low selects the nibble-parallel interface.

TLBK

Terminal Loopback. A low enables a transmit to receive loopback at the line
side.

PLBK

Payload Loopback. A low enables a receive to transmit loopback at the termi-
nal side in the serial mode of operation only.

TAIS

Transmit Alarm Indication Signal. A low causes an all ones signal (AIS) to
be sent in place of a G.7XX frame format.

LPT

Loop Timing. A low enables the loop timing feature. Loop timing disables the
transmit clock and enables the receive clock to be used as the transmit clock.

FORCEFE

Force Framing Error. The errored bit is sent into the framing pattern upon the
high-to-low transition of this pin.

Microprocessor Interface

Pin #

Name

I/O/P

Description

Recommendation

Rate (kbit/s)

G.745

8448

G.742

8448

G.753

34368

G.751

34368

5-20

MT90732

CMOS

Advance Information

Note: I = Input, O = Output, P = Power

RESET

Reset. A positive pulse applied to this pin resets the internal counters, logic
circuits, and the performance counters and control bits in the memory map to
zero. The reset pulse is applied after the power becomes stable.

DAIS

Disable AIS. A low disables the automatic insertion of AIS into the terminal
side receive nibble/serial bit stream.

TLCINV

Transmit Line Clock Invert. A low inverts the output clock TCK/TCKL when
operating in the dual rail mode.

Coding Violation. A positive pulse, one clock cycle wide, is generated when
an illegal coding violation is detected.

RAIS

Receive Alarm Indication Signal. An active low alarm occurs within one milli-
second after the E2/E3F detects an all ones condition, including in the pres-
ence of a 10

-3

error rate. An incoming signal with a framing pattern and all

ones in the data field is not mistaken as an AIS.

RLOC

Receive Loss of Clock. An active low alarm occurs when there are no transi-
tions in the received clock (RCK/RCKL). Recovery occurs on the first clock
transition.

RLOF

Receive Loss of Frame. An active low alarm occurs when a valid frame can-
not be detected accordingly to G.7XX recommendations.

Framing Error. An active high alarm occurs when one or more framing bits
are in error.

TLOC

Transmit Loss of Clock. An active low alarm occurs when there are no transi-
tions in the transmit clock (TCK). Recovery occurs on the first clock transition.

BIP-4E

BIP-4E. A positive pulse occurs when the comparison between the received
BIP-4 value and the calculated value does not match in a column.

Control Interface

Pin #

Name

I/O/P

Description

Functional Description

The block diagram for the E2/E3F is shown in Figure
1. The E2/E3F receives NRZ data signal (RDL) and
clock signal (RCKL), or a positive (RP) and negative
(RN) rail signal and clock signal (RCK), from a line
interface circuit. The selection of the line interface,
dual rail or NRZ, is controlled by the external lead
labeled NRZ LINE. Indications of HDB3 coding viola-
tion errors are provided on an external signal lead
(CV) as pulses. Coding violation errors are also
counted in an 8-bit saturating counter accessed by the
microprocessor through the memory map.

The selection of the framing format (G.742, G.745,
G.751 or G.753) is done by external control leads (M1
and M0), or by the microprocessor. The Framer Block
performs frame alignment and alarm detection includ-
ing Loss of Frame (RLOF), Loss of Clock (RLOC), AIS
detection (RAIS) and BIP-4 detection (BIP-4E). A
framing error (FE) output is also provided to indicate
when any of the framing bits in the G. 7XX frame are in
error. The disable AIS (DAIS) control lead permits the
E2/E3F to provide receive data on the terminal side

regardless of frame alignment. The external alarm
indications (latched and unlatched states) are provided
in the memory map, and unlatched alarm indications
are provided at signal leads.

The E2/E3F terminal side output block provides either
a bit-serial or a nibble-parallel interface. The interface
is selected by an external control lead (SER) or by the
microprocessor. The bit-serial interface consists of the
following signals: a data output signal (RSD), a clock
output signal (RSC), a receive clock gapped output
signal (RCG), and a framing pulse (RSF). The receive
clock gapped signal (RCG) identifies framing and ser-
vice bit times. The nibble-parallel interface consists of
data output signal having a nibble format (RNIB3
through RNIB0), a clock output signal (RNC), and a
framing pulse (RNF). In the nibble mode, the framing
pattern, service bits and BIP-4 nibble are not provided
at the interface. The receive nibble clock (RNC) is
gapped during framing pattern, service bit and BIP-4
times.

Advance Information

CMOS

MT90732

5-21

The transmitter operates independently of the receiver,
unless the loop timing feature(LPT) is selected, when
the receive clock becomes the transmitted clock. In the
transmit direction, the terminal side bit-serial interface
consists of: data input signal (XSD), a clock input sig-
nal (XCK), and a framing pulse (XSF). The nibble-par-
allel interface consists of the following signals: a data
input signal having a nibble format (XNIB3 - XNIB0), a
clock input signal (XCK), a framing output pulse (XNF),
and a nibble output clock signal (XNC). The transmit
nibble clock (XNC) is stretched to accommodate the
framing pattern, service bit and BIP-4 times.

MT90372 provides interface to service bits as defined
in G.7XX recommendations.The receive service bit
interface consists of: data output (ROD), clock output
(ROC), and framing pulse (ROF) output. The clock sig-
nal (ROC) is gapped and is provided for clocking out
the service bits. The service bit states are also written
into E2/E3F memory locations, which can be read by
the microprocessor. The transmitted service bits are
inserted into the frame format from either an external
interface or from memory map locations. The transmit
service bit interface consists of data input signal
(TOD), a clock output (TOC), and a framing pulse
(TOF) output.

To fix transmit time-base for the terminal payload multi-
plexer circuitry, while operating in the bit-serial mode,
the E2/E3F provides a transmit frame reference gener-
ator. The transmit frame reference generator accepts
an external 8.448 or 34.368 MHz clock signal (TCIN)
and produces a clock out signal (TCOUT), a framing
pulse (TFOUT), a clock gap signal (TCG), and a data
signal (TDOUT). The data signal consists of G.7XX
framing bits and zeros elsewhere.

The selection of the transmit line interface, dual rail or
NRZ, is controlled by the NRZLINE control lead, which

also controls the receive interface selection. When the
internal HDB3 Encoder Block is bypassed, the trans-
mit line interface consists of a data signal (TDL) and a
clock signal (TCKL). When the HDB3 encoder is
enabled, the transmit line interface consists of positive
(TP) and negative (TN) rail signals and a clock signal
(TCK).

A high placed on the microprocessor control lead
(MICRO) selects the microprocessor interface. All the
external control leads, except the loop timing (LPT),
receive AIS disable (DAIS), and the line interface con-
trol leads (NRZLINE) are disabled when the micropro-
cessor interface is selected.

The microprocessor interface consists of eight bidirec-
tional data and address leads (AD7 - AD0), along with
other microprocessor control leads, including a ready
(RDY) signal.

Typical Application

The E2/E3 Framer is used for wideband data
transport as shown in Figure 2. In the receive
direction, the E2/E3 Framer receives NRZ or dual rail
data from LIU, removes overhead bits and puts out
only the payload of the incoming signal to the
terminal. Overhead bits can be accessed through
microprocessor or by service bit interface. In the
transmit direction, the E2/E3 Framer receives data
generated from Data Source, adds framing pattern
and service bits and sends it out to LIU. The E2/E3
Framer handles wideband data at either 8448 or 34
368 Kb/s, and can optionally perform BIP-4 making
data transport more reliable.

Figure 2. Wideband Data Transport using E2/E3 Framer

Line Side

E2/E3

Framer

Line

Interface

Unit

Terminal Side

Wideband

Data Sink/ Source

Overhead bit-I/O

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