PIN CONFIGURATION (TOP VIEW)
Package type : 64P6N-A/64P6Q-A
DESCRIPTION
The 38C2 group is the 8-bit microcomputer based on the 740 family
core technology.
The 38C2 group has an LCD drive control circuit, a 10-channel A-D
converter, and a Serial I/O as additional functions.
The various microcomputers in the 38C2 group include variations of
internal memory size and packaging. For details, refer to the section
on part numbering.
FEATURES
q
Basic machine-language instructions ....................................... 71
q
The minimum instruction execution time .......................... 0.25
s
(at 8MHz oscillation frequency)
q
Memory size
ROM ................................................................ 16 K to 60 K bytes
RAM ................................................................. 640 to 2048 bytes
q
Programmable input/output ports ............................................. 51
(common to SEG: 24)
q
Interrupts ................................................... 18 sources, 16 vectors
q
Timers ............................................................ 8-bit
4, 16-bit
2
q
A-D converter ................................................. 10-bit
8 channels
q
Serial I/O ........................ 8-bit
2 (UART or Clock-synchronized)
q
PWM .................. 10-bit
2, 16-bit
1 (common to IGBT output)
q
LCD drive control circuit
Bias ................................................................................... 1/2, 1/3
Duty ........................................................................... 1/2, 1/3, 1/4
Common output .......................................................................... 4
Segment output ........................................................................ 24
q
Two clock generating circuits
(connect to external ceramic resonator or quartz-crystal oscillator)
q
Watchdog timer ............................................................... 8-bit
1
q
LED direct drive port .................................................................. 8
(average current: 15 mA, peak current: 30 mA, total current: 90 mA)
q
Power source voltage
In through mode .......................................................... 4.0 to 5.5 V
(at 8 MHz oscillation frequency)
In frequency/2 mode ................................................... 1.8 to 5.5 V
(at 4 MHz oscillation frequency, A-D operation excluded)
In low-speed mode ..................................................... 1.8 to 5.5 V
(at 32 kHz oscillation frequency)
q
Power dissipation
In through mode ................................................................. 26 mW
(at 8 MHz oscillation frequency, V
CC
= 5 V)
In low-speed mode ............................................................. 21
W
(at 32 kHz oscillation frequency, V
CC
= 3 V)
q
Operating temperature range ................................... 20 to 85C
Fig. 1 M38C2XMX-XXXFP pin configuration
38C2 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
P
0
6
/
S
E
G
6
P
0
7
/
S
E
G
7
P
1
0
/
S
E
G
8
P
1
1
/
S
E
G
9
P
1
2
/
S
E
G
1
0
P
1
3
/
S
E
G
1
1
P
1
4
/
S
E
G
1
2
P
1
5
/
S
E
G
1
3
P
1
6
/
S
E
G
1
4
P
1
7
/
S
E
G
1
5
P
6
0
/
C
N
T
R
1
P
3
7
/
C
N
T
R
0
/
(
L
E
D
7
)
61
3
2
3
1
30
29
2
8
2
7
2
6
2
5
2
4
2
3
2
2
2
1
6
7
8
9 1
0 11 12 1
3 1
4 15 1
6
4
5 44 4
3 4
2 4
1 40 3
9 3
8 3
7 36 3
5 3
4 3
3
P2
4
/SEG
20
P2
5
/SEG
21
COM
2
COM
1
COM
0
P2
7
/SEG
23
/V
L2
P2
6
/SEG
22
/V
L1
C
O
M
3
(
K
W
7
)
/
P
0
3
/
S
E
G
3
P
0
4
/
S
E
G
4
P
0
5
/
S
E
G
5
P5
1
/INT
1
(
K
W
2
)
/
P
5
6
/
S
C
L
K
1
(
K
W
1
)
/
P
5
5
/
T
X
D
1
(
K
W
0
)
/
P
5
4
/
R
X
D
1
P
5
3
/
T
4
O
U
T
/
P
W
M
1
P
2
0
/
S
E
G
1
6
P
2
1
/
S
E
G
1
7
P
2
2
/
S
E
G
1
8
P
2
3
/
S
E
G
1
9
4
9
5
0
5
1
5
2
5
3
4
8 4
7 4
6
6
2
6
3
6
4
1
2
3
4
5
2
0
19
1
8
1
7
5
5
5
6
5
7
5
8
59
60
M
3
8
C
2
X
M
X
-
X
X
X
F
P
5
4
P
3
6
/
T
2
O
U
T
/
/
(
L
E
D
6
)
X
O
U
T
P
5
2
/
T
3
O
U
T
/
P
W
M
0
VREF
V
L3
P
4
3
/
A
N
3
P
4
2
/
A
N
2
P
4
4
/
A
N
4
P
4
7
/
R
T
P
1
/
A
N
7
P
4
6
/
R
T
P
0
/
A
N
6
P
4
5
/
A
N
5
V
S
S
P
3
2
/
T
X
D
2
/
(
L
E
D
2
)
P3
1
/S
CLK2
/(LED
1)
P3
3
/R
X
D
2
/(LED
3)
P
5
0
/
I
N
T
0
AV
SS
(
K
W
6
)
/
P
0
2
/
S
E
G
2
(
K
W
5
)
/
P
0
1
/
S
E
G
1
(
K
W
4
)
/
P
0
0
/
S
E
G
0
P
4
1
/
O
O
U
T
1
/
A
N
1
P
4
0
/
O
O
U
T
0
/
A
N
0
C
N
V
S
S
P
6
2
/
X
C
O
U
T
P
6
1
/
X
C
I
N
V
C
C
X
I
N
R
E
S
E
T
(
K
W
3
)
/
P
5
7
/
S
R
D
Y
1
P
3
0
/
S
R
D
Y
2
/
(
L
E
D
0
)
P
3
5
/
T
X
O
U
T
/
(
L
E
D
5
)
P
3
4
/
I
N
T
2
/
(
L
E
D
4
)
PRELIMINAR
Y
Notice: This is not a final specification.
Some parametric limits are subject to change.
2
38C2 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
PRELIMINAR
Y
Notice: This is not a final specification.
Some parametric limits are subject to change.
FUNCTIONAL
BLOCK DIAGRAM
Fig. 2 Functional block diagram
T
i
m
e
r
T
i
m
e
r
X
(
1
6
b
i
t
s
)
P
W
M
(
1
6
b
i
t
s
)
I
G
B
T
o
u
t
p
u
t
T
i
m
e
r
Y
(
1
6
b
i
t
s
)
T
i
m
e
r
1
(
8
b
i
t
s
)
T
i
m
e
r
2
(
8
b
i
t
s
)
T
i
m
e
r
3
(
8
b
i
t
s
)
P
W
M
0
(
1
0
b
i
t
s
)
T
i
m
e
r
4
(
8
b
i
t
s
)
P
W
M
1
(
1
0
b
i
t
s
)
P
o
r
t
P
0
(
8
)
8
P
o
r
t
P
1
(
8
)
8
P
o
r
t
P
2
(
8
)
8
I
n
t
e
r
n
a
l
p
e
r
i
p
h
e
r
a
l
f
u
n
c
t
i
o
n
A
-
D
c
o
n
v
e
r
s
i
o
n
1
0
-
b
i
t
8
-
c
h
a
n
n
e
l
S
e
r
i
a
l
I
/
O
S
e
r
i
a
l
I
/
O
1
(
U
A
R
T
o
r
C
l
o
c
k
s
y
n
c
h
r
o
n
o
u
s
)
S
e
r
i
a
l
I
/
O
2
(
U
A
R
T
o
r
C
l
o
c
k
s
y
n
c
h
r
o
n
o
u
s
)
L
C
D
d
r
i
v
e
c
o
n
t
r
o
l
c
i
r
c
u
i
t
4
C
O
M
2
4
S
E
G
S
y
s
t
e
m
c
l
o
c
k
g
e
n
e
r
a
t
i
o
n
X
I
N
X
O
U
T
(
M
a
i
n
c
l
o
c
k
)
X
C
I
N
X
C
O
U
T
(
S
u
b
-
c
l
o
c
k
)
M
e
m
o
r
y
R
O
M
R
A
M
f
o
r
L
C
D
d
i
s
p
l
a
y
(
1
2
b
y
t
e
s
)
R
A
M
C
P
U
c
o
r
e
W
a
t
c
h
d
o
g
t
i
m
e
r
8
8
P
o
r
t
P
4
(
8
)
P
o
r
t
P
5
(
8
)
P
o
r
t
P
6
(
3
)
P
o
r
t
P
3
(
8
)
8
3
3
38C2 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
PRELIMINAR
Y
Notice: This is not a final specification.
Some parametric limits are subject to change.
Apply voltage of 1.8 V to 5.5 V to V
CC
, and 0 V to V
SS
.
Reference voltage input pin for A-D converter.
GND input pin for A-D converter. Connect to V
SS
.
Reset input pin for active "L."
Input and output pins for the main clock generating circuit.
Feedback resistor is built in between X
IN
pin and X
OUT
pin.
Connect a ceramic resonator or a quartz-crystal oscillator between the X
IN
and X
OUT
pins to
set the oscillation frequency. When an external clock is used, connect the clock source to X
IN
,
and leave X
OUT
pin open.
Input 0
V
L1
V
L2
V
L3
V
CC
voltage.
Input 0 V
L3
voltage to LCD.
LCD common output pins.
COM
2
and COM
3
are not used at 1/2 duty ratio.
COM
3
is not used at 1/3 duty ratio.
8-bit I/O port.
CMOS compatible input level.
CMOS 3-state output structure.
I/O direction register allows each port to be individually
programmed as either input or output.
Pull-up control is enabled.
V
CC
, V
SS
V
REF
AV
SS
RESET
X
IN
V
L3
COM
0
COM
3
P0
0
/SEG
0
P0
3
/SEG
3
P0
4
/SEG
4
P0
7
/SEG
7
P1
0
/SEG
8
P1
7
/SEG
15
P2
0
/SEG
16
P2
5
/SEG
21
P2
6
/SEG
22
/V
L1
P2
7
/SEG
23
/V
L2
P3
0
/S
RDY2
P3
1
/S
CLK2
P3
2
/TxD
2
P3
3
/RxD
2
P3
4
/INT
2
P3
5
/T
XOUT
P3
6
/T
2OUT
/
P3
7
/CNTR
0
P4
0
/O
OUT0
/AN
0
P4
1
/O
OUT1
/AN
1
P4
2
/AN
2
P4
5
/AN
5
P4
6
/RTP
0
/AN
6
P4
7
/RTP
1
/AN
7
P5
0
/INT
0
P5
1
/INT
1
P5
2
/T
3OUT
/PWM
0
P5
3
/T
4OUT
/PWM
1
P5
4
/RxD
1
P5
5
/TxD
1
P5
6
/S
CLK1
P5
7
/S
RDY1
Power source
Analog reference
voltage
Analog power source
Reset input
Clock input
LCD power
source
Common output
I/O port P0
I/O port P1
I/O port P2
I/O port P3
I/O port P4
I/O port P5
Function except a port function
PIN DESCRIPTION
Table 1 Pin description (1)
Function
Pin
Name
LCD segment
output pins
Serial I/O2 function pins
External interrupt pin
Timer X, Timer 2 output pins
Timer X function pin
AD converter input
pins
External interrupt pins
Timer 3, Timer 4 output pins
PWM output pins
Serial I/O1 function pins
Key input interrupt input pins
Key input interrupt
pins
LCD power source
input pins
Oscillation external
output pins
Real time port
function pins
X
OUT
Clock output
4
38C2 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
PRELIMINAR
Y
Notice: This is not a final specification.
Some parametric limits are subject to change.
Function except a port function
PIN DESCRIPTION
Table 2 Pin description (2)
Function
Pin
Name
P6
0
/CNTR
1
P6
1
/X
CIN
P6
2
/X
COUT
CNV
SS
I/O port P6
CNV
SS
3-bit I/O port.
CMOS compatible input level.
CMOS 3-state output structure.
I/O direction register allows each pin to be individually
programmed as either input or output.
Pull-up control is enabled.
V
PP
power input pin in the flash mode. When MCU is operating, connect to V
SS
.
Timer Y function pin
I/O pins for sub-clock generating circuit.
Connect oscillators to them.
5
38C2 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
PRELIMINAR
Y
Notice: This is not a final specification.
Some parametric limits are subject to change.
PART NUMBERING
Fig. 3 Part numbering
M38C2 9 M C XXX HP
Product
ROM/PROM size
1
2
3
4
5
6
7
8
: 4096 bytes
: 8192 bytes
: 12288 bytes
: 16384 bytes
: 20480 bytes
: 24576 bytes
: 28672 bytes
: 32768 bytes
The first 128 bytes and the last 2 bytes of ROM
are reserved areas ; they cannot be used.
Memory type
M
F
: Mask ROM version
: Flash memory version
RAM size
0
1
2
3
4
5
6
7
8
9
: 192 bytes
: 256 bytes
: 384 bytes
: 512 bytes
: 640 bytes
: 768 bytes
: 896 bytes
: 1024 bytes
: 1536 bytes
: 2048 bytes
Package type
FP
HP
ROM number
Omitted in Flash memory version.
Characteristics
: Standard
D : Extended operating temperature version
: 64P6N-A package
: 64P6Q-A package
9
A
B
C
D
E
F
: 36864 bytes
: 40960 bytes
: 45056 bytes
: 49152 bytes
: 53248 bytes
: 57344 bytes
: 61440 bytes
6
38C2 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
PRELIMINAR
Y
Notice: This is not a final specification.
Some parametric limits are subject to change.
GROUP EXPANSION
Mitsubishi plans to expand the 38C2 group as follows.
Memory Type
Support for mask ROM, Flash-memory versions
Memory Size
ROM/flash memory size ...................................... 16 K to 60 K bytes
RAM size ............................................................. 640 to 2048 bytes
Memory Expansion Plan
Fig. 4 Memory expansion plan
Currently supported products are listed below.
As of May 2000
Package
64P6N-A
64P6Q-A
64P6N-A
64P6Q-A
64P6N-A
64P6Q-A
64P6N-A
64P6Q-A
Product name
ROM size (bytes)
ROM size for User in ( )
49152 (49022)
24576 (24446)
16384 (16254)
61440 (61310)
RAM size
(bytes)
2048
640
640
2048
Table 3 Support products
Mask ROM version
Mask ROM version
Mask ROM version
Mask ROM version
Mask ROM version
Mask ROM version
Flash memory version
Flash memory version
Remarks
Packages
64P6Q-A ..................................... 0.5 mm-pitch plastic molded QFP
64P6N-A ..................................... 0.8 mm-pitch plastic molded QFP
Products under development or planning : the development schedule and specification may be revised without notice.
ROM size (bytes)
32K
28K
24K
20K
16K
12K
8K
4K
256
384
512
640
768
896
1024
192
RAM size (bytes)
40K
48K
56K
60K
Under development
Under development
Under development
1536
2048
M38C24M6
M38C24M4
M38C29FF
Under development
M38C29MC
M38C29MC-XXXFP
M38C29MC-XXXHP
M38C24M6-XXXFP
M38C24M6-XXXHP
M38C24M4-XXXFP
M38C24M4-XXXHP
M38C29FFFP
M38C29FFHP
7
38C2 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
PRELIMINAR
Y
Notice: This is not a final specification.
Some parametric limits are subject to change.
FUNCTIONAL DESCRIPTION
Central Processing Unit (CPU)
The 38C2 group uses the standard 740 Family instruction set. Refer
to the table of 740 Family addressing modes and machine instruc-
tions or the 740 Family Software Manual for details on the instruction
set.
Machine-resident 740 Family instructions are as follows:
The FST and SLW instructions cannot be used.
The STP, WIT, MUL, and DIV instructions can be used.
[Accumulator (A)]
The accumulator is an 8-bit register. Data operations such as data
transfer, etc., are executed mainly through the accumulator.
[Index Register X (X)]
The index register X is an 8-bit register. In the index addressing modes,
the value of the OPERAND is added to the contents of register X and
specifies the real address.
[Index Register Y (Y)]
The index register Y is an 8-bit register. In partial instruction, the
value of the OPERAND is added to the contents of register Y and
specifies the real address.
[Stack Pointer (S)]
The stack pointer is an 8-bit register used during subroutine calls
and interrupts. This register indicates start address of stored area
(stack) for storing registers during subroutine calls and interrupts.
The low-order 8 bits of the stack address are determined by the con-
tents of the stack pointer. The high-order 8 bits of the stack address
are determined by the stack page selection bit. If the stack page
selection bit is "0" , the high-order 8 bits becomes "00
16
". If the stack
page selection bit is "1", the high-order 8 bits becomes "01
16
".
The operations of pushing register contents onto the stack and pop-
ping them from the stack are shown in Figure 6.
Store registers other than those described in Figure 6 with program
when the user needs them during interrupts or subroutine calls.
[Program Counter (PC)]
The program counter is a 16-bit counter consisting of two 8-bit regis-
ters PC
H
and PC
L
. It is used to indicate the address of the next in-
struction to be executed.
Fig. 5 740 Family CPU register structure
A
Accumulator
b7
b7
b7
b7
b0
b7
b15
b0
b7
b0
b0
b0
b0
X
Index register X
Y
Index register Y
S
Stack pointer
PC
L
Program counter
PC
H
N V T B D I Z C
Processor status register (PS)
Carry flag
Zero flag
Interrupt disable flag
Decimal mode flag
Break flag
Index X mode flag
Overflow flag
Negative flag
8
38C2 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
PRELIMINAR
Y
Notice: This is not a final specification.
Some parametric limits are subject to change.
Table 4 Push and pop instructions of accumulator or processor status register
Accumulator
Processor status register
Push instruction to stack
PHA
PHP
Pop instruction from stack
PLA
PLP
Fig. 6 Register push and pop at interrupt generation and subroutine call
N
o
t
e:
C
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1
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E
x
e
c
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e
J
S
R
O
n
-
g
o
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g
R
o
u
t
i
n
e
M
(
S
)
(
P
C
H
)
(
S
)
(
S
)
1
M
(
S
)
(
P
C
L
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9
38C2 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
PRELIMINAR
Y
Notice: This is not a final specification.
Some parametric limits are subject to change.
[Processor Status Register (PS)]
The processor status register is an 8-bit register consisting of 5 flags
which indicate the status of the processor after an arithmetic opera-
tion and 3 flags which decide MCU operation. Branch operations
can be performed by testing the Carry (C) flag , Zero (Z) flag, Over-
flow (V) flag, or the Negative (N) flag. In decimal mode, the Z, V, N
flags are not valid.
Bit 0: Carry flag (C)
The C flag contains a carry or borrow generated by the arithmetic
logic unit (ALU) immediately after an arithmetic operation. It can
also be changed by a shift or rotate instruction.
Bit 1: Zero flag (Z)
The Z flag is set if the result of an immediate arithmetic operation
or a data transfer is "0", and cleared if the result is anything other
than "0".
Bit 2: Interrupt disable flag (I)
The I flag disables all interrupts except for the interrupt generated
by the BRK instruction.
Interrupts are disabled when the I flag is "1".
Bit 3: Decimal mode flag (D)
The D flag determines whether additions and subtractions are ex-
ecuted in binary or decimal. Binary arithmetic is executed when
this flag is "0"; decimal arithmetic is executed when it is "1".
Decimal correction is automatic in decimal mode. Only the ADC
and SBC instructions can be used for decimal arithmetic.
Bit 4: Break flag (B)
The B flag is used to indicate that the current interrupt was gener-
ated by the BRK instruction. The BRK flag in the processor status
register is always "0". When the BRK instruction is used to gener-
ate an interrupt, the processor status register is pushed onto the
stack with the break flag set to "1".
Bit 5: Index X mode flag (T)
When the T flag is "0", arithmetic operations are performed be-
tween accumulator and memory. When the T flag is "1", direct arith-
metic operations and direct data transfers are enabled between
memory locations.
Bit 6: Overflow flag (V)
The V flag is used during the addition or subtraction of one byte of
signed data. It is set if the result exceeds +127 to -128. When the
BIT instruction is executed, bit 6 of the memory location operated
on by the BIT instruction is stored in the overflow flag.
Bit 7: Negative flag (N)
The N flag is set if the result of an arithmetic operation or data
transfer is negative. When the BIT instruction is executed, bit 7 of
the memory location operated on by the BIT instruction is stored in
the negative flag.
Table 5 Set and clear instructions of each bit of processor status register
Set instruction
Clear instruction
C flag
SEC
CLC
Z flag
I flag
SEI
CLI
D flag
SED
CLD
B flag
T flag
SET
CLT
V flag
CLV
N flag
10
38C2 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
PRELIMINAR
Y
Notice: This is not a final specification.
Some parametric limits are subject to change.
[CPU Mode Register (CPUM)] 003B
16
The CPU mode register contains the stack page selection bit and
the control bit for the internal system clock.
The CPU mode register is allocated at address 003B
16
.
Fig. 7 Structure of CPU mode register
Not available
Processor mode bits
b1 b0
0 0 : Single-chip mode
0 1 :
1 0 :
1 1 :
Stack page selection bit
0 : RAM in the zero page is used as stack area
1 : RAM in page 1 is used as stack area
Not used (returns "1" when read)
(Do not write "0" to this bit.)
Main clock (X
IN
X
OUT
) d
ivision ratio selection bits
b5 b4
0 0 : X
IN
/8 (frequency/8 mode)
0 1 : X
IN
/4 (frequency/4 mode)
1 0 : X
IN
/2 (frequency/2 mode)
1 1 : X
IN
(through mode)
System clock control bits
b7 b6
0 0 : X
IN
stop, X
CIN
oscillating, system clock = X
CIN
0 1 : X
IN
oscillating, X
CIN
stop, system clock = X
IN
1 0 : X
IN
oscillating, X
CIN
oscillating, system clock = X
CIN
1 1 : X
IN
oscillating, X
CIN
oscillating, system clock = X
IN
CPU mode register
(CPUM (CM) : address 003B
16
)
b7
b0
11
38C2 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
PRELIMINAR
Y
Notice: This is not a final specification.
Some parametric limits are subject to change.
MEMORY
Special Function Register (SFR) Area
The Special Function Register area in the zero page contains control
registers such as I/O ports and timers.
RAM
RAM is used for data storage and for stack area of subroutine calls
and interrupts.
ROM
The first 128 bytes and the last 2 bytes of ROM are reserved for
device testing and the rest is user area for storing programs.
Interrupt Vector Area
The interrupt vector area contains reset and interrupt vectors.
Zero Page
Access to this area with only 2 bytes is possible in the zero page
addressing mode.
Special Page
Access to this area with only 2 bytes is possible in the special page
addressing mode.
Fig. 8 Memory map diagram
0100
16
0
0
0
0
1
6
0
0
4
0
1
6
0
8
4
0
1
6
F
F
0
0
1
6
F
F
D
C
1
6
F
F
F
E
1
6
F
F
F
F
1
6
1
9
2
2
5
6
3
8
4
5
1
2
6
4
0
7
6
8
8
9
6
1
0
2
4
1
5
3
6
2
0
4
8
XXXX
16
0
0
F
F
1
6
0
1
3
F
1
6
0
1
B
F
1
6
0
2
3
F
1
6
0
2
B
F
1
6
0
3
3
F
1
6
0
3
B
F
1
6
0
4
3
F
1
6
0
6
3
F
1
6
0
8
3
F
1
6
4
0
9
6
8
1
9
2
1
2
2
8
8
1
6
3
8
4
2
0
4
8
0
2
4
5
7
6
2
8
6
7
2
3
2
7
6
8
3
6
8
6
4
4
0
9
6
0
4
5
0
5
6
4
9
1
5
2
5
3
2
4
8
5
7
3
4
4
6
1
4
4
0
F
0
0
0
1
6
E
0
0
0
1
6
D
0
0
0
1
6
C
0
0
0
1
6
B
0
0
0
1
6
A
0
0
0
1
6
9
0
0
0
1
6
8
0
0
0
1
6
7
0
0
0
1
6
6
0
0
0
1
6
5
0
0
0
1
6
4
0
0
0
1
6
3
0
0
0
1
6
2
0
0
0
1
6
1
0
0
0
1
6
F
0
8
0
1
6
E
0
8
0
1
6
D
0
8
0
1
6
C
0
8
0
1
6
B
0
8
0
1
6
A
0
8
0
1
6
9
0
8
0
1
6
8
0
8
0
1
6
7
0
8
0
1
6
6
0
8
0
1
6
5
0
8
0
1
6
4
0
8
0
1
6
3
0
8
0
1
6
2
0
8
0
1
6
1
0
8
0
1
6
Y
Y
Y
Y
1
6
Z
Z
Z
Z
1
6
RAM
ROM
R
A
M
a
r
e
a
R
A
M
s
i
z
e
(
b
y
t
e
s
)
A
d
d
r
e
s
s
X
X
X
X
1
6
ROM area
R
O
M
s
i
z
e
(
b
y
t
e
s
)
Address
YYYY
16
Address
ZZZZ
16
R
e
s
e
r
v
e
d
a
r
e
a
S
F
R
a
r
e
a
N
o
t
u
s
e
d
Interrupt vector area
R
e
s
e
r
v
e
d
R
O
M
a
r
e
a
(
1
2
8
b
y
t
e
s
)
Zero
page
S
p
e
c
i
a
l
p
a
g
e
L
C
D
d
i
s
p
l
a
y
R
A
M
a
r
e
a
R
e
s
e
r
v
e
d
R
O
M
a
r
e
a
S
F
R
a
r
e
a
0
0
4
C
1
6
0
F
E
0
1
6
1
0
00
1
6
12
38C2 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
PRELIMINAR
Y
Notice: This is not a final specification.
Some parametric limits are subject to change.
Fig. 9 Memory map of special function register (SFR)
0FF9
16
0020
16
0021
16
0022
16
0023
16
0024
16
0025
16
0026
16
0027
16
0028
16
0029
16
002A
16
002B
16
002C
16
002D
16
002E
16
002F
16
0030
16
0031
16
0032
16
0033
16
0034
16
0035
16
0036
16
0037
16
0038
16
0039
16
003A
16
003B
16
003C
16
003D
16
003E
16
003F
16
0000
16
0001
16
0002
16
0003
16
0004
16
0005
16
0006
16
0007
16
0008
16
0009
16
000A
16
000B
16
000C
16
000D
16
000E
16
000F
16
0010
16
0011
16
0012
16
0013
16
0014
16
0015
16
0016
16
0017
16
0018
16
0019
16
001A
16
001B
16
001C
16
001D
16
001E
16
001F
16
Port P0 (P0)
Port P0 direction register (P0D)
Port P1 (P1)
Port P1 direction register (P1D)
Port P2 (P2)
Port P2 direction register (P2D)
Port P3 (P3)
Port P4 (P4)
Port P4 direction register (P4D)
Port P5 (P5)
Port P5 direction register (P5D)
Port P6 (P6)
Port P6 direction register (P6D)
A-D control register (ADCON)
A-D conversion register (low-order) (ADL)
A-D conversion register (high-order) (ADH)
Interrupt control register 2 (ICON2)
Interrupt edge selection register (INTEDGE)
CPU mode register (CPUM)
Interrupt request register 1 (IREQ1)
Interrupt request register 2 (IREQ2)
Interrupt control register 1 (ICON1)
Timer 1 (T1)
Timer 3 (T3)
PWM01 register (PWM01)
Timer 12 mode register (T12M)
Timer 2 (T2)
Timer 4 (T4)
Compare register (low-order) (COMPL)
Compare register (high-order) (COMPH)
Timer X (low-order) (TXL)
LCD power control register (VLCON)
LCD mode register (LM)
Timer X (high-order) (TXH)
Timer X (extension) (TXEX)
0FF0
16
0FF1
16
0FF2
16
0FF3
16
0FF4
16
0FF5
16
0FF6
16
0FF7
16
0FE0
16
0FE1
16
0FE2
16
0FE6
16
0FE7
16
0FE9
16
0FE3
16
0FE4
16
0FE5
16
Port P3 direction register (P3D)
Transmit/receive buffer register 1 (TB1/RB1)
Serial I/O1 status register (SIO1STS)
Transmit/receive buffer register 2 (TB2/RB2)
Serial I/O2 status register (SIO2STS)
UART1 control register (UART1CON)
Serial I/O1 control register (SIO1CON)
Serial I/O2 control register (SIO2CON)
Baudrate generator 1 (BRG1)
Baudrate generator 2 (BRG2)
UART2 control register (UART2CON)
0FEA
16
0FEB
16
0FEC
16
0FED
16
0FEE
16
0FEF
16
Clock output control register (CKOUT)
PULL register (PULL)
Timer 34 mode register (T34M)
Timer Y (low-order) (TYL)
Timer Y (high-order) (TYH)
Timer X mode register (TXM)
Timer Y mode register (TYM)
Watchdog timer control register (WDTCON)
0FF8
16
0FFA
16
0FFB
16
0FFC
16
0FFD
16
0FFE
16
0FFF
16
Oscillation output control register (OSCOUT)
Key input control register (KIC)
Timer 1234 mode register (T1234M)
Timer X control register (TXCON)
Timer 12 frequency division selection register (PRE12)
Timer 34 frequency division selection register (PRE34)
Timer XY frequency division selection register (PREXY)
Segment output disable register 0 (SEG0)
Segment output disable register 1 (SEG1)
Segment output disable register 2 (SEG2)
Timer Y mode register 2 (TYM2)
Flash memory control register (FMCR)
Reserved area
0FE8
16
13
38C2 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
PRELIMINAR
Y
Notice: This is not a final specification.
Some parametric limits are subject to change.
I/O PORTS
Direction Registers
The I/O ports P0P6 have direction registers which determine the
input/output direction of each individual pin. Each bit in a direction
register corresponds to one pin, each pin can be set to be input port
or output port.
When "0" is written to the bit of the direction register, the correspond-
ing pin becomes an input pin. As for ports P0P2, when "1" is written
to the bit of the direction register and the segment output disable
register, the corresponding pin becomes an output pin. As for ports
P3P6, when "1" is written to the bit of the direction register, the
corresponding pin becomes an output pin.
If data is read from a pin set to output, the value of the port output
latch is read, not the value of the pin itself. Pins set to input are float-
ing. If a pin set to input is written to, only the port output latch is
written to and the pin remains floating.
Pull-up Control
Each individual bit of ports P0P2 can be pulled up with a program
by setting direction registers and segment output disable registers 0
to 2 (addresses 0FF8
16
to 0FFA
16
).
The pin is pulled up by setting "0" to the direction register and "1" to
the segment output disable register.
By setting the PULL register (address 0FF1
16
), ports P3P6 can con-
trol pull-up with a program.
However, the contents of PULL register do not affect ports pro-
grammed as the output ports.
Fig. 11 Structure of PULL register and segment output disable register
Fig. 10 Structure of ports P0 to P2
S
e
g
m
e
n
t
o
u
t
p
u
t
d
i
s
a
b
l
e
r
e
g
i
s
t
e
r
D
i
r
e
c
t
i
o
n
r
e
g
i
s
t
e
r
"
0
"
"
1
"
"
0
"
"
1
"
I
n
p
u
t
p
o
r
t
N
o
p
u
l
l
-
u
p
S
e
g
m
e
n
t
o
u
t
p
u
t
P
o
r
t
o
u
t
p
u
t
I
n
p
u
t
p
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r
t
P
u
l
l
-
u
p
I
n
i
t
i
a
l
s
t
a
t
e
P3
0
P3
3
pull-up
P3
4
P3
7
pull-up
P4
0
P4
3
pull-up
P4
4
P4
7
pull-up
P5
0
P5
3
pull-up
P5
4
P5
7
pull-up
P6
0
P6
2
pull-up
Not used (return "0" when read)
PULL register
(PULL : address 0FF1
16
)
b7
b0
P0
0
pull-up
P0
1
pull-up
P0
2
pull-up
P0
3
pull-up
P0
4
pull-up
P0
5
pull-up
P0
6
pull-up
P0
7
pull-up
Segment output disable register 0
(SEG0 : address 0FF8
16
)
b7
b0
Note: The PULL register and segment output disable register
affect only ports programmed as the input ports.
0: No pull-up
1: Pull-up
P1
0
pull-up
P1
1
pull-up
P1
2
pull-up
P1
3
pull-up
P1
4
pull-up
P1
5
pull-up
P1
6
pull-up
P1
7
pull-up
b7
b0
Segment output disable register 1
(SEG1 : address 0FF9
16
)
P2
0
pull-up
P2
1
pull-up
P2
2
pull-up
P2
3
pull-up
P2
4
pull-up
P2
5
pull-up
P2
6
pull-up
P2
7
pull-up
b7
b0
Segment output disable register 2
(SEG2 : address 0FFA
16
)
0: No pull-up
1: Pull-up
14
38C2 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
PRELIMINAR
Y
Notice: This is not a final specification.
Some parametric limits are subject to change.
Name
Port P0
Port P1
Port P2
Port P3
Port P4
Port P5
Port P6
Common
Input/Output
Input/Output,
individual bits
Input/Output,
individual bits
Input/Output,
individual bits
Input/Output,
individual bits
Input/Output,
individual bits
Input/Output,
individual bits
Input/Output,
individual bits
Output
I/O format
CMOS compatible
input level
CMOS 3-state output
CMOS compatible
input level
CMOS 3-state output
CMOS compatible
input level
CMOS 3-state output
CMOS compatible
input level
CMOS 3-state output
CMOS compatible
input level
CMOS 3-state output
CMOS compatible
input level
CMOS 3-state output
CMOS compatible
input level
CMOS 3-state output
LCD common output
Non-port function
LCD segment
output
Serial I/O2 function I/O
External interrupt input
Timer X output
Timer 2 output
Timer X function input
A-D conversion
input
External interrupt input
Timer 3 output
Timer 4 output
PWM output
Serial I/O1
function I/O
Timer Y function input
Sub-clock oscillation circuit
Related SFRs
Segment output disable
register 1
Segment output disable
register 2
Segment output disable
register 3
PULL register
Serial I/O2 control register
Serial I/O2 status register
UART2 control register
PULL register
Interrupt edge selection
register
PULL register
Timer X mode register
Timer 12 mode register
PULL register
Timer X mode register
PULL register
A-D control register
PULL register
A-D control register
Timer Y mode register
PULL register
Interrupt edge selection
register
PULL register
Timer 12 mode register
PULL register
Serial I/O1 control register
Serial I/O1 status register
UART1 control register
PULL register
Timer Y mode register
PULL register
CPU mode register
LCD mode register
Ref. No.
(1)
(2)
(3)
(4)
(5)
(6)
(7)
(8)
(9)
(7)
(11)
(10)
(11)
(7)
(9)
(12)
(13)
(14)
(15)
(7)
(16)
(17)
(18)
Table 6 List of I/O port function
Notes 1: For details of how to use double/triple function ports as function I/O ports, refer to the applicable sections.
2: Make sure that the input level at each pin is either 0 V or V
CC
during execution of the STP instruction.
When an input level is at an intermediate potential, a current will flow from V
CC
to V
SS
through the input-stage gate.
P0
0
/SEG
0
P0
3
/SEG
3
P0
4
/SEG
4
P0
7
/SEG
7
P1
0
/SEG
8
P1
7
/SEG
15
P2
0
/SEG
16
P2
5
/SEG
21
P2
6
/SEG
22
/V
L1
P2
7
/SEG
23
/V
L2
P3
0
/S
RDY2
P3
1
/S
CLK2
P3
2
/TxD
2
P3
3
/RxD
2
P3
4
/INT
2
P3
5
/T
XOUT
P3
6
/T
2OUT
/
P3
7
/CNTR
0
P4
0
/O
OUT0
/AN
0
P4
1
/O
OUT1
/AN
1
P4
2
/AN
2
P4
5
/AN
5
P4
6
/RTP
0
/AN
6
P4
7
/RTP
1
/AN
7
P5
0
/INT
0
P5
1
/INT
1
P5
2
/T
3OUT
/PWM
0
P5
3
/T
4OUT
/PWM
1
P5
4
/RxD
1
P5
5
/TxD
1
P5
6
/S
CLK1
P5
7
/S
RDY1
P6
0
/CNTR
1
P6
1
/X
CIN
P6
2
/X
COUT
COM
0
COM
3
Pin
Key input
(key-on wakeup)
interrupt input
LCD power
input
Oscillation
external
output
Real time
port function
output
Key input
(key-on wakeup)
interrupt input
15
38C2 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
PRELIMINAR
Y
Notice: This is not a final specification.
Some parametric limits are subject to change.
Fig. 12 Port block diagram (1)
(
1
)
P
o
r
t
s
P
0
0
P
0
3
(3) Port P3
0
Data bus
Serial I/O output
P
o
r
t
l
a
t
c
h
P
u
l
l
-
u
p
c
o
n
t
r
o
l
Serial I/O ready output
Data bus
P
o
r
t
l
a
t
c
h
D
i
r
e
c
t
i
o
n
r
e
g
i
s
t
e
r
P
u
l
l
-
u
p
c
o
n
t
r
o
l
P
u
l
l
-
u
p
c
o
n
t
r
o
l
Direction register
Data bus
S
e
r
i
a
l
I
/
O
i
n
p
u
t
P
o
r
t
l
a
t
c
h
Data bus
S
e
r
i
a
l
I
/
O
c
l
o
c
k
o
u
t
p
u
t
S
e
r
i
a
l
I
/
O
c
l
o
c
k
i
n
p
u
t
Serial I/O mode selection bit
Serial I/O enable bit
Port latch
Direction register
P
u
l
l
-
u
p
c
o
n
t
r
o
l
S
e
g
m
e
n
t
o
u
t
p
u
t
d
i
s
a
b
l
e
b
i
t
D
a
t
a
b
u
s
P
o
r
t
l
a
t
c
h
V
L
2
/
V
L
3
V
L
1
/
V
S
S
K
e
y
i
n
p
u
t
c
o
n
t
r
o
l
K
e
y
-
o
n
w
a
k
e
u
p
i
n
t
e
r
r
u
p
t
i
n
p
u
t
S
e
g
m
e
n
t
d
a
t
a
S
e
g
m
e
n
t
o
u
t
p
u
t
d
i
s
a
b
l
e
b
i
t
D
i
r
e
c
t
i
o
n
r
e
g
i
s
t
e
r
D
a
t
a
b
u
s
P
o
r
t
l
a
t
c
h
L
C
D
p
o
w
e
r
i
n
p
u
t
(
V
L
1
,
V
L
2
)
o
n
l
y
f
o
r
P
2
6
,
P
2
7
V
L
2
/
V
L
3
V
L
1
/
V
S
S
S
e
g
m
e
n
t
d
a
t
a
S
e
g
m
e
n
t
o
u
t
p
u
t
d
i
s
a
b
l
e
b
i
t
Segment output disable bit
(
2
)
P
o
r
t
s
P
0
4
P
0
7
,
P
1
,
P
2
D
i
r
e
c
t
i
o
n
r
e
g
i
s
t
e
r
Serial I/O mode selection bit
Serial I/O enable bit
S
RDY
output enable bit
(5) Port P3
2
P
3
2
/
T
x
D
2
P
-
c
h
a
n
n
e
l
o
u
t
p
u
t
d
i
s
a
b
l
e
b
i
t
S
e
r
i
a
l
I
/
O
e
n
a
b
l
e
b
i
t
T
r
a
n
s
m
i
t
e
n
a
b
l
e
b
i
t
(6) Port P3
3
S
e
r
i
a
l
I
/
O
e
n
a
b
l
e
b
i
t
R
e
c
e
i
v
e
e
n
a
b
l
e
b
i
t
(
4
)
P
o
r
t
P
3
1
Serial I/O synchronous
clock selection bit
Serial I/O enable bit
D
i
r
e
c
t
i
o
n
r
e
g
i
s
t
e
r
16
38C2 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
PRELIMINAR
Y
Notice: This is not a final specification.
Some parametric limits are subject to change.
Fig. 13 Port block diagram (2)
A
n
a
l
o
g
i
n
p
u
t
p
i
n
s
e
l
e
c
t
i
o
n
b
i
t
A-D conversion input
D
a
t
a
b
u
s
P
o
r
t
l
a
t
c
h
D
i
r
e
c
t
i
o
n
r
e
g
i
s
t
e
r
Pull-up control
Data bus
Serial I/O clock output
Port latch
Direction register
Pull-up control
Serial I/O clock input
K
e
y
-
o
n
w
a
k
e
u
p
i
n
t
e
r
r
u
p
t
i
n
p
u
t
K
e
y
i
n
p
u
t
c
o
n
t
r
o
l
Data bus
Direction register
Port latch
P
u
l
l
-
u
p
c
o
n
t
r
o
l
Port latch
Data bus
P
u
l
s
e
o
u
t
p
u
t
m
o
d
e
T
i
m
e
r
X
o
u
t
p
u
t
D
i
r
e
c
t
i
o
n
r
e
g
i
s
t
e
r
Pull-up control
Direction register
D
a
t
a
b
u
s
Serial I/O enable bit
Receive enable bit
Port latch
Pull-up control
Serial I/O input
Key-on wakeup interrupt input
K
e
y
i
n
p
u
t
c
o
n
t
r
o
l
P
o
r
t
l
a
t
c
h
D
a
t
a
b
u
s
D
i
r
e
c
t
i
o
n
r
e
g
i
s
t
e
r
P
u
l
l
-
u
p
c
o
n
t
r
o
l
Data bus
P
o
r
t
l
a
t
c
h
Direction register
Pull-up control
Analog input pin selection bit
A
-
D
c
o
n
v
e
r
s
i
o
n
i
n
p
u
t
D
a
t
a
b
u
s
S
e
r
i
a
l
I
/
O
o
u
t
p
u
t
Port latch
Direction register
Pull-up control
K
e
y
-
o
n
w
a
k
e
u
p
i
n
t
e
r
r
u
p
t
i
n
p
u
t
K
e
y
i
n
p
u
t
c
o
n
t
r
o
l
(
7
)
P
o
r
t
s
P
3
4
,
P
3
7
,
P
5
0
,
P
5
1
,
P
6
0
(
9
)
P
o
r
t
s
P
3
6
,
P
5
2
,
P
5
3
(
1
1
)
P
o
r
t
s
P
4
0
,
P
4
1
,
P
4
6
,
P
4
7
(
1
3
)
P
o
r
t
P
5
5
(14) Port P5
6
(12) Port P5
4
(8) Port P3
5
(10) Ports P4
2
P4
5
C
N
T
R
0
,
C
N
T
R
1
i
n
t
e
r
r
u
p
t
i
n
p
u
t
I
N
T
0
I
N
T
2
i
n
t
e
r
r
u
p
t
i
n
p
u
t
P
o
r
t
/
T
i
m
e
r
o
u
t
p
u
t
s
e
l
e
c
t
i
o
n
T
i
m
e
r
o
u
t
p
u
t
/
P
W
M
o
u
t
p
u
t
T
i
m
e
r
o
u
t
p
u
t
/
S
y
s
t
e
m
c
l
o
c
k
o
u
t
p
u
t
O
s
c
i
l
l
a
t
i
o
n
o
u
t
p
u
t
c
o
n
t
r
o
l
b
i
t
/
R
e
a
l
t
i
m
e
c
o
n
t
r
o
l
b
i
t
O
s
c
i
l
l
a
t
i
o
n
o
u
t
p
u
t
/
D
a
t
a
f
o
r
r
e
a
l
t
i
m
e
p
o
r
t
S
e
r
i
a
l
I
/
O
e
n
a
b
l
e
b
i
t
T
r
a
n
s
m
i
t
e
n
a
b
l
e
b
i
t
S
e
r
i
a
l
I
/
O
s
y
n
c
h
r
o
n
o
u
s
c
l
o
c
k
s
e
l
e
c
t
i
o
n
b
i
t
S
e
r
i
a
l
I
/
O
e
n
a
b
l
e
b
i
t
S
e
r
i
a
l
I
/
O
m
o
d
e
s
e
l
e
c
t
i
o
n
b
i
t
S
e
r
i
a
l
I
/
O
e
n
a
b
l
e
b
i
t
P
5
5
/
T
x
D
1
P
-
c
h
a
n
n
e
l
o
u
t
p
u
t
d
i
s
a
b
l
e
b
i
t
17
38C2 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
PRELIMINAR
Y
Notice: This is not a final specification.
Some parametric limits are subject to change.
Fig. 14 Port block diagram (3)
V
L3
V
L2
V
L1
V
SS
(
1
5
)
P
o
r
t
P
5
7
S
e
r
i
a
l
I
/
O
r
e
a
d
y
o
u
t
p
u
t
Data bus
P
o
r
t
l
a
t
c
h
D
i
r
e
c
t
i
o
n
r
e
g
i
s
t
e
r
P
u
l
l
-
u
p
c
o
n
t
r
o
l
K
e
y
-
o
n
w
a
k
e
u
p
i
n
t
e
r
r
u
p
t
i
n
p
u
t
Key input control
X
c
o
s
c
i
l
l
a
t
i
o
n
e
n
a
b
l
e
d
Port P6
1
Oscillator
Xc oscillation enabled
(17) Port P6
2
D
a
t
a
b
u
s
P
o
r
t
l
a
t
c
h
D
i
r
e
c
t
i
o
n
r
e
g
i
s
t
e
r
X
c
o
s
c
i
l
l
a
t
i
o
n
e
n
a
b
l
e
d
+
P
u
l
l
-
u
p
c
o
n
t
r
o
l
(
1
7
)
C
O
M
0
C
O
M
3
(
1
6
)
P
o
r
t
P
6
1
Data bus
Port latch
Direction register
X
c
o
s
c
i
l
l
a
t
i
o
n
e
n
a
b
l
e
d
Xc oscillation enabled + Pull-up control
Sub-clock generation circuit input
S
e
r
i
a
l
I
/
O
m
o
d
e
s
e
l
e
c
t
i
o
n
b
i
t
S
e
r
i
a
l
I
/
O
e
n
a
b
l
e
b
i
t
S
R
D
Y
o
u
t
p
u
t
e
n
a
b
l
e
b
i
t
Gate input signal of
each gate depends
on the duty ratio
and bias values.
18
38C2 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
PRELIMINAR
Y
Notice: This is not a final specification.
Some parametric limits are subject to change.
INTERRUPTS
Interrupts occur by nineteen sources: six external, twelve internal,
and one software.
Interrupt Control
Each interrupt except the BRK instruction interrupt have both an in-
terrupt request bit and an interrupt enable bit, and is controlled by the
interrupt disable flag. An interrupt occurs if the corresponding inter-
rupt request and enable bits are "1" and the interrupt disable flag is
"0".
Interrupt enable bits can be set or cleared by software. Interrupt re-
quest bits can be cleared by software, but cannot be set by software.
The BRK instruction interrupt and reset cannot be disabled with any
flag or bit. The I flag disables all interrupts except the BRK instruction
interrupt and reset. If several interrupts requests occurs at the same
time the interrupt with highest priority is accepted first.
Interrupt Operation
By acceptance of an interrupt, the following operations are automati-
cally performed:
1. The processing being executed is stopped.
2. The contents of the program counter and processor status reg-
ister are automatically pushed onto the stack.
3. The interrupt disable flag is set and the corresponding interrupt
request bit is cleared.
4. The interrupt jump destination address is read from the vector
table into the program counter.
s
Notes on Interrupts
When the active edge of an external interrupt (INT
0
INT
2
, CNTR
0
or CNTR
1
) is set or an interrupt source where several interrupt source
is assigned to the same vector address is switched, the correspond-
ing interrupt request bit may also be set. Therefore, take following
sequence:
(1) Disable the interrupt.
(2) Set the interrupt edge selection register (Timer X control reg-
ister for CNTR
0
, Timer Y mode register for CNTR
1
).
(3) Clear the set interrupt request bit to "0."
(4) Enable the interrupt.
Interrupt Source
Reset (Note 2)
INT
0
INT
1
INT
2
Key input
(key-on wakeup)
Serial I/O1 receive
Serial I/O1 transmit
Serial I/O2 receive
Serial I/O2 transmit
Timer X
Timer 1
Timer 2
Timer 3
Timer 4
CNTR
0
Timer Y
CNTR
1
A-D conversion
BRK instruction
Priority
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
Vector Addresses (Note 1)
High
FFFD
16
FFFB
16
FFF9
16
FFF7
16
FFF5
16
FFF3
16
FFF1
16
FFEF
16
FFED
16
FFEB
16
FFE9
16
FFE7
16
FFE5
16
FFE3
16
FFE1
16
FFDF
16
FFDD
16
Interrupt Request
Generating Conditions
At reset
At detection of either rising or falling
edge of INT
0
input
At detection of either rising or falling
edge of INT
1
input
At detection of either rising or falling
edge of INT
2
input
At falling of ports P0
0
P0
3
, P5
4
P5
7
input logical level AND
At completion of serial I/O1 data receive
At completion of serial I/O1 transmit
shift or transmit buffer is empty
At completion of serial I/O2 data receive
At completion of serial I/O2 transmit
shift or transmit buffer is empty
At timer X underflow
At timer 1 underflow
At timer 2 underflow
At timer 3 underflow
At timer 4 underflow
At detection of either rising or falling
edge of CNTR
0
input
At timer Y underflow
At detection of either rising or falling
edge of CNTR
1
input
At completion of A-D conversion
At BRK instruction execution
Non-maskable
External interrupt (active edge selectable)
External interrupt (active edge selectable)
Valid when INT
2
interrupt is selected
External interrupt (active edge selectable)
Valid when key input interrupt is selected
External interrupt (falling valid)
Valid only when serial I/O1 is selected
Valid only when serial I/O1 is selected
Valid only when serial I/O2 is selected
Valid only when serial I/O2 is selected
Valid only when timer 1 interrupt is selected
Valid only when timer 2 interrupt is selected
External interrupt (active edge selectable)
External interrupt (active edge selectable)
Valid when A-D conversion interrupt is se-
lected
Non-maskable software interrupt
Low
FFFC
16
FFFA
16
FFF8
16
FFF6
16
FFF4
16
FFF2
16
FFF0
16
FFEE
16
FFEC
16
FFEA
16
FFE8
16
FFE6
16
FFE4
16
FFE2
16
FFE0
16
FFDE
16
FFDC
16
Notes 1: Vector addresses contain interrupt jump destination addresses.
2: Reset function in the same way as an interrupt with the highest priority.
Table 7 Interrupt vector addresses and priority
Remarks
19
38C2 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
PRELIMINAR
Y
Notice: This is not a final specification.
Some parametric limits are subject to change.
Fig. 15 Interrupt control
Fig. 16 Structure of interrupt-related registers
Interrupt request bit
Interrupt enable bit
Interrupt disable flag (I)
BRK instruction
Reset
Interrupt request
b7
b0
Interrupt edge selection register
INT
0
interrupt edge selection bit
INT
1
interrupt edge selection bit
INT
2
interrupt edge selection bit
INT
2
/Key input interrupt switch bit
Timer Y/CNTR
1
interrupt switch bit
Not used (return "0" when read)
(Do not write to "1")
(INTEDGE : address 003A
16
)
Interrupt request register 1
INT
0
interrupt request bit
INT
1
interrupt request bit
INT
2
interrupt request bit
Key input interrupt request bit
Serial I/O1 receive interrupt request bit
Serial I/O1 transmit interrupt request bit
Serial I/O2 receive interrupt request bit
Serial I/O2 transmit interrupt request bit
Timer X interrupt request bit
Interrupt control register 1
INT
0
interrupt enable bit
INT
1
interrupt enable bit
INT
2
interrupt enable bit
Key input interrupt enable bit
Serial I/O1 receive interrupt enable bit
Serial I/O1 transmit interrupt enable bit
Serial I/O2 receive interrupt enable bit
Serial I/O2 transmit interrupt enable bit
Timer X interrupt enable bit
0 : No interrupt request issued
1 : Interrupt request issued
(IREQ1 : address 003C
16
)
(ICON1 : address 003E
16
)
Interrupt request register 2
Timer 1 interrupt request bit
Timer 2 interrupt request bit
Timer 3 interrupt request bit
Timer 4 interrupt request bit
CNTR
0
interrupt request bit
Timer Y interrupt request bit
CNTR
1
interrupt request bit
AD conversion interrupt request bit
Not used (returns "0" when read)
(IREQ2 : address 003D
16
)
Interrupt control register 2
Timer 1 interrupt enable bit
Timer 2 interrupt enable bit
Timer 3 interrupt enable bit
Timer 4 interrupt enable bit
CNTR
0
interrupt enable bit
Timer Y interrupt enable bit
CNTR
1
interrupt enable bit
AD conversion interrupt enable bit
Not used (returns "0" when read)
(Do not write to "1".)
0 : Interrupts disabled
1 : Interrupts enabled
(ICON2 : address 003F
16
)
0 : Falling edge active
1 : Rising edge active
b7
b0
b7
b0
b7
b0
b7
b0
0 : INT
2
interrupt
1 : Key input interrupt
0 : Timer Y interrupt
1 : CNTR
1
interrupt
20
38C2 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
PRELIMINAR
Y
Notice: This is not a final specification.
Some parametric limits are subject to change.
Key Input Interrupt (Key-on Wake-Up)
A key input interrupt request is generated by detecting the falling
edge from any pin of ports P0
0
P0
3
, P5
4
P5
7
that have been set to
input mode. In other words, it is generated when AND of input level
goes from "1" to "0". An example of using a key input interrupt is
shown in Figure 17, where an interrupt request is generated by press-
ing one of the keys consisted as an active-low key matrix which in-
puts to ports P5
4
P5
7
.
Fig. 17 Connection example when using key input interrupt and ports P0 and P5 block diagram
Key input control
register = "1"
K
e
y
i
n
p
u
t
c
o
n
t
r
o
l
r
e
g
i
s
t
e
r
=
"
1
"
K
e
y
i
n
p
u
t
c
o
n
t
r
o
l
r
e
g
i
s
t
e
r
=
"
1
"
Key input control
register = "1"
Key input control
register = "1"
Key input control
register = "1"
Key input control
register = "1"
Port P5
4
latch
Port P5
4
direction register = "0"
Port P5
5
latch
P
o
r
t
P
5
5
d
i
r
e
c
t
i
o
n
r
e
g
i
s
t
e
r
=
"
0
"
Port P5
6
latch
Port P5
6
direction register = "0"
Port P5
7
latch
P
o
r
t
P
5
7
d
i
r
e
c
t
i
o
n
r
e
g
i
s
t
e
r
=
"
0
"
P
o
r
t
P
0
0
l
a
t
c
h
Port P0
0
direction register = "1"
Port P0
1
latch
Port P0
1
direction register = "1"
Port P0
2
latch
P
o
r
t
P
0
2
d
i
r
e
c
t
i
o
n
r
e
g
i
s
t
e
r
=
"
1
"
P
o
r
t
P
0
3
l
a
t
c
h
Port P0
3
direction register = "1"
P
5
4
i
n
p
u
t
P
5
5
i
n
p
u
t
P5
6
input
P
5
7
i
n
p
u
t
P
0
0
o
u
t
p
u
t
P
0
1
o
u
t
p
u
t
P
0
2
o
u
t
p
u
t
P
0
3
o
u
t
p
u
t
PULL register
Bit 5 = "1"
P
o
r
t
P
0
I
n
p
u
t
r
e
a
d
i
n
g
c
i
r
c
u
i
t
P
o
r
t
P
X
x
"
L
"
l
e
v
e
l
o
u
t
p
u
t
K
e
y
i
n
p
u
t
i
n
t
e
r
r
u
p
t
r
e
q
u
e
s
t
P
o
r
t
P
5
I
n
p
u
t
r
e
a
d
i
n
g
c
i
r
c
u
i
t
Key input control
register = "1"
Segment output
disable register 1
Bit 3 = "1"
S
e
g
m
e
n
t
o
u
t
p
u
t
d
i
s
a
b
l
e
r
e
g
i
s
t
e
r
1
B
i
t
2
=
"
1
"
Segment output
disable register 1
Bit 1 = "1"
Segment output
disable register 1
Bit 0 = "1"
P-channel transistor for pull-up
CMOS output buffer
21
38C2 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
PRELIMINAR
Y
Notice: This is not a final specification.
Some parametric limits are subject to change.
A key input interrupt is controlled by the key input control register and
port direction registers. When the key input interrupt is enabled, set
"1" to the key input control register. A key input of any pin of ports
P0
0
P0
3
, P5
4
P5
7
that have been set to input mode is accepted.
Fig. 18 Structure of key input control register
Key input control register
P5
4
key input control bit
P5
5
key input control bit
P5
6
key input control bit
P5
7
key input control bit
P0
0
key input control bit
P0
1
key input control bit
P0
2
key input control bit
P0
3
key input control bit
(KIC : address 0FF2
16
)
b7
b0
0 : Key input interrupt disabled
1 : Key input interrupt enabled
22
38C2 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
PRELIMINAR
Y
Notice: This is not a final specification.
Some parametric limits are subject to change.
TIMERS
8-Bit Timer
The 38C2 group has four built-in timers : Timer 1, Timer 2, Timer 3,
and Timer 4.
Each timer has the 8-bit timer latch. All timers are down-counters.
When the timer reaches "00
16
," the contents of the timer latch is
reloaded into the timer with the next count pulse. In this mode, the
interrupt request bit corresponding to that timer is set to "1."
The count can be stopped by setting the stop bit of each timer to "1."
q
Frequency Divider For Timer
Timer 1, timer 2, timer 3 and timer 4 have the frequency divider for
the count source. The count source of the frequency divider is switched
to X
IN
or X
CIN
by the CPU mode register. The frequency divider is
controlled by the 3-bit register. The division ratio can be selected
from as follows;
1/1, 1/2, 1/16, 1/32, 1/64, 1/128, 1/256, 1/1024 of f(X
IN
) or f(X
CIN
).
q
Timer 1, Timer 2
The count sources of timer 1 and timer 2 can be selected by setting
the timer 12 mode register.
When f(X
CIN
) is selected as the count source, counting can be per-
formed regardless of X
CIN
oscillation. However, when X
CIN
is stopped,
the external pulse input from X
CIN
pin is counted. Also, by the timer
12 mode register, each time timer 2 underflows,
the signal of which
polarity is inverted can be output from P3
6
/T
2OUT
pin.
At reset, all bits of the timer 12 mode register are cleared to "0," timer
1 is set to "FF
16
," and timer 2 is set to "01
16
."
When executing the STP instruction, previously set the wait time at
return.
q
Timer 3, Timer 4
The count sources of timer 3 and timer 4 can be selected by setting
the timer 34 mode register. Also, by the timer 34 mode register, each
time timer 3 or timer 4 underflows,
the signal of which polarity is
inverted can be output from P5
2
/T
3OUT
pin or P5
3
/T
4OUT
pin.
q
Timer 3 PWM
0
Mode, Timer 4 PWM
1
Mode
A PWM rectangular waveform corresponding to the 10-bit accuracy
can be output from the P5
2
/PWM
0
pin and P5
3
/PWM
1
pin by set-
ting the timer 34 mode register and PWM01 register (refer to Figure
21).
The "n" is the value set in the timer 3 (address 0022
16
) or the timer
4 (address 0023
16
). The "ts" is one period of timer 3 or timer 4
count source.
One output pulse is the short interval. Four output pulses are the
long interval. "H" width of the short interval is obtained by n
ts.
However, in the long interval, "H" width of output pulse is extended
for ts which is set by the PWM01 register (address 0024
16
).
23
38C2 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
PRELIMINAR
Y
Notice: This is not a final specification.
Some parametric limits are subject to change.
Timer 12 mode register
(T12M: address 0025
16
)
Timer 1 count stop bit
0 : Count operation
1 : Count stop
Timer 2 count stop bit
0 : Count operation
1 : Count stop
Timer 1 count source selection bits
b3 b2
0 0 : Frequency divider for Timer 1
0 1 : f(X
CIN
)
1 0 : Underflow of Timer Y
1 1 : Not available
Timer 2 count source selection bits
b5 b4
0 0 : Underflow of Timer 1
0 1 : f(X
CIN
)
1 0 : Frequency divider for Timer 2
1 1 : Not available
Timer 2 output selection bit (P3
6
)
0 : I/O port
1 : Timer 2 output
T
2OUT
output edge switch bit
0 : Start at "L" output
1 : Start at "H" output
Timer 34 mode register
(T34M: address 0026
16
)
Timer 3 count stop bit
0 : Count operation
1 : Count stop
Timer 4 count stop bit
0 : Count operation
1 : Count stop
Timer 3 count source selection bit
0 : Frequency divider for Timer 3
1 : Underflow of Timer 2
Timer 4 count source selection bits
b4 b3
0 0 : Frequency divider for Timer 4
0 1 : Underflow of Timer 3
1 0 : Underflow of Timer 2
1 1 : Not available
Timer 3 operating mode selection bit
0 : Timer mode
1 : PWM mode
Timer 4 operating mode selection bit
0 : Timer mode
1 : PWM mode
Not used (returns "0" when read)
Timer 1234 mode register
(T1234M: address 0FF3
16
)
T
3OUT
output edge switch bit
0 : Start at "L" output
1 : Start at "H" output
T
4OUT
output edge switch bit
0 : Start at "L" output
1 : Start at "H" output
Timer 3 output selection bit (P5
2
)
0 : I/O port
1 : Timer 3 output
Timer 4 output selection bit (P5
3
)
0 : I/O port
1 : Timer 4 output
Timer 2 write control bit
0 : Write data to both timer latch and timer
1 : Write data to timer latch only
Timer 3 write control bit
0 : Write data to both timer latch and timer
1 : Write data to timer latch only
Timer 4 write control bit
0 : Write data to both timer latch and timer
1 : Write data to timer latch only
Not used (returns "0" when read)
b7
b0
b7
b0
b7
b0
PWM01 register
(PWM01: address 0024
16
)
PWM0 set bits
b1 b0
0 0 : No extended
0 1 : Extended once in four periods
1 0 : Extended twice in four periods
1 1 : Extended three times in four periods
PWM1 set bits
b3 b2
0 0 : No extended
0 1 : Extended once in four periods
1 0 : Extended twice in four periods
1 1 : Extended three times in four periods
Not used (returns "0" when read)
Timer 12 frequency division selection register
(PRE12: address 0FF5
16
)
Timer 1 frequency division selection bits
b2 b1 b0
0 0
0 : 1/16
f(X
IN
) or 1/16
f(X
CIN
)
0 0
1 : 1/1
f(X
IN
) or 1/1
f(X
CIN
)
0 1
0 : 1/2
f(X
IN
) or 1/2
f(X
CIN
)
0 1
1 : 1/32
f(X
IN
) or 1/32
f(X
CIN
)
1 0
0 : 1/64
f(X
IN
) or 1/64
f(X
CIN
)
1 0
1 : 1/128
f(X
IN
) or 1/128
f(X
CIN
)
1 1
0 : 1/256
f(X
IN
) or 1/256
f(X
CIN
)
1 1
1 : 1/1024
f(X
IN
) or 1/1024
f(X
CIN
)
Timer 2 frequency division selection bits
b5 b4 b3
0 0 0 : 1/16
f(X
IN
) or 1/16
f(X
CIN
)
0 0 1 : 1/1
f(X
IN
) or 1/1
f(X
CIN
)
0 1 0 : 1/2
f(X
IN
) or 1/2
f(X
CIN
)
0 1 1 : 1/32
f(X
IN
) or 1/32
f(X
CIN
)
1 0 0 : 1/64
f(X
IN
) or 1/64
f(X
CIN
)
1 0 1 : 1/128
f(X
IN
) or 1/128
f(X
CIN
)
1 1 0 : 1/256
f(X
IN
) or 1/256
f(X
CIN
)
1 1 1 : 1/1024
f(X
IN
) or 1/1024
f(X
CIN
)
Not used (returns "0" when read)
b7
b0
b7
b0
Timer 34 frequency division selection register
(PRE34: address 0FF6
16
)
Timer 3 frequency division selection bits
b2 b1 b0
0 0 0 : 1/16
f(X
IN
) or 1/16
f(X
CIN
)
0 0 1 : 1/1
f(X
IN
) or 1/1
f(X
CIN
)
0 1 0 : 1/2
f(X
IN
) or 1/2
f(X
CIN
)
0 1 1 : 1/32
f(X
IN
) or 1/32
f(X
CIN
)
1 0 0 : 1/64
f(X
IN
) or 1/64
f(X
CIN
)
1 0 1 : 1/128
f(X
IN
) or 1/128
f(X
CIN
)
1 1 0 : 1/256
f(X
IN
) or 1/256
f(X
CIN
)
1 1 1 : 1/1024
f(X
IN
) or 1/1024
f(X
CIN
)
Timer 4 frequency division selection bits
b5 b4 b3
0 0 0 : 1/16
f(X
IN
) or 1/16
f(X
CIN
)
0 0 1 : 1/1
f(X
IN
) or 1/1
f(X
CIN
)
0 1 0 : 1/2
f(X
IN
) or 1/2
f(X
CIN
)
0 1 1 : 1/32
f(X
IN
) or 1/32
f(X
CIN
)
1 0 0 : 1/64
f(X
IN
) or 1/64
f(X
CIN
)
1 0 1 : 1/128
f(X
IN
) or 1/128
f(X
CIN
)
1 1 0 : 1/256
f(X
IN
) or 1/256
f(X
CIN
)
1 1 1 : 1/1024
f(X
IN
) or 1/1024
f(X
CIN
)
Not used (returns "0" when read)
b7
b0
Fig. 19 Structure of timer related register
24
38C2 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
PRELIMINAR
Y
Notice: This is not a final specification.
Some parametric limits are subject to change.
Fig. 20 Block diagram of timers 1, 2, 3 and 4
Timer 1 latch (8)
T
i
m
e
r
1
(
8
)
T
i
m
e
r
1
i
n
t
e
r
r
u
p
t
r
e
q
u
e
s
t
T
i
m
e
r
2
i
n
t
e
r
r
u
p
t
r
e
q
u
e
s
t
T
i
m
e
r
3
i
n
t
e
r
r
u
p
t
r
e
q
u
e
s
t
X
CIN
D
a
t
a
b
u
s
Timer 1 count stop bit
10 bit
PWM1
circuit
1/2
Q
Q
S
T
P
5
3
l
a
t
c
h
P5
3
/PWM
1
/T
4OUT
10 bit
PWM0
circuit
1/2
Q
Q
S
T
T
i
m
e
r
3
o
p
e
r
a
t
i
n
g
m
o
d
e
s
e
l
e
c
t
i
o
n
b
i
t
P5
2
latch
Timer 3 output control bit
P5
2
direction
register
P
5
2
/
P
W
M
0
/
T
3
O
U
T
"00"
"01"
C
l
o
c
k
f
o
r
T
i
m
e
r
1
C
l
o
c
k
f
o
r
T
i
m
e
r
2
Clock for
Timer 3
C
l
o
c
k
f
o
r
T
i
m
e
r
4
S
y
s
t
e
m
c
l
o
c
k
c
o
n
t
r
o
l
b
i
t
s
F
r
e
q
u
e
n
c
y
d
i
v
i
s
i
o
n
s
e
l
e
c
t
i
o
n
b
i
t
s
(
3
b
i
t
s
f
o
r
e
a
c
h
T
i
m
e
r
)
C
l
o
c
k
f
o
r
T
i
m
e
r
4
C
l
o
c
k
f
o
r
T
i
m
e
r
3
C
l
o
c
k
f
o
r
T
i
m
e
r
2
C
l
o
c
k
f
o
r
T
i
m
e
r
1
12
T
h
e
f
o
l
l
o
w
i
n
g
v
a
l
u
e
s
c
a
n
b
e
s
e
l
e
c
t
e
d
t
h
e
c
l
o
c
k
f
o
r
T
i
m
e
r
;
1
/
1
,
1
/
2
,
1
/
1
6
,
1
/
3
2
,
1
/
6
4
,
1
/
1
2
8
,
1
/
2
5
6
,
1
/
1
0
2
4
Frequency divider
1/2
Q
Q
S
T
T
2OUT
output
edge switch bit
Timer 2 output control bit
P3
6
direction
register
P
3
6
/
T
2
O
U
T
/
f
/
(
L
E
D
6
)
P3
6
latch
T
i
m
e
r
2
o
u
t
p
u
t
s
e
l
e
c
t
i
o
n
b
i
t
P
3
6
c
l
o
c
k
o
u
t
p
u
t
c
o
n
t
r
o
l
b
i
t
X
C
I
N
X
I
N
S
y
s
t
e
m
c
l
o
c
k
f
"10"
T
i
m
e
r
Y
o
u
t
p
u
t
T
i
m
e
r
3
w
r
i
t
e
c
o
n
t
r
o
l
b
i
t
PWM01 register (2)
P
W
M
0
1
r
e
g
i
s
t
e
r
(
2
)
Timer 2 write
control bit
T
i
m
e
r
1
c
o
u
n
t
s
o
u
r
c
e
s
e
l
e
c
t
i
o
n
b
i
t
s
Timer 2 count
source selection
bits
Timer 2 count stop bit
Timer 3 count source
selection bit
Timer 3 count stop bit
T
i
m
e
r
1
T
i
m
e
r
2
T
i
m
e
r
3
T
i
m
e
r
4
Timer 2 latch (8)
T
i
m
e
r
2
(
8
)
Timer 3 latch (8)
Timer 3 (8)
T
i
m
e
r
4
i
n
t
e
r
r
u
p
t
r
e
q
u
e
s
t
T
i
m
e
r
4
w
r
i
t
e
c
o
n
t
r
o
l
b
i
t
Timer 4 latch (8)
T
i
m
e
r
4
(
8
)
Timer 4 count source
selection bits
Timer 4 count stop bit
T
3OUT
output
edge switch bit
T
i
m
e
r
3
o
u
t
p
u
t
s
e
l
e
c
t
i
o
n
b
i
t
T
i
m
e
r
4
o
p
e
r
a
t
i
n
g
m
o
d
e
s
e
l
e
c
t
i
o
n
b
i
t
Timer 4 output control bit
P
5
3
d
i
r
e
c
t
i
o
n
r
e
g
i
s
t
e
r
T
4
O
U
T
o
u
t
p
u
t
e
d
g
e
s
w
i
t
c
h
b
i
t
T
i
m
e
r
4
o
u
t
p
u
t
s
e
l
e
c
t
i
o
n
b
i
t
"
0
0
"
"
0
1
"
"
1
0
"
"0"
"1"
"0"
"1"
"1"
"0"
"1"
"0"
"0"
"1"
"01"
"
1
0
"
"00"
"1"
"0"
"
0
"
"
1
"
25
38C2 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
PRELIMINAR
Y
Notice: This is not a final specification.
Some parametric limits are subject to change.
Fig. 21 Waveform of PWM01
16-bit Timer
q
Frequency Divider For Timer
Each timer X and timer Y have the frequency dividers for the count
source. The count source of the frequency divider is switched to X
IN
or X
CIN
by the CPU mode register. The division ratio of each timer
can be controlled by the 3-bit register. The division ratio can be se-
lected from as follows;
1/1, 1/2, 1/16, 1/32, 1/64, 1/128, 1/256, 1/1024 of f(X
IN
) or f(X
CIN
).
q
Timer X
The timer X count source can be selected by setting the timer X mode
register. When f(X
CIN
) is selected as the count source, counting can
be performed regardless of X
CIN
oscillation. However, when X
CIN
is
stopped, the external pulse input from X
CIN
pin is counted.
The timer X operates as down-count. When the timer contents reach
"0000
16
", an underflow occurs at the next count pulse and the timer
latch contents are reloaded. After that, the timer continues count-
down. When the timer underflows, the interrupt request bit correspond-
ing to the timer X is set to "1".
Six operating modes can be selected for timer X by the timer X mode
register and timer X control register.
(1) Timer Mode
The count source can be selected by setting the timer X mode regis-
ter. In this mode, timer X operates as the 18-bit counter by setting the
timer X register (extension).
(2) Pulse Output Mode
Pulses of which polarity is inverted each time the timer underflows
are output from the T
XOUT
pin. Except for that, this mode operates
just as in the timer mode.
When using this mode, set the port sharing the T
XOUT
pin to output
mode.
(3) IGBT Output Mode
After dummy output from the T
XOUT
pin, count starts with the INT
0
pin input as a trigger. In the case that the timer X output edge switch
bit is "0", when the trigger is detected or the timer X underflows, "H" is
output from the T
XOUT
pin. When the count value corresponds with
the compare register value, the T
XOUT
output becomes "L".
After noise is cleared by noise filters, judging continuous 4-time same
levels with sampling clocks to be signals, the INT
0
signal can use 4
types of delay time by a delay circuit.
When using this mode, set the port sharing the INT
0
pin to input
mode and set the port sharing the T
XOUT
pin to output mode.
When the timer X output control bit 1 or 2 of the timer X control reg-
ister is set to "1", the timer X count stop bit is fixed to "1" forcibly by
the interrupt signal of INT
1
or INT
2
. And then, by stopping the timer X
counting, the T
XOUT
output can be fixed to the signal output at that
time.
Do not write "1" to the timer X register (extension) when using the
IGBT output mode.
(4) PWM Mode
IGBT dummy output, an external trigger with the INT
0
pin and output
control with pins INT
1
and INT
2
are not used. Except for those, this
mode operates just as in the IGBT output mode.
The period of PWM waveform is specified by the timer X set value. In
the case that the timer X output edge switch bit is "0", the "H" interval
is specified by the compare register set value.
When using this mode, set the port sharing the T
XOUT
pin to output
mode.
Do not write "1" to the timer X register (extension) when using the
PWM mode.
O
u
t
p
u
t
w
a
v
e
f
o
r
m
o
f
T
i
m
e
r
3
P
W
M
0
o
r
T
i
m
e
r
4
P
W
M
1
256
t
s
256
t
s
256
t
s
256
t
s
n
t
s
n
ts
n
t
s
n
t
s
n
t
s
n
t
s
n
t
s
n
ts
n
t
s
n
t
s
P
W
M
0
1
r
e
g
i
s
t
e
r
=
"
0
0
2
"
n: Setting value of Timer 3 or Timer 4
ts: One period of Timer 3 count source or Timer 4 count source
PWM01 register (address 0024
16
) : 2-bit value corresponding to PWM0 or PWM1
(n+1)
ts
(n+1)
ts
(n+1)
ts
(n+1)
ts
(
n
+
1
)
t
s
(
n
+
1
)
t
s
P
W
M
0
1
r
e
g
i
s
t
e
r
=
"
0
1
2
"
P
W
M
0
1
r
e
g
i
s
t
e
r
=
"
1
0
2
"
P
W
M
0
1
r
e
g
i
s
t
e
r
=
"
1
1
2
"
S
h
o
r
t
i
n
t
e
r
v
a
l
Short interval
Short interval
S
h
o
r
t
i
n
t
e
r
v
a
l
4
256
t
s
Long interval
26
38C2 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
PRELIMINAR
Y
Notice: This is not a final specification.
Some parametric limits are subject to change.
Fig. 22 Waveform of PWM/IGBT
(5) Event Counter Mode
The timer counts signals input through the CNTR
0
pin. In this mode,
timer X operates as the 18-bit counter by setting the timer X register
(extension). When using this mode, set the port sharing the CNTR
0
pin to input mode.
In this mode, the window control can be performed by the timer 1
underflow. When the bit 5 (data for control of event counter window)
of the timer X mode register is set to "1", counting is stopped at the
next timer 1 underflow. When the bit is set to "0", counting is re-
started at the next timer 1 underflow.
(6) Pulse Width Measurement Mode
In this mode, the count source is the output of frequency divider for
timer. In this mode, timer X operates as the 18-bit counter by setting
the timer X register (extension). When the bit 6 of the CNTR
0
active
edge switch bits is "0", counting is executed during the "H" interval of
CNTR
0
pin input. When the bit is "1", counting is executed during the
"L" interval of CNTR
0
pin input. When using this mode, set the port
sharing the CNTR
0
pin to input mode.
s
Notes on Timer X
(1) Write Order to Timer X
In the timer mode, pulse output mode, event counter mode and
pulse width measurement mode, write to the following registers in
the order as shown below;
the timer X register (extension),
the timer X register (low-order),
the timer X register (high-order).
Do not write to only one of them.
When the above mode is set and timer X operates as the 16-bit
counter, if the timer X register (extension) is never set after reset is
released, setting the timer X register (extension) is not required. In
this case, write the timer X register (low-order) first and the timer X
register (high-order). However, once writing to the timer X register
is executed, note that the value is retained to the reload latch.
In the IGBT and PWM modes, do not write "1" to the timer X register
(extension). Also, when "1" is already written to the timer X register,
be sure to write "0" to the register before using.
Write to the following registers in the order as shown below;
the compare register (high- and low-order),
the timer X register (extension),
the timer X register (low-order),
the timer X register (high-order).
It is possible to use whichever order to write to the compare regis-
ter (high- and low-order). However, write both the compare register
and the timer X register at the same time.
(2) Read Order to Timer X
In all modes, read the following registers in the order as shown below;
the timer X register (extension),
the timer X register (high-order),
the timer X register (low-order).
When reading the timer X register (extension) is not required, read
the timer X register (high-order) first and the timer X register (low-
order).
Read order to the compare register is not specified.
If reading to the timer X register during write operation or writing to
it during read operation is performed, normal operation will not be
performed.
(3) Write to Timer X
When writing a value to the timer X address to write to the latch
only, the value is set into the reload latch and the timer is updated
at the next underflow. Normally, when writing a value to the timer X
address, the value is set into the timer and the timer latch at the
same time, because they are written at the same time.
When writing to the latch only, if the write timing to the high-order
reload latch and the underflow timing are almost the same, the value
is set into the timer and the timer latch at the same time. In this time,
counting is stopped during writing to the high-order reload latch.
Do not switch the timer count source during timer count operation.
Stop the timer count before switching it.
t
s
Timer X count
source
T
i
m
e
r
X
P
W
M
m
o
d
e
I
G
B
T
m
o
d
e
(
n
-
m
+
1
)
t
s
m
t
s
(
n
+
1
)
t
s
W
h
e
n
t
h
e
T
i
m
e
r
X
s
e
t
t
i
n
g
v
a
l
u
e
=
n
a
n
d
t
h
e
c
o
m
p
a
r
e
r
e
g
i
s
t
e
r
s
e
t
t
i
n
g
v
a
l
u
e
=
m
,
t
h
e
f
o
l
l
o
w
i
n
g
P
W
M
w
a
v
e
f
o
r
m
i
s
o
u
t
p
u
t
;
D
u
t
y
:
(
n
-
m
+
1
)
/
(
n
+
1
)
P
e
r
i
o
d
:
(
n
+
1
)
t
s
(
t
s
:
p
e
r
i
o
d
o
f
t
i
m
e
r
X
c
o
u
n
t
s
o
u
r
c
e
)
27
38C2 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
PRELIMINAR
Y
Notice: This is not a final specification.
Some parametric limits are subject to change.
(4) Set of Timer X Mode Register
Set the write control bit of the timer X mode register to "1" (write to
the latch only) when setting the IGBT output and PWM modes.
Output waveform simultaneously reflects the contents of both regis-
ters at the next underflow after writing to the timer X register (high-
order).
(5) Output Control Function of Timer X
When using the output control function (INT
1
and INT
2
) in the IGBT
output mode, set the levels of INT
1
and INT
2
to "H" in the falling edge
active or to "L" in the rising edge active before switching to the IGBT
output mode.
(6) Note on Switch of CNTR
0
Active Edge
When the CNTR
0
active edge switch bits are set, at the same time,
the interrupt active edge is also affected.
When the pulse width is measured, set the bit 7 of the CNTR
0
ac-
tive edge switch bits to "0".
Timer Y
Timer Y is a 16-bit timer.
The timer Y count source can be selected by setting the timer Y mode
register. When f(X
CIN
) is selected as the count source, counting can
be performed regardless of X
CIN
oscillation. However, when X
CIN
is
stopped, the external pulse input from X
CIN
pin is counted.
Four operating modes can be selected for timer Y by the timer Y
mode register. Also, the real time port can be controlled.
(1) Timer Mode
The timer Y count source can be selected by setting the timer Y mode
register.
(2) Period Measurement Mode
The interrupt request is generated at rising/falling edge of CNTR
1
pin input signal. Simultaneously, the value in timer Y latch is reloaded
in timer Y and timer Y continues counting. Except for that, this mode
operates just as in the timer mode.
The timer value just before the reloading at rising/falling of CNTR
1
pin input is retained until the timer Y is read once after the reload.
The rising/falling timing of CNTR
1
pin input is found by CNTR
1
inter-
rupt. When using this mode, set the port sharing the CNTR
1
pin to
input mode.
(3) Event Counter Mode
The timer counts signals input through the CNTR
1
pin.
Except for that, this mode operates just as in the timer mode.
When using this mode, set the port sharing the CNTR
1
pin to input
mode.
(4) Pulse Width HL Continuously Measurement
Mode
The interrupt request is generated at both rising and falling edges of
CNTR
1
pin input signal. Except for that, this mode operates just as in
the period measurement mode. When using this mode, set the port
sharing the CNTR
1
pin to input mode.
s
Notes on Timer Y
q
CNTR
1
Interrupt Active Edge Selection
CNTR
1
interrupt active edge depends on the CNTR
1
active edge
switch bit. However, in pulse width HL continuously measurement
mode, CNTR
1
interrupt request is generated at both rising and falling
edges of CNTR
1
pin input signal regardless of the setting of CNTR
1
active edge switch bit.
q
Timer Y Read/Write Control
When reading from/writing to timer Y, read from/write to both the
high-order and low-order bytes of timer Y. When the value is read,
read the high-order bytes first and the low-order bytes next. When
the value is written, write the low-order bytes first and the high-
order bytes next.
If reading from the timer Y register during write operation or writing
to it during read operation is performed, normal operation will not
be performed.
When writing a value to the timer Y address to write to the latch
only, the value is set into the reload latch and the timer is updated
at the next underflow. Normally, when writing a value to the timer Y
address, the value is set into the timer and the timer latch at the
same time, because they are set to write at the same time.
When writing to the latch only, if the write timing to the high-order
reload latch and the underflow timing are almost the same, the value
is set into the timer and the timer latch at the same time. In this
time, counting is stopped during writing to the high-order reload
latch.
Do not switch the timer count source during timer count operation.
Stop the timer count before switching it.
q
Real Time Port Control
When the real time port function is valid, data for the real time port is
output from ports P4
7
and P4
6
each time the timer Y underflows.
(However, if the real time port control bit is changed from "0" to "1"
after the data for real time port is set, data is output independent of
the timer Y operation.) When the data for the real time port is changed
while the real time port function is valid, the changed data is output at
the next underflow of timer Y. Before using this function, set the cor-
responding port direction registers to output mode.
28
38C2 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
PRELIMINAR
Y
Notice: This is not a final specification.
Some parametric limits are subject to change.
Fig. 23 Structure of Timer X, Y related registers
Timer X mode register
(TXM: address 002F
16
)
Timer X operating mode bits
b2 b1 b0
0 0 0 : Timer mode
0 0 1 : Pulse output mode
0 1 0 : IGBT output mode
0 1 1 : PWM mode
1 0 0 : Event counter mode
1 0 1 : Pulse width measurement mode
Timer X write control bit
0 : Write data to both timer latch and timer
1 : Write data to timer latch only
Timer X count source selection bit
0 : Frequency divider output
1 : f(X
CIN
)
Data for control of event counter window
0 : Event count enabled
1 : Event count disabled
Timer X count stop bit
0 : Count operation
1 : Count stop
Timer X output selection bit (P3
5
)
0 : I/O port
1 : Timer X output
b7
b0
Timer X control register
(TXCON: address 0FF4
16
)
Noise filter sampling clock selection bit
0 : f(X
IN
)/2
1 : f(X
IN
)/4
External trigger delay time selection bits
b2 b1
0 0 : Not delayed
0 1 : (4/f(X
IN
))
s
1 0 : (8/f(X
IN
))
s
1 1 : (16/f(X
IN
))
s
Timer X output control bit 1 (P5
1
)
0 : Not used
1 : INT
1
interrupt used
Timer X output control bit 2 (P3
4
)
0 : Not used
1 : INT
2
interrupt used
Timer X output edge switch bit
0 : Start at "L" output
1 : Start at "H" output
CNTR
0
active edge switch bits
b7 b6
0 0 : Count at rising edge in event counter mode
Falling edge active for CNTR
0
interrupt
Measure "H" pulse width in pulse width measurement mode
0 1 : Count at falling edge in event counter mode
Rising edge active for CNTR
0
interrupt
Measure "L" pulse width in pulse width measurement mode
1 0 : Count at both edges in event counter mode
Both edges active for CNTR
0
interrupt
1 1 : Count at both edges in event counter mode
Both edges active for CNTR
0
interrupt
b7
b0
Timer XY frequency division selection register
(PREXY: address 0FF7
16
)
Timer X frequency division selection bits
b2 b1 b0
0 0 0 : 1/16
f(X
IN
) or 1/16
f(X
CIN
)
0 0 1 : 1/1
f(X
IN
) or 1/1
f(X
CIN
)
0 1 0 : 1/2
f(X
IN
) or 1/2
f(X
CIN
)
0 1 1 : 1/32
f(X
IN
) or 1/32
f(X
CIN
)
1 0 0 : 1/64
f(X
IN
) or 1/64
f(X
CIN
)
1 0 1 : 1/128
f(X
IN
) or 1/128
f(X
CIN
)
1 1 0 : 1/256
f(X
IN
) or 1/256
f(X
CIN
)
1 1 1 : 1/1024
f(X
IN
) or 1/1024
f(X
CIN
)
Timer Y frequency division selection bits
b5 b4 b3
0 0 0 : 1/16
f(X
IN
) or 1/16
f(X
CIN
)
0 0 1 : 1/1
f(X
IN
) or 1/1
f(X
CIN
)
0 1 0 : 1/2
f(X
IN
) or 1/2
f(X
CIN
)
0 1 1 : 1/32
f(X
IN
) or 1/32
f(X
CIN
)
1 0 0 : 1/64
f(X
IN
) or 1/64
f(X
CIN
)
1 0 1 : 1/128
f(X
IN
) or 1/128
f(X
CIN
)
1 1 0 : 1/256
f(X
IN
) or 1/256
f(X
CIN
)
1 1 1 : 1/1024
f(X
IN
) or 1/1024
f(X
CIN
)
Not used (returns "0" when read)
b7
b0
Timer Y mode register
(TYM: address 0030
16
)
Real time port control bit
0 : Real time port function invalid
1 : Real time port functin valid
P4
6
data for real time port
P4
7
data for real time port
Timer Y count source selection bit
0 : Frequency divider output
1 : f(X
CIN
)
Timer Y operating mode bits
b5 b4
0 0 : Timer mode
0 1 : Period measurement mode
1 0 : Event counter mode
1 1 : Pulse width HL continuous measurement mode
CNTR
1
active edge switch bit
0 : Count at rising edge in event counter mode
Measure falling period in period measurement mode
Falling edge active for CNTR
1
interrupt
1 : Count at falling edge in event counter mode
Measure rising period in period measurement mode
Rising edge active for CNTR
1
interrupt
Timer Y count stop bit
0 : Count operation
1 : Count stop
b7
b0
Timer Y mode register 2
(TYM2: address 0FFB
16
)
Timer Y write control bit
0 : Write data to both timer latch and timer
1 : Write data to timer latch only
Not used (returns "0" when read)
b7
b0
29
38C2 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
PRELIMINAR
Y
Notice: This is not a final specification.
Some parametric limits are subject to change.
Fig. 24 Block diagram of Timer X, Y
Real time port
control bit
Real time port
control bit
Q D
Latch
Q D
L
a
t
c
h
P4
7
direction
register
P4
7
latch
P4
7
data for real time port
P4
6
direction
register
P4
6
latch
P4
6
data for real time port
"
1
"
Timer Y (low-order) latch (8)
"
0
"
CNTR
1
active
edge switch bit
"10"
P
4
7
/
R
T
P
1
/
A
N
7
P4
6
/RTP
0
/AN
6
P6
0
/CNTR
1
Falling edge detection
Period measurement mode
T
i
m
e
r
Y
i
n
t
e
r
r
u
p
t
r
e
q
u
e
s
t
Pulse width HL continuous
measurement mode
Timer Y operating
mode bits
C
N
T
R
1
i
n
t
e
r
r
u
p
t
r
e
q
u
e
s
t
Rising edge detection
Count source selection bit
X
c
I
N
"
1
"
Clock for Timer Y
D
a
t
a
b
u
s
1
/
2
1
/
4
F
r
e
q
u
e
n
c
y
d
i
v
i
d
e
r
N
o
i
s
e
f
i
l
t
e
r
s
a
m
p
l
i
n
g
c
l
o
c
k
s
e
l
e
c
t
i
o
n
b
i
t
"1"
"
0
"
T
i
m
e
r
X
i
n
t
e
r
r
u
p
t
r
e
q
u
e
s
t
Equal
"000"
"001"
"010"
"011"
"101"
P
u
l
s
e
w
i
d
t
h
m
e
a
s
u
r
e
m
e
n
t
m
o
d
e
Timer X count
stop bit
Compare register (low-order)(8) Compare register (high-order)(8)
Output selection bit
P3
5
latch
P3
5
direction
register
P3
5
/T
XOUT
/(LED
5
)
P
5
1
/
I
N
T
1
P
3
4
/
I
N
T
2
/
(
L
E
D
4
)
S
Q
Q
T
R
T
XOUT
edge
switch bit
S
"0"
"
1
"
Q
Q
T
S
Pulse output mode
C
N
T
R
0
a
c
t
i
v
e
e
d
g
e
s
w
i
t
c
h
b
i
t
s
T
i
m
e
r
X
o
p
e
r
a
t
i
n
g
m
o
d
e
b
i
t
s
CNTR
0
interrupt request
"
1
0
0
"
E
x
t
e
n
d
l
a
t
c
h
(
2
)
E
x
t
e
n
d
c
o
u
n
t
e
r
(
2
)
T
i
m
e
r
X
w
r
i
t
e
c
o
n
t
r
o
l
b
i
t
T
i
m
e
r
1
i
n
t
e
r
r
u
p
t
D
Q
L
a
t
c
h
Data for control of event counter window
P
3
7
/
C
N
T
R
0
/
(
L
E
D
7
)
P
5
0
/
I
N
T
0
0
s
Delay time
selection bits
4/f(XIN)
"00"
"01"
"10"
"11"
8/f(XIN)
16/f(XIN)
N
o
i
s
e
f
i
l
t
e
r
(
4
t
i
m
e
s
s
a
m
e
l
e
v
e
l
s
j
u
d
g
m
e
n
t
)
I
N
T
0
i
n
t
e
r
r
u
p
t
r
e
q
u
e
s
t
Count source selection bit
Xc
IN
C
l
o
c
k
f
o
r
T
i
m
e
r
X
Sy
s
t
e
m
c
l
o
c
k
c
o
n
t
r
o
l
b
i
t
s
3
C
l
o
c
k
f
o
r
T
i
m
e
r
Y
X
I
N
R
e
a
l
t
i
m
e
p
o
r
t
c
o
n
t
r
o
l
b
i
t
Timer Y mode register
write signal
Timer Y (low-order)(8)
X
c
I
N
X
I
N
F
r
e
q
u
e
n
c
y
d
i
v
i
d
e
r
IGBT output mode
PWM mode
Timer Y operating mode bits
Timer X frequency division
selection bit
Timer Y frequency division
selection bit
3
B
o
t
h
e
d
g
e
s
d
e
t
e
c
t
i
o
n
"00"
"
0
1
"
"
1
0
"
"
1
1
"
Edge
detection
T
XOUT
output
control bit 1
T
X
O
U
T
o
u
t
p
u
t
c
o
n
t
r
o
l
b
i
t
2
Timer X
operating
mode bits
"
0
1
0
"
"00", "01", "11"
"
1
"
"0"
"1"
"0"
"1"
"0"
"00", "01", "10"
"
1
1
"
"
0
"
Timer Y write control bit
T
i
m
e
r
Y
c
o
u
n
t
s
t
o
p
b
i
t
"000"
"001"
"011"
"100"
"101"
Timer X operating
mode bits
"
0
1
0
"
Delay
circuit
Timer Y (high-order) latch (8)
Timer Y (high-order)(8)
Timer X (low-order) latch (8)
Timer X (low-order)(8)
Timer X (high-order) latch (8)
T
i
m
e
r
X
(
h
i
g
h
-
o
r
d
e
r
)
(
8
)
T
h
e
f
o
l
l
o
w
i
n
g
v
a
l
u
e
s
c
a
n
b
e
s
e
l
e
c
t
e
d
t
h
e
c
l
o
c
k
f
o
r
T
i
m
e
r
;
1
/
1
,
1
/
2
,
1
/
1
6
,
1
/
3
2
,
1
/
6
4
,
1
/
1
2
8
,
1
/
2
5
6
,
1
/
1
0
2
4
"
1
"
"0"
30
38C2 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
PRELIMINAR
Y
Notice: This is not a final specification.
Some parametric limits are subject to change.
SERIAL I/O
The 38C2 group has built-in two 8-bit serial I/O.
Serial I/O can be used as either clock synchronous or asynchronous
(UART) serial I/O. A dedicated timer is also provided for baud rate
generation.
(1) Clock Synchronous Serial I/O Mode
Clock synchronous serial I/O mode can be selected by setting the
serial I/O mode selection bit of the serial I/O control register to "1".
For clock synchronous serial I/O, the transmitter and the receiver
must use the same clock. If an internal clock is used, transfer is
started by a write signal to the TB/RB.
Fig. 25 Block diagram of clock synchronous serial I/O
Fig. 26 Operation of clock synchronous serial I/O function
1/4
1/4
F/F
P5
6
/S
CLK1
[P3
1
/S
CLK2
]
Serial I/O status register
Serial I/O control register
P5
7
/S
RDY1
[P3
0
/S
RDY2
]
P5
4
/R
X
D
1
[P3
3
/R
X
D
2
]
P5
5
/T
X
D
1
[P3
2
/T
X
D
2
]
f(X
IN
)
Receive buffer register
Address 001C
16
[Address 001E
16
]
Receive shift register
Receive buffer full flag (RBF)
Receive interrupt request (RI)
Clock control circuit
Shift clock
Serial I/O synchronous
clock selection bit
Frequency division ratio 1/(n+1)
Baud rate generator
Address 0FE2
16
[Address 0FE5
16
]
BRG count source selection bit
Clock control circuit
Falling-edge detector
Transmit buffer register
Data bus
Address 001C
16
[Address 001E
16
]
Shift clock
Transmit shift completion flag (TSC)
Transmit buffer empty flag (TBE)
Transmit interrupt request (TI)
Transmit interrupt source selection bit
Address 001D
16
[Address 001F
16
]
Data bus
Address 0FE0
16
[Address 0FE3
16
]
Transmit shift register
(f(X
CIN
) in low-speed mode)
[ ] : For Serial I/O2
D
7
D
7
D
0
D
1
D
2
D
3
D
4
D
5
D
6
D
0
D
1
D
2
D
3
D
4
D
5
D
6
RBF = 1
TSC = 1
TBE = 0
TBE = 1
TSC = 0
Transfer shift clock
(1/2 to 1/2048 of the internal
clock, or an external clock)
Serial output TxD
Serial input RxD
Write pulse to receive/transmit
buffer register
Overrun error (OE)
detection
Notes 1: As the transmit interrupt (TI), which can be selected, either when the transmit buffer has emptied (TBE=1) or after the
transmit shift operation has ended (TSC=1), by setting the transmit interrupt source selection bit (TIC) of the serial I/O
control register.
2: If data is written to the transmit buffer register when TSC=0, the transmit clock is generated continuously and serial data
is output continuously from the TxD pin.
3: The receive interrupt (RI) is set when the receive buffer full flag (RBF) becomes "1" .
Receive enable signal
S
RDY
31
38C2 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
PRELIMINAR
Y
Notice: This is not a final specification.
Some parametric limits are subject to change.
(2) Asynchronous Serial I/O (UART) Mode
Clock asynchronous serial I/O mode (UART) can be selected by clear-
ing the serial I/O mode selection bit of the serial I/O control register
to "0".
Eight serial data transfer formats can be selected, and the transfer
formats used by a transmitter and receiver must be identical.
The transmit and receive shift registers each have a buffer, but the
two buffers have the same address in memory. Since the shift regis-
ter cannot be written to or read from directly, transmit data is written
to the transmit buffer register, and receive data is read from the re-
ceive buffer register.
The transmit buffer register can also hold the next data to be trans-
mitted, and the receive buffer register can hold a character while the
next character is being received.
Fig. 27 Block diagram of UART serial I/O
f(X
IN
)
1/4
OE
PE FE
1/16
1/16
Data bus
Receive buffer register
Receive shift register
Receive buffer full flag (RBF)
Receive interrupt request (RI)
Baud rate generator
Frequency division ratio 1/(n+1)
ST/SP/PA generator
Transmit buffer register
Data bus
Transmit shift register
Transmit shift completion flag (TSC)
Transmit buffer empty flag (TBE)
Transmit interrupt request (TI)
ST detector
SP detector
UART control register
Address 0FE1
16
[Address 0FE4
16
]
Character length selection bit
BRG count source selection bit
Transmit interrupt source selection bit
Serial I/O synchronous clock selection bit
Clock control circuit
Character length selection bit
7 bits
8 bits
Serial I/O control register
Serial I/O status register
(f(X
CIN
) in low-speed mode)
P5
6
/S
CLK1
[P3
1
/S
CLK2
]
P5
4
/R
X
D
1
[P3
3
/R
X
D
2
]
P5
5
/T
X
D
1
[P3
2
/T
X
D
2
]
Address 001C
16
[Address 001E
16
]
Address 0FE2
16
[Address 0FE5
16
]
Address 001C
16
[Address 001E
16
]
Address 001D
16
[Address 001F
16
]
Address 0FE0
16
[Address 0FE3
16
]
[ ] : For Serial I/O2
Fig. 28 Operation of UART serial I/O function
TSC=0
TBE=1
RBF=0
TBE=0
TBE=0
RBF=1
RBF=1
ST
D
0
D
1
SP
D
0
D
1
ST
SP
TBE=1
TSC=1
ST
D
0
D
1
SP
D
0
D
1
ST
SP
Transmit or receive clock
Transmit buffer write
signal
Generated at 2nd bit in 2-stop-bit mode
1 start bit
7 or 8 data bit
1 or 0 parity bit
1 or 2 stop bit (s)
1: Error flag detection occurs at the same time that the RBF flag becomes "1" (at 1st stop bit, during reception).
2: As the transmit interrupt (TI), when either the TBE or TSC flag becomes "1," can be selected to occur depending on the setting of the transmit
interrupt source selection bit (TIC) of the serial I/O control register.
3: The receive interrupt (RI) is set when the RBF flag becomes "1."
4: After data is written to the transmit buffer when TSC=1, 0.5 to 1.5 cycles of the data shift cycle is necessary until changing to TSC=0.
Notes
Serial output T
X
D
Serial input R
X
D
Receive buffer read
signal
32
38C2 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
PRELIMINAR
Y
Notice: This is not a final specification.
Some parametric limits are subject to change.
[Transmit Buffer Register/Receive Buffer Reg-
ister (TB/RB)]
The transmit buffer register and the receive buffer register are lo-
cated at the same address. The transmit buffer is write-only and the
receive buffer is read-only. If a character bit length is 7 bits, the MSB
of data stored in the receive buffer is "0".
[Serial I/O Status Register (SIO1STS, SIO2STS)]
The read-only serial I/O status register consists of seven flags (bits 0
to 6) which indicate the operating status of the serial I/O function and
various errors.
Three of the flags (bits 4 to 6) are valid only in UART mode.
The receive buffer full flag (bit 1) is cleared to "0" when the receive
buffer register is read.
If there is an error, it is detected at the same time that data is trans-
ferred from the receive shift register to the receive buffer register,
and the receive buffer full flag is set. A write to the serial I/O status
register clears all the error flags OE, PE, FE, and SE (bit 3 to bit 6,
respectively). Writing "0" to the serial I/O enable bit SIOE (bit 7 of the
serial I/O control register) also clears all the status flags, including
the error flags.
All bits of the serial I/O status register are initialized to "0" at reset,
but if the transmit enable bit (bit 4) of the serial I/O control register
has been set to "1", the transmit shift completion flag (bit 2) and the
transmit buffer empty flag (bit 0) become "1".
[Serial I/O Control Register (SIO1CON, SIO2CON)]
The serial I/O control register consists of eight control bits for the
serial I/O function.
[UART Control Register (UART1CON, UART2CON)]
The UART control register consists of four control bits (bits 0 to 3)
which are valid when asynchronous serial I/O is selected and set the
data format of an data transfer and one bit (bit 4) which is always
valid and sets the output structure of the P5
5
/T
X
D
1
[P3
2
/TxD
2
] pin.
[Baud Rate Generator (BRG1, BRG2)]
The baud rate generator determines the baud rate for serial transfer.
The baud rate generator divides the frequency of the count source
by 1/(n + 1), where n is the value written to the baud rate generator.
33
38C2 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
PRELIMINAR
Y
Notice: This is not a final specification.
Some parametric limits are subject to change.
Fig. 29 Structure of serial I/O related registers
b7
b7
Transmit buffer empty flag (TBE)
0: Buffer full
1: Buffer empty
Receive buffer full flag (RBF)
0: Buffer empty
1: Buffer full
Transmit shift completion flag (TSC)
0: Transmit shift in progress
1: Transmit shift completed
Overrun error flag (OE)
0: No error
1: Overrun error
Parity error flag (PE)
0: No error
1: Parity error
Framing error flag (FE)
0: No error
1: Framing error
Summing error flag (SE)
0: (OE) U (PE) U (FE)=0
1: (OE) U (PE) U (FE)=1
Not used (returns "1" when read)
Serial I/O status register
Serial I/O control register
b0
b0
BRG count source selection bit (CSS)
0: f(X
IN
) (f(X
CIN
) in low-speed mode)
1: f(X
IN
)/4 (f(X
CIN
)/4 in low-speed mode)
Serial I/O synchronous clock selection bit (SCS)
0: BRG output divided by 4 when clock synchronous
serial I/O is selected.
BRG output divided by 16 when UART is selected.
1: External clock input when clock synchronous serial
I/O is selected.
External clock input divided by 16 when UART is selected.
S
RDY
output enable bit (SRDY)
0: P5
7
[P3
0
] pin operates as ordinary I/O pin
1: P5
7
[P3
0
] pin operates as S
RDY
output pin
Transmit interrupt source selection bit (TIC)
0: Interrupt when transmit buffer has emptied
1: Interrupt when transmit shift operation is completed
Transmit enable bit (TE)
0: Transmit disabled
1: Transmit enabled
Receive enable bit (RE)
0: Receive disabled
1: Receive enabled
Serial I/O mode selection bit (SIOM)
0: Clock asynchronous (UART) serial I/O
1: Clock synchronous serial I/O
Serial I/O enable bit (SIOE)
0: Serial I/O disabled
(pins P5
4
[P3
0
] to P5
7
[P3
3
] operate as ordinary I/O pins)
1: Serial I/O enabled
(pins P5
4
[P3
0
] to P5
7
[P3
3
] operate as serial I/O pins)
b7
UART control register
Character length selection bit (CHAS)
0: 8 bits
1: 7 bits
Parity enable bit (PARE)
0: Parity checking disabled
1: Parity checking enabled
Parity selection bit (PARS)
0: Even parity
1: Odd parity
Stop bit length selection bit (STPS)
0: 1 stop bit
1: 2 stop bits
P5
5
/TXD
1
[P3
2
/TxD
2
] P-channel output disable bit (POFF)
0: CMOS output (in output mode)
1: N-channel open drain output (in output mode)
Not used (return "1" when read)
b0
(SIO1STS : address 001D
16
)
[SIO2STS : address 001F
16
]
(SIO1CON : address 0FE0
16
)
[SIO2CON : address 0FE3
16
]
(UART1CON : address 0FE1
16
)
[UART2CON : address 0FE4
16
]
( ) : For Serial I/O1
[ ] : For Serial I/O2
34
38C2 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
PRELIMINAR
Y
Notice: This is not a final specification.
Some parametric limits are subject to change.
A-D CONVERTER
The 38C2 group has a 10-bit A-D converter. The A-D converter per-
forms successive approximation conversion.
[A-D Conversion Register (ADL, ADH)]
One of these registers is a high-order register, and the other is a low-
order register. The high-order 8 bits of a conversion result is stored in
the A-D conversion register (high-order) (address 001B
16
), and the
low-order 2 bits of the same result are stored in bit 7 and bit 6 of the
A-D conversion register (low-order) (address 001A
16
).
During A-D conversion, do not read these registers.
Also, the connection between the resistor ladder and reference volt-
age input pin (V
REF
) can be controlled by the V
REF
input switch bit
(bit 0 of address 001A
16
). When "1" is written to this bit, the resistor
ladder is always connected to V
REF
. When "0" is written to this bit,
the resistor ladder is disconnected from V
REF
except during the A-D
conversion.
[A-D Control Register (ADCON)]
This register controls A-D converter. Bits 2 to 0 are analog input pin
selection bits. Bit 3 is an AD conversion completion bit and "0" during A-
D conversion. This bit is set to "1" upon completion of A-D conversion.
A-D conversion is started by setting "0" in this bit.
[Comparison Voltage Generator]
The comparison voltage generator divides the voltage between AV
SS
and V
REF
, and outputs the divided voltages.
[Channel Selector]
The channel selector selects one of the input ports P4
7
/AN
7
P4
0
/
AN
0
and inputs it to the comparator.
[Comparator and Control Circuit]
The comparator and control circuit compares an analog input volt-
age with the comparison voltage and stores the result in the A-D
conversion register. When an A-D conversion is completed, the con-
trol circuit sets the AD conversion completion bit and the AD conver-
sion interrupt request bit to "1."
Fig. 31 Block diagram of A-D converter
Fig. 30 Structure of A-D control register
Data bus
AV
SS
A-D interrupt request
b7
b0
3
P4
0
/O
OUT0
/AN
0
P4
1
/O
OUT1
/AN
1
P4
2
/AN
2
P4
3
/AN
3
P4
4
/AN
4
P4
5
/AN
5
P4
6
/AN
6
P4
7
/AN
7
A-D control register
Channel selector
Comparator
A-D control circuit
A-D conversion register (H)
A-D conversion register (L)
(Address 001B
16
)
(Address 001A
16
)
Resistor ladder
V
REF
Analog input pin selection bits
b2 b1 b0
0 0 0: P4
0
/AN
0
0 0 1: P4
1
/AN
1
0 1 0: P4
2
/AN
2
0 1 1: P4
3
/AN
3
1 0 0: P4
4
/AN
4
1 0 1: P4
5
/AN
5
1 1 0: P4
6
/AN
6
1 1 1: P4
7
/AN
7
AD conversion completion bit
0: Conversion in progress
1: Conversion completed
AD conversion clock selection bits
b5 b4
0 0: Frequency not divided
0 1: Frequency divided by 2
1 0: Frequency divided by 4
1 1: Frequency divided by 8
10-bit or 8-bit conversion switch bit
0: 10-bit AD
1: 8-bit AD
Booster selection bit
0: Booster not used
1: Booster used
A-D control register
(ADCON: address 0019
16
)
b7
b0
10-bit reading
(Read address 001B
16
before 001A
16
)
A-D conversion register 1
(Address 001B
16
)
A-D conversion register 2
(Address 001A
16
)
8-bit reading
(Read only address 001B
16
)
(Address 001B
16
)
b0
b7
b0
b1
* V
REF
input switch bit
b9 b8 b7 b6 b5 b4 b3 b2
b7
b0
b9 b8 b7 b6 b5 b4 b3 b2
b7
b0
*
(high-order)
(low-order)
Note : The bit 5 to bit 1 of address 001A
16
becomes "0" at reading.
Also, bit 0 is undefined at reading.
1: ON
0: ON only during A-D conversion
35
38C2 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
PRELIMINAR
Y
Notice: This is not a final specification.
Some parametric limits are subject to change.
LCD DRIVE CONTROL CIRCUIT
The 38C2 group has the built-in Liquid Crystal Display (LCD) drive
control circuit consisting of the following.
LCD display RAM
Segment output disable register
LCD mode register
Selector
Timing controller
Common driver
Segment driver
Bias control circuit
A maximum of 24 segment output pins and 4 common output pins
can be used.
Up to 96 pixels can be controlled for an LCD display. When the LCD
enable bit is set to "1" after data is set in the LCD mode register, the
Fig. 32 Structure of LCD related registers
segment output disable register, and the LCD display RAM, the LCD
drive control circuit starts reading the display data automatically, per-
forms the bias control and the duty ratio control, and displays the
data on the LCD panel.
Table 8 Maximum number of display pixels at each duty ratio
Duty ratio
2
3
4
Maximum number of display pixels
48 dots
or 8 segment LCD 6 digits
72 dots
or 8 segment LCD 9 digits
96 dots
or 8 segment LCD 12 digits
Segment output disable bit 0
0 : Segment output SEG
0
1 : Output port P0
0
Segment output disable bit 1
0 : Segment output SEG
1
1 : Output port P0
1
Segment output disable bit 2
0 : Segment output SEG
2
1 : Output port P0
2
Segment output disable bit 3
0 : Segment output SEG
3
1 : Output port P0
3
Segment output disable bit 4
0 : Segment output SEG
4
1 : Output port P0
4
Segment output disable bit 5
0 : Segment output SEG
5
1 : Output port P0
5
Segment output disable bit 6
0 : Segment output SEG
6
1 : Output port P0
6
Segment output disable bit 7
0 : Segment output SEG
7
1 : Output port P0
7
Segment output disable register 0
(SEG0 : address 0FF8
16
)
b7
b0
LCD mode register
(LM : address 0039
16
)
Duty ratio selection bits
b1 b0
0 0 : Not used
0 1 : 2 (use COM
0
,COM
1
)
1 0 : 3 (use COM
0
COM
2
)
1 1 : 4 (use COM
0
COM
3
)
Bias control bit
0 : 1/3 bias
1 : 1/2 bias
LCD enable bit
0 : LCD OFF
1 : LCD ON
LCD drive timing selection bit
0 : Type A
1 : Type B
LCD circuit divider division ratio selection bits
b6 b5
0 0 : Clock input
0 1 : 2 division of clock input
1 0 : 4 division of clock input
1 1 : 8 division of clock input
LCDCK count source selection bit (Note)
0 : f(X
CIN
)/32
1 : f(X
IN
)/8192 (f(X
CIN
)/8192 in low-speed mode)
Note : LCDCK is a clock for an LCD timing controller.
b7
b0
Segment output disable bit 8
0 : Segment output SEG
8
1 : Output port P1
0
Segment output disable bit 9
0 : Segment output SEG
9
1 : Output port P1
1
Segment output disable bit 10
0 : Segment output SEG
10
1 : Output port P1
2
Segment output disable bit 11
0 : Segment output SEG
11
1 : Output port P1
3
Segment output disable bit 12
0 : Segment output SEG
12
1 : Output port P1
4
Segment output disable bit 13
0 : Segment output SEG
13
1 : Output port P1
5
Segment output disable bit 14
0 : Segment output SEG
14
1 : Output port P1
6
Segment output disable bit 15
0 : Segment output SEG
15
1 : Output port P1
7
Segment output disable register 1
(SEG1 : address 0FF9
16
)
b7
b0
Segment output disable bit 16
0 : Output port P2
0
1 : Segment output SEG
16
Segment output disable bit 17
0 : Output port P2
1
1 : Segment output SEG
17
Segment output disable bit 18
0 : Output port P2
2
1 : Segment output SEG
18
Segment output disable bit 19
0 : Output port P2
3
1 : Segment output SEG
19
Segment output disable bit 20
0 : Output port P2
4
1 : Segment output SEG
20
Segment output disable bit 21
0 : Output port P2
5
1 : Segment output SEG
21
Segment output disable bit 22
0 : Output port P2
6
1 : Segment output SEG
22
Segment output disable bit 23
0 : Output port P2
7
1 : Segment output SEG
23
Segment output disable register 2
(SEG2 : address 0FFA
16
)
b7
b0
Note : Only pins set to output ports by the direction register can be controlled to switch
to output ports or segment outputs by the segment output disable register.
36
38C2 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
PRELIMINAR
Y
Notice: This is not a final specification.
Some parametric limits are subject to change.
Fig. 33 Block diagram of LCD controller/driver
f
(
X
C
I
N
)
/
3
2
f
(
X
I
N
)
/
8
1
9
2
L
e
v
e
l
s
h
i
f
t
L
e
v
e
l
s
h
i
f
t
L
e
v
e
l
s
h
i
f
t
L
e
v
e
l
s
h
i
f
t
L
e
v
e
l
s
h
i
f
t
L
e
v
e
l
s
h
i
f
t
L
e
v
e
l
s
h
i
f
t
L
e
v
e
l
s
h
i
f
t
L
e
v
e
l
s
h
i
f
t
L
e
v
e
l
s
h
i
f
t
C
O
M
0
C
O
M
1
C
O
M
2
C
O
M
3
V
S
S
P
2
7
/
S
E
G
2
3
/
V
L
2
V
L
3
P
2
6
/
S
E
G
2
2
/
V
L
1
P
0
3
/
S
E
G
3
P
0
2
/
S
E
G
2
P
0
1
/
S
E
G
1
P
0
0
/
S
E
G
0
P
2
0
/
S
E
G
1
6
"
0
"
"
1
"
L
C
D
C
K
2
2
5
P
2
7
/
V
L
2
S
E
G
2
3
/
P
2
6
/
V
L
1
S
E
G
2
2
/
D
a
t
a
b
u
s
T
i
m
i
n
g
c
o
n
t
r
o
l
l
e
r
L
C
D
d
i
v
i
d
e
r
(
f
(
X
C
I
N
)
/
8
1
9
2
i
n
l
o
w
-
s
p
e
e
d
m
o
d
e
)
C
o
m
m
o
n
d
r
i
v
e
r
B
i
a
s
c
o
n
t
r
o
l
A
d
d
r
e
s
s
0
0
4
0
1
6
A
d
d
r
e
s
s
0
0
4
1
1
6
L
C
D
C
K
c
o
u
n
t
s
o
u
r
c
e
s
e
l
e
c
t
i
o
n
b
i
t
L
C
D
c
i
r
c
u
i
t
d
i
v
i
d
e
r
d
i
v
i
s
i
o
n
r
a
t
i
o
s
e
l
e
c
t
i
o
n
b
i
t
s
B
i
a
s
c
o
n
t
r
o
l
b
i
t
L
C
D
e
n
a
b
l
e
b
i
t
D
u
t
y
r
a
t
i
o
s
e
l
e
c
t
i
o
n
b
i
t
s
S
e
l
e
c
t
o
r
S
e
l
e
c
t
o
r
S
e
l
e
c
t
o
r
S
e
l
e
c
t
o
r
L
C
D
d
i
s
p
l
a
y
R
A
M
A
d
d
r
e
s
s
0
0
4
C
1
6
S
e
g
m
e
n
t
d
r
i
v
e
r
S
e
g
m
e
n
t
d
r
i
v
e
r
S
e
g
m
e
n
t
d
r
i
v
e
r
S
e
g
m
e
n
t
d
r
i
v
e
r
C
o
m
m
o
n
d
r
i
v
e
r
C
o
m
m
o
n
d
r
i
v
e
r
C
o
m
m
o
n
d
r
i
v
e
r
S
e
l
e
c
t
o
r
S
e
l
e
c
t
o
r
S
e
g
m
e
n
t
d
r
i
v
e
r
S
e
g
m
e
n
t
d
r
i
v
e
r
L
C
D
p
o
w
e
r
c
o
n
t
r
o
l
r
e
g
i
s
t
e
r
37
38C2 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
PRELIMINAR
Y
Notice: This is not a final specification.
Some parametric limits are subject to change.
Duty
ratio
2
3
4
Voltage value
V
L3
=V
LCD
V
L2
=2/3 V
LCD
V
L1
=1/3 V
LCD
V
L3
=V
LCD
V
L2
=V
L1
=1/2 V
LCD
Bias Control and Applied Voltage to LCD Power
Input Pins
When the voltage is applied from the LCD power input pins (V
L1
V
L3
), set the VL pin input selection bit (bit 5 of the LCD power control
register) and V
L3
connection bit (bit 6 of LCD power control register)
to "1", apply the voltage value shown in Table 9 according to the bias
value. In this case, SEG
22
pin and SEG
23
pin cannot be used.
Select a bias value by the bias control bit (bit 2 of the LCD mode
register).
Fig. 34 Example of circuit at each bias (at external power input)
Table 9 Bias control and applied voltage to V
L1
V
L3
Bias value
1/3 bias
1/2 bias
Note : V
LCD
is the maximum value of supplied voltage for the LCD panel.
Table 10 Duty ratio control and common pins used
Note: Unused common pin outputs the unselected waveform.
Common pins used
COM
0
, COM
1
COM
0
COM
2
COM
0
COM
3
Bit 1
0
1
1
Bit 0
1
0
1
Duty ratio selection bit
Common Pin and Duty Ratio Control
The common pins (COM
0
COM
3
) to be used are determined by duty
ratio. Select duty ratio by the duty ratio selection bits (bits 0 and 1 of
the LCD mode register). When reset is released, V
CC
voltage is out-
put from the common pin.
Segment Signal Output Pin
The segment signal output pins (SEG
0
SEG
23
) are shared with ports
P0P2. When these pins are used as the segment signal output pins,
set the direction registers of the corresponding pins to "1", and clear
the segment output disable register to "0".
Also, these pins are set to the input port after reset, the V
CC
voltage
is output by the pull-up resistor.
V
L3
V
L2
V
L1
R
4
R5
R4 = R5
C
o
n
t
r
a
s
t
a
d
j
u
s
t
1/2 bias
V
L
3
V
L
2
V
L
1
C
o
n
t
r
a
s
t
a
d
j
u
s
t
R1
R
2
R3
R
1
=
R
2
=
R
3
1
/
3
b
i
a
s
38
38C2 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
PRELIMINAR
Y
Notice: This is not a final specification.
Some parametric limits are subject to change.
LCD Power Circuit
The LCD power circuit has the dividing resistor for LCD power which
can be connected/disconnected with the LCD power control register.
Fig. 35 Structure of LCD power control register
Dividing resistor for LCD power control bit (LCDRON)
0 : Internal dividing resistor disconnected from LCD power circuit
1 : Internal dividing resistor connected to LCD power circuit
Dividing resistor for LCD power selection bits (RSEL)
b3 b2
1 0 : Larger resistor
0 1 :
0 0 :
1 1 : Smaller resistor
Not used (return "0" when read)
(Do not write to "1")
VL pin input selection bit (VLSEL)
0 : Input invalid
1 : VL input function valid
V
L3
connection bit
0 : Connect LCD internal V
L3
to V
CC
1 : Connect LCD internal V
L3
to V
L3
pin
Not used (return "0" when read)
(Do not write to "1")
LCD power control register
(VLCON : address 0038
16
)
b7
b0
Fig. 36 VL block diagram
V
L
3
P
2
7
/
S
E
G
2
3
/
V
L
2
P
2
6
/
S
E
G
2
2
/
V
L
1
Vcc
L
C
D
m
o
d
e
r
e
g
i
s
t
e
r
(
b
i
t
2
)
L
C
D
p
o
w
e
r
c
o
n
t
r
o
l
r
e
g
i
s
t
e
r
(
b
i
t
5
)
LCD power control
register (bit 0)
D
i
v
i
d
i
n
g
r
e
s
i
s
t
o
r
f
o
r
L
C
D
p
o
w
e
r
L
C
D
p
o
w
e
r
c
o
n
t
r
o
l
r
e
g
i
s
t
e
r
(
b
i
t
s
2
a
n
d
1
)
LCD power control
register (bit 6)
L
C
D
i
n
t
e
r
n
a
l
V
L
3
L
C
D
i
n
t
e
r
n
a
l
V
L
2
L
C
D
i
n
t
e
r
n
a
l
V
L
1
39
38C2 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
PRELIMINAR
Y
Notice: This is not a final specification.
Some parametric limits are subject to change.
(frequency of count source for LCDCK)
(divider division ratio for LCD)
f(LCDCK)=
f(LCDCK)
duty ratio
Frame frequency=
Fig. 37 LCD display RAM map
LCD Display RAM
The 12-byte area of address 0040
16
to 004B
16
is the designated
RAM for the LCD display. When "1" is written to these addresses, the
corresponding segments of the LCD display panel are turned on.
LCD Drive Timing
For the LCD drive timing, type A or type B can be selected.
The LCD drive timing is selected by the timing selection bit (bit 4 of
LCD mode register).
Type A is selected by setting the LCD drive timing selection bit to "0",
type B is selected by setting the bit to "1". Type A is selected after
reset.
The LCDCK timing frequency (LCD drive timing) is generated inter-
nally and the frame frequency can be determined with the following
equation;
s
Note
(1) When the STP instruction is executed, the following bits are
cleared to "0";
LCD enable bit (bit 3 of LCD mode register)
Bits other than bit 6 of the LCD power control register.
(2) When the voltage is applied to V
L1
to V
L3
by using the external
resistor, write "10
2
" to dividing resistor for LCD power selection bits
(RSEL) of the LCD power control register (address 38
16
).
C
O
M
3
C
O
M
2
C
O
M
1
C
O
M
0
Bit
Address
7
6
5
4
3
2
1
0
0040
16
0041
16
0042
16
0043
16
0044
16
0045
16
0046
16
0047
16
0048
16
0049
16
004A
16
004B
16
SEG
1
SEG
3
SEG
5
SEG
7
SEG
9
SEG
11
SEG
13
SEG
15
SEG
17
SEG
19
SEG
21
SEG
23
SEG
0
SEG
2
SEG
4
SEG
6
SEG
8
SEG
10
SEG
12
SEG
14
SEG
16
SEG
18
SEG
20
SEG
22
C
O
M
3
C
O
M
2
C
O
M
1
C
O
M
0
40
38C2 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
PRELIMINAR
Y
Notice: This is not a final specification.
Some parametric limits are subject to change.
Fig. 38 LCD drive waveform (1/2 bias, type A)
1
/
4
d
u
t
y
Voltage level
V
L3
V
L2
=V
L1
V
SS
V
L3
V
SS
C
O
M
0
C
O
M
1
C
O
M
2
C
O
M
3
S
E
G
0
O
F
F
O
N
O
F
F
ON
C
O
M
3
COM
2
COM
1
COM
0
C
O
M
3
COM
2
COM
1
COM
0
1
/
3
d
u
t
y
V
L3
V
L2
=V
L1
V
SS
V
L3
V
SS
OFF
O
N
O
N
OFF
O
N
O
F
F
1
/
2
d
u
t
y
C
O
M
0
C
O
M
1
C
O
M
2
S
E
G
0
COM
0
C
O
M
1
S
E
G
0
V
L3
V
L2
=V
L1
V
SS
V
L3
V
SS
OFF
O
N
O
F
F
O
N
OFF
O
N
OFF
O
N
C
O
M
0
C
O
M
2
COM
1
C
O
M
0
C
O
M
2
COM
1
COM
0
C
O
M
2
C
O
M
1
C
O
M
0
COM
1
COM
0
C
O
M
1
COM
0
COM
1
C
O
M
0
I
n
t
e
r
n
a
l
s
i
g
n
a
l
L
C
D
C
K
t
i
m
i
n
g
LCD
LCD
L
C
D
41
38C2 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
PRELIMINAR
Y
Notice: This is not a final specification.
Some parametric limits are subject to change.
Fig. 39 LCD drive waveform (1/3 bias, type A)
V
L
3
V
SS
C
O
M
0
C
O
M
1
C
O
M
2
C
O
M
3
SEG
0
C
O
M
3
COM
2
COM
1
COM
0
COM
3
COM
2
COM
1
COM
0
C
O
M
0
C
O
M
1
COM
2
S
E
G
0
C
O
M
0
C
O
M
1
S
E
G
0
V
L
3
V
L
2
V
S
S
V
L
1
V
L
3
V
L
2
V
SS
V
L
1
V
L
3
V
SS
V
L
3
V
L
2
V
S
S
V
L1
V
L
3
V
S
S
COM
0
COM
2
COM
1
COM
0
COM
2
COM
1
COM
0
COM
2
C
O
M
1
COM
0
COM
1
COM
0
C
O
M
1
COM
0
COM
1
COM
0
1
/
4
d
u
t
y
Voltage level
O
F
F
ON
OFF
O
N
1
/
3
d
u
t
y
OFF
O
N
O
N
OFF
O
N
OFF
1/2 duty
OFF
O
N
O
F
F
ON
O
F
F
O
N
OFF
O
N
I
n
t
e
r
n
a
l
s
i
g
n
a
l
L
C
D
C
K
t
i
m
i
n
g
LCD
L
C
D
L
C
D
42
38C2 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
PRELIMINAR
Y
Notice: This is not a final specification.
Some parametric limits are subject to change.
Fig. 40 LCD drive waveform (1/2 bias, type B)
C
O
M
0
C
O
M
1
C
O
M
2
C
O
M
3
S
E
G
0
COM
3
COM
2
COM
1
COM
0
COM
3
COM
2
COM
1
COM
0
C
O
M
0
COM
1
C
O
M
2
S
E
G
0
C
O
M
0
C
O
M
1
S
E
G
0
V
L3
V
L2=
V
L1
V
SS
C
O
M
0
C
O
M
2
C
O
M
1
COM
0
C
O
M
2
C
O
M
1
C
O
M
0
C
O
M
2
C
O
M
1
C
O
M
0
COM
1
C
O
M
0
C
O
M
1
COM
0
C
O
M
1
C
O
M
0
1 frame
1
f
r
a
m
e
1 frame
1 frame
1 frame
1 frame
1 frame
1 frame
V
L3
V
SS
V
L3
V
SS
V
L3
V
SS
V
L3
V
L2=
V
L1
V
SS
V
L3
V
L2=
V
L1
V
SS
1/4 duty
V
o
l
t
a
g
e
l
e
v
e
l
OFF
ON
OFF
ON
1
/
3
d
u
t
y
O
F
F
ON
O
N
O
F
F
ON
O
F
F
1
/
2
d
u
t
y
O
F
F
O
N
O
F
F
O
N
O
F
F
O
N
OFF
ON
I
n
t
e
r
n
a
l
s
i
g
n
a
l
L
C
D
C
K
t
i
m
i
n
g
L
C
D
L
C
D
LCD
43
38C2 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
PRELIMINAR
Y
Notice: This is not a final specification.
Some parametric limits are subject to change.
Fig. 41 LCD drive waveform (1/3 bias, type B)
C
O
M
0
C
O
M
1
C
O
M
2
C
O
M
3
SEG
0
C
O
M
3
COM
2
COM
1
COM
0
COM
3
COM
2
COM
1
COM
0
C
O
M
0
C
O
M
1
COM
2
SEG
0
C
O
M
0
C
O
M
1
SEG
0
V
L
3
V
L
2
V
S
S
V
L
1
V
L
3
V
L
2
V
SS
V
L
1
V
L
3
V
L
2
V
S
S
V
L1
COM
0
COM
2
COM
1
COM
0
COM
2
COM
1
COM
0
COM
2
C
O
M
1
COM
0
COM
1
COM
0
C
O
M
1
C
O
M
0
COM
1
C
O
M
0
V
L
3
V
L
2
V
SS
V
L1
V
L3
V
L
2
V
SS
V
L
1
V
L
3
V
L
2
V
S
S
V
L1
1
f
r
a
m
e
1
f
r
a
m
e
1 frame
1 frame
1 frame
1 frame
1 frame
1 frame
1
/
4
d
u
t
y
V
o
l
t
a
g
e
l
e
v
e
l
OFF
ON
OFF
ON
1
/
3
d
u
t
y
O
F
F
O
N
O
N
O
F
F
O
N
O
F
F
1
/
2
d
u
t
y
O
F
F
O
N
O
F
F
ON
OFF
ON
O
F
F
O
N
I
n
t
e
r
n
a
l
s
i
g
n
a
l
L
C
D
C
K
t
i
m
i
n
g
L
C
D
LCD
L
C
D
44
38C2 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
PRELIMINAR
Y
Notice: This is not a final specification.
Some parametric limits are subject to change.
WATCHDOG TIMER
The watchdog timer gives a mean of returning to the reset status
when a program cannot run on a normal loop (for example, because
of a software run-away). The watchdog timer consists of an 8-bit
counter.
Initial Value of Watchdog Timer
At reset or writing to the watchdog timer control register, each watch-
dog timer is set to "FF
16
." Instructions such as STA, LDM and CLB to
generate the write signals can be used.
The written data in bits 0 to 5 are not valid, and the above values are
set.
Standard Operation of Watchdog Timer
The watchdog timer is in the stop state at reset and the watchdog
timer starts to count down by writing an optional value in the watch-
dog timer control register. An internal reset occurs at an underflow of
the watchdog timer. Then, reset is released after the reset release
time is elapsed, the program starts from the reset vector address.
Normally, writing to the watchdog timer control register before an
underflow of the watchdog timer is programmed. If writing to the watch-
dog control register is not executed, the watchdog timer does not
operate.
Fig. 44 Timing diagram of reset output
When reading the watchdog timer control register is executed, the
contents of the high-order 6-bit counter and the STP instruction dis-
able bit (bit 6), and the count source selection bit (bit 7) are read out.
When the STP instruction disable bit is "0", the STP instruction is
valid. The STP instruction is disabled by writing to "1" to this bit. In
this time, when the STP instruction is executed, it is handled as the
undefined instruction, the internal reset occurs. This bit cannot be
cleared to "0" by program. This bit is "0" after reset.
The time until the underflow of the watchdog timer control register
after writing to the watchdog timer control register is executed is as
follows (when the bit 7 of the watchdog timer control register is "0") ;
at through, frequency/2/4/8 mode (f(X
IN
)) = 8 MHz): 32.768 ms
at low-speed mode (f(X
CIN
) = 32 KHz): 8.19s
s
Note
The watchdog timer continues to count even during the wait time set
by timer 1 and timer 2 to release the stop state and in the wait mode.
Accordingly, do not underflow the watchdog timer in this time.
Fig. 42 Block diagram of Watchdog timer
Fig. 43 Structure of Watchdog timer control register
b0
STP instruction disable bit
0: STP instruction enabled
1: STP instruction disabled
Watchdog timer count source selection bit
0: 1/1024 of system clock
1: 1/4 of system clock
Watchdog timer H (for read-out of high-order 6 bit)
"FF
16
" is set to watchdog timer by writing to these bits.
Watchdog timer control register
(WDTCON : address 0037
16
)
b7
I
n
t
e
r
n
a
l
r
e
s
e
t
s
i
g
n
a
l
Watchdog timer detected
32
msec
(at f(X
IN
)=8MH
Z
)
f
(
X
I
N
)
X
IN
X
C
I
N
Sy
s
t
e
m
c
l
o
c
k
c
o
n
t
r
o
l
b
i
t
(
b
i
t
6
)
1/1024
U
n
d
e
f
i
n
e
d
i
n
s
t
r
u
c
t
i
o
n
R
e
s
e
t
R
E
S
E
T
I
N
Wait until reset release
1
/
4
D
a
t
a
b
u
s
W
a
t
c
h
d
o
g
t
i
m
e
r
H
c
o
u
n
t
s
o
u
r
c
e
s
e
l
e
c
t
i
o
n
b
i
t
R
e
s
e
t
c
i
r
c
u
i
t
S
T
P
i
n
s
t
r
u
c
t
i
o
n
d
i
s
a
b
l
e
b
i
t
Watchdog timer
H (6)
Internal reset
S
T
P
i
n
s
t
r
u
c
t
i
o
n
Watchdog timer
L (2)
"
F
F
1
6
"
i
s
s
e
t
w
h
e
n
w
a
t
c
h
d
o
g
t
i
m
e
r
c
o
n
t
r
o
l
r
e
g
i
s
t
e
r
i
s
w
r
i
t
t
e
n
t
o
.
"1"
"0"
"0"
"1"
45
38C2 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
PRELIMINAR
Y
Notice: This is not a final specification.
Some parametric limits are subject to change.
CLOCK OUTPUT FUNCTION
A system clock
can be output from I/O port P3
6
.The triple function
of I/O port, timer 2 output function and system clock
output function
is performed by the clock output control register (address 0018
16
)
and the timer 2 output selection bit of the timer 12 mode register
(address 0025
16
).
In order to output a system clock
from I/O port P3
6
, set the timer 2
output selection bit and bit 0 of the clock output control register to "1".
When the clock output function is selected, a clock is output while
the direction register of port P3
6
is set to the output mode.
P3
6
is switched to the port output or the output (timer 2 output and
the clock output) except port at the cycle after the timer 2 output
control bit is switched.
Fig. 46 Block diagram of Clock output function
Fig. 45 Structure of clock output control register
b0
Not used (returns "0" when read)
P3
6
clock output control bit
0: Timer 2 output
1: System clock
output
Clock output control register
(CKOUT : address 0018
16
)
b7
T
i
m
e
r
2
l
a
t
c
h
(
8
)
T
i
m
e
r
2
(
8
)
1
/
2
Q
Q
S
T
T
2
O
U
T
o
u
t
p
u
t
e
d
g
e
s
w
i
t
c
h
b
i
t
T
i
m
e
r
2
o
u
t
p
u
t
c
o
n
t
r
o
l
b
i
t
P
3
6
l
a
t
c
h
T
i
m
e
r
2
o
u
t
p
u
t
s
e
l
e
c
t
i
o
n
b
i
t
P
3
6
d
i
r
e
c
t
i
o
n
r
e
g
i
s
t
e
r
P
3
6
/
T
2
O
U
T
/
S
y
s
t
e
m
c
l
o
c
k
P
3
6
c
l
o
c
k
o
u
t
p
u
t
c
o
n
t
r
o
l
b
i
t
b
7
b
0
T
i
m
e
r
1
2
m
o
d
e
r
e
g
i
s
t
e
r
(
a
d
d
r
e
s
s
0
0
2
5
1
6
)
T
1
2
M
T
i
m
e
r
2
o
u
t
p
u
t
s
e
l
e
c
t
i
o
n
b
i
t
0
:
I
/
O
p
o
r
t
1
:
T
i
m
e
r
2
o
u
t
p
u
t
"
0
"
"
1
"
"
0
"
"
1
"
46
38C2 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
PRELIMINAR
Y
Notice: This is not a final specification.
Some parametric limits are subject to change.
RESET CIRCUIT
To reset the microcomputer, RESET pin should be held at an "L"
level for 2
s or more. Then the RESET pin is returned to an "H" level
(the power source voltage should be between V
CC
(min.) and 5.5 V,
and the quartz-crystal oscillator should be stable), reset is released.
After the reset is completed, the program starts from the address
contained in address FFFD
16
(high-order byte) and address FFFC
16
(low-order byte). Make sure that the reset input voltage meets V
IL
spec. when a power source voltage passes V
CC
(min.).
Fig. 48 Reset sequence
Fig. 47 Reset circuit example
V
IL
spec.
0V
0V
Poweron
V
CC
RESET
V
CC
RESET
Power source
voltage detection
circuit
Power source
voltage
Reset input
voltage
RESET
Internal
reset
Address
Data
SYNC
X
IN
FFFC
FFFD
AD
H,
AD
L
AD
L
?
?
?
?
X
IN
: about 8000 cycles
Note
Reset address from
vector table
1: The frequency relation of f(X
IN
) and f(
) is f(X
IN
) = 8 f(
).
2: The question marks (?) indicate an undefined state that depends on the previous state.
AD
H
47
38C2 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
PRELIMINAR
Y
Notice: This is not a final specification.
Some parametric limits are subject to change.
Fig. 49 Internal status at reset
FF
16
FF
16
00
16
002A
16
0
0
2
B
1
6
0
0
2
C
1
6
0
0
3
7
1
6
0
0
3
8
1
6
0
0
3
A
1
6
X: Not fixed
Since the initial values for other than above mentioned registers and
RAM contents are indefinite at reset, they must be set.
A
d
d
r
e
s
s
R
e
g
i
s
t
e
r
c
o
n
t
e
n
t
s
A
d
d
r
e
s
s
R
e
g
i
s
t
e
r
c
o
n
t
e
n
t
s
00
16
00
16
00
16
00
16
00
16
00
16
00
16
00
16
00
16
00
16
00
16
00
16
00
16
00
16
00
16
FF
16
FF
16
00
16
0
0
0
0
1
6
0
0
0
1
1
6
0
0
0
2
1
6
0
0
0
4
1
6
0
0
0
5
1
6
0
0
0
6
1
6
0
0
0
8
1
6
0
0
0
9
1
6
000A
16
0
0
0
B
1
6
0
0
0
C
1
6
0
0
0
D
1
6
0018
16
0
0
1
9
1
6
001D
16
0
0
1
F
1
6
0020
16
0
0
2
1
1
6
0022
16
0
0
2
3
1
6
0024
16
0025
16
0
0
2
8
1
6
C
o
m
p
a
r
e
r
e
g
i
s
t
e
r
(
l
o
w
-
o
r
d
e
r
)
P
o
r
t
P
0
P
o
r
t
P
0
d
i
r
e
c
t
i
o
n
r
e
g
i
s
t
e
r
P
o
r
t
P
1
P
o
r
t
P
2
P
o
r
t
P
2
d
i
r
e
c
t
i
o
n
r
e
g
i
s
t
e
r
P
o
r
t
P
3
P
o
r
t
P
4
P
o
r
t
P
4
d
i
r
e
c
t
i
o
n
r
e
g
i
s
t
e
r
Port P5
P
o
r
t
P
5
d
i
r
e
c
t
i
o
n
r
e
g
i
s
t
e
r
P
o
r
t
P
6
P
o
r
t
P
6
d
i
r
e
c
t
i
o
n
r
e
g
i
s
t
e
r
Clock output control register
A-D control register
S
e
r
i
a
l
I
/
O
1
s
t
a
t
u
s
r
e
g
i
s
t
e
r
Timer 2
T
i
m
e
r
3
Timer 4
PWM01 register
T
i
m
e
r
1
2
m
o
d
e
r
e
g
i
s
t
e
r
Timer 34 mode register
C
o
m
p
a
r
e
r
e
g
i
s
t
e
r
(
h
i
g
h
-
o
r
d
e
r
)
T
i
m
e
r
X
(
l
o
w
-
o
r
d
e
r
)
Timer X (high-order)
(1)
(2)
(3)
(5)
(6)
(7)
(8)
(9)
(10)
(11)
(12)
(13)
(14)
(15)
(16)
(17)
(18)
(19)
(20)
(21)
(22)
(23)
(24)
(25)
(26)
(27)
(28)
(29)
00
16
0029
16
T
i
m
e
r
X
(
e
x
t
e
n
s
i
o
n
)
(30)
(
3
2
)
(33)
(
3
5
)
(
3
6
)
(
3
7
)
(
3
8
)
T
i
m
e
r
Y
(
l
o
w
-
o
r
d
e
r
)
T
i
m
e
r
Y
(
h
i
g
h
-
o
r
d
e
r
)
T
i
m
e
r
X
m
o
d
e
r
e
g
i
s
t
e
r
W
a
t
c
h
d
o
g
t
i
m
e
r
c
o
n
t
r
o
l
r
e
g
i
s
t
e
r
L
C
D
p
o
w
e
r
c
o
n
t
r
o
l
r
e
g
i
s
t
e
r
L
C
D
m
o
d
e
r
e
g
i
s
t
e
r
I
n
t
e
r
r
u
p
t
e
d
g
e
s
e
l
e
c
t
i
o
n
r
e
g
i
s
t
e
r
0
0
1
6
00
16
00
16
0
0
3
B
1
6
0
0
3
C
1
6
0
0
3
F
1
6
0
F
E
0
1
6
0
F
E
1
1
6
0
F
E
3
1
6
0FE4
16
(
3
9
)
(
4
0
)
(
4
3
)
(44)
(
4
5
)
(
4
6
)
(47)
CPU mode register
I
n
t
e
r
r
u
p
t
r
e
q
u
e
s
t
r
e
g
i
s
t
e
r
1
I
n
t
e
r
r
u
p
t
r
e
q
u
e
s
t
r
e
g
i
s
t
e
r
2
Interrupt control register 1
I
n
t
e
r
r
u
p
t
c
o
n
t
r
o
l
r
e
g
i
s
t
e
r
2
0
0
1
6
0
0
1
6
0
0
1
6
Serial I/O2 status register
T
i
m
e
r
1
(
3
1
)
FFFC
16
contents
(PS)
(
P
C
H
)
(
P
C
L
)
P
r
o
g
r
a
m
c
o
u
n
t
e
r
P
r
o
c
e
s
s
o
r
s
t
a
t
u
s
r
e
g
i
s
t
e
r
F
F
F
D
1
6
c
o
n
t
e
n
t
s
1
0039
16
08
16
FF
16
01
16
FF
16
FF
16
00
16
00
16
00
16
00
16
0
0
0
3
1
6
P
o
r
t
P
1
d
i
r
e
c
t
i
o
n
r
e
g
i
s
t
e
r
(4)
0
0
3
E
1
6
(
4
1
)
(
4
2
)
0
0
1
6
0
0
1
6
0
0
3
D
1
6
0
0
1
6
00
16
00
16
0
F
F
0
1
6
0
F
F
1
1
6
0
F
F
2
1
6
0
F
F
3
1
6
(
4
8
)
(49)
(50)
(51)
0
0
1
6
0
0
1
6
0
F
F
4
1
6
0FF5
16
0FF6
16
(
5
2
)
(53)
(54)
00
16
0
0
1
6
0
0
1
6
F
F
1
6
0
F
F
7
1
6
0
F
F
8
1
6
0
F
F
9
1
6
(
5
5
)
(56)
(
5
7
)
F
F
1
6
F
F
1
6
0FFA
16
0FFB
16
0
F
F
E
1
6
(58)
(
5
9
)
(60)
0
0
1
6
(61)
(
6
2
)
P
o
r
t
P
3
d
i
r
e
c
t
i
o
n
r
e
g
i
s
t
e
r
0
0
0
7
1
6
0
0
2
6
1
6
0
0
2
D
1
6
0
0
2
E
1
6
002F
16
1 0 0 0 0 0
0
0
1 0 0 0 0 0
0
0
00
16
(
3
4
) Timer Y mode register
0
0
3
0
1
6
S
e
r
i
a
l
I
/
O
1
c
o
n
t
r
o
l
r
e
g
i
s
t
e
r
U
A
R
T1
c
o
n
t
r
o
l
r
e
g
i
s
t
e
r
S
e
r
i
a
l
I
/
O
2
c
o
n
t
r
o
l
r
e
g
i
s
t
e
r
U
A
R
T
2
c
o
n
t
r
o
l
r
e
g
i
s
t
e
r
O
s
c
i
l
l
a
t
i
o
n
o
u
t
p
u
t
c
o
n
t
r
o
l
r
e
g
i
s
t
e
r
PULL register
K
e
y
i
n
p
u
t
c
o
n
t
r
o
l
r
e
g
i
s
t
e
r
Timer 1234 mode register
T
i
m
e
r
X
c
o
n
t
r
o
l
r
e
g
i
s
t
e
r
T
i
m
e
r
1
2
f
r
e
q
u
e
n
c
y
d
i
v
i
s
i
o
n
s
e
l
e
c
t
i
o
n
r
e
g
i
s
t
e
r
T
i
m
e
r
3
4
f
r
e
q
u
e
n
c
y
d
i
v
i
s
i
o
n
s
e
l
e
c
t
i
o
n
r
e
g
i
s
t
e
r
Timer XY frequency division selection register
S
e
g
m
e
n
t
o
u
t
p
u
t
d
i
s
a
b
l
e
r
e
g
i
s
t
e
r
0
S
e
g
m
e
n
t
o
u
t
p
u
t
d
i
s
a
b
l
e
r
e
g
i
s
t
e
r
1
Segment output disable register 2
T
i
m
e
r
Y
m
o
d
e
r
e
g
i
s
t
e
r
2
F
l
a
s
h
m
e
m
o
r
y
c
o
n
t
r
o
l
r
e
g
i
s
t
e
r
0 0 1 1 1 1
1
1
0 1 0 0 1 0
0
0
0
0
1
6
1 1 1 0 0 0
0
0
1 1 1 0 0 0
0
0
1
0
0
0
0
48
38C2 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
PRELIMINAR
Y
Notice: This is not a final specification.
Some parametric limits are subject to change.
CLOCK GENERATING CIRCUIT
The 38C2 group has two built-in oscillation circuits; main clock X
IN
X
OUT
and sub-clock X
CIN
X
COUT
. An oscillation circuit can be formed
by connecting a resonator between X
IN
and X
OUT
(X
CIN
and X
COUT
).
Use the circuit constants in accordance with the resonator
manufacturer's recommended values. No external resistor is needed
between X
IN
and X
OUT
since a feedback resistor exists on-chip. How-
ever, an external feedback resistor is needed between X
CIN
and
X
COUT
.
When the clock signal is supplied from external for the main clock,
input the signal to X
IN
pin and input the inverted-phase signal of X
IN
to X
OUT
pin by the external inverter.
When the clock signal is supplied from external for the sub-clock,
input the signal to X
CIN
and leave X
COUT
open.
Immediately after power on, only the X
IN
oscillation circuit starts os-
cillating.
Frequency Control
(1) Frequency/8 Mode
The system clock
is the frequency of X
IN
divided by 8. After reset is
released, this mode is selected.
(2) Frequency/4 Mode
The system clock
is the frequency of X
IN
divided by 4.
(3) Frequency/2 Mode
The system clock
is the frequency of X
IN
divided by 2.
(4) Through Mode
The system clock
is the frequency of X
IN
.
(5) Low-speed Mode
The system clock
is the frequency of X
CIN
divided by 2. In the low-
speed mode, the low-power dissipation operation can be performed
when the main clock X
IN
is stopped by setting the bit 7 of the CPU
mode register to "0". In this case, when main clock X
IN
oscillation is
restarted, generate the wait time until the oscillation is stable by pro-
gram after the bit 7 of the CPU mode register is set to "1".
Fig. 50 Ceramic resonator circuit
Fig. 51 External clock input circuit
X
O
U
T
C
I
N
C
O
U
T
C
C
I
N
C
C
O
U
T
R
f
c
X
C
I
N
X
C
O
U
T
X
I
N
X
C
I
N
X
C
O
U
T
X
I
N
X
O
U
T
E
x
t
e
r
n
a
l
o
s
c
i
l
l
a
t
i
o
n
c
i
r
c
u
i
t
V
C
C
V
S
S
O
p
e
n
V
C
C
V
S
S
E
x
t
e
r
n
a
l
o
s
c
i
l
l
a
t
i
o
n
c
i
r
c
u
i
t
,
o
r
E
x
t
e
r
n
a
l
p
u
l
s
e
s
Notes on Clock Generating Circuit
If you switch the mode between through, frequency/2/4, or 8 and
low-speed, stabilize both X
IN
and X
CIN
oscillations. The sufficient time
is required for the sub-clock to stabilize, especially immediately after
power on and at returning from stop mode. When switching the mode,
set the frequency on condition that f(X
IN
) > 3f(X
CIN
).
Oscillation Control
(1) Stop Mode
If the STP instruction is executed, the system clock
stops at an "H"
level, and main clock and sub-clock oscillators stop.
In this time, values set previously to timer 1 latch and timer 2 latch
are loaded automatically to timer 1 and timer 2. Set the values to
generate the wait time required for oscillation stabilization to timer 1
latch and timer 2 latch (low-order 8 bits of timer 1 and high-order 8
bits of timer 2) before the STP instruction.
The frequency divider for timer 1 is used for the timer 1 count source,
and the output of timer 1 is forcibly connected to timer 2. In this time,
bits 0 to 5 of the timer 12 mode register are cleared to "0".
The values of the timer 12 frequency divider selection register are
not changed.
Set the interrupt enable bits of the timer 1 and timer 2 to disabled
("0") before executing the STP instruction.
Oscillator restarts When reset occurs or an interrupt request is re-
ceived, but the system clock
is not supplied to the CPU until timer
2 underflows. This allows time for the clock circuit oscillation to stabi-
lize.
(2) Wait Mode
If the WIT instruction is executed, the system clock
stops at an "H"
level. The states of X
IN
and X
CIN
are the same as the state before
executing the WIT instruction. The system clock
restarts at reset or
when an interrupt is received. Since the oscillator does not stop, nor-
mal operation can be started immediately after the clock is restarted.
49
38C2 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
PRELIMINAR
Y
Notice: This is not a final specification.
Some parametric limits are subject to change.
Fig. 52 Clock generating circuit block diagram
S
R
Q
S
R
Q
S
R
Q
X
I
N
X
O
U
T
1
/
2
1
/
2
1
/
2
1
/
2
P6
1
/X
CIN
P
6
2
/
X
C
O
U
T
T
i
m
e
r
1
c
o
u
n
t
s
o
u
r
c
e
s
e
l
e
c
t
i
o
n
b
i
t
s
Through mode
"01"
"00"
"
1
1
"
"
0
1
"
"
0
0
"
"00"
"
1
0
"
T
i
m
e
r
2
c
o
u
n
t
s
o
u
r
c
e
s
e
l
e
c
t
i
o
n
b
i
t
s
"
0
0
,
1
0
,
1
1
"
"01"
"01,10,11"
"
0
0
"
"10"
"
0
0
,
1
0
"
"
0
0
,
1
0
"
"
0
1
,
1
1
"
"01,11"
WIT instruction
System clock
STP instruction
T
i
m
e
r
2
T
i
m
e
r
1
I
n
t
e
r
r
u
p
t
r
e
q
u
e
s
t
Reset
System clock
control bits
Main clock
division ratio
selection bits
Interrupt disable flag I
STP instruction
S
y
s
t
e
m
c
l
o
c
k
c
o
n
t
r
o
l
b
i
t
s
System clock
control bits
S
y
s
t
e
m
c
l
o
c
k
c
o
n
t
r
o
l
b
i
t
s
F
r
e
q
u
e
n
c
y
d
i
v
i
d
e
r
f
o
r
T
i
m
e
r
Frequency/8 mode
Frequency/4 mode
F
r
e
q
u
e
n
c
y
/
2
m
o
d
e
"00"
"
0
0
,
1
0
,
1
1
"
"
0
1
"
System clock
control bits
50
38C2 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
PRELIMINAR
Y
Notice: This is not a final specification.
Some parametric limits are subject to change.
Fig. 53 State transitions of system clock
X
I
N
o
s
c
i
l
l
a
t
i
o
n
,
X
C
I
N
s
t
o
p
C
M
7
=
0
,
C
M
6
=
1
S
y
s
t
e
m
c
l
o
c
k
:
f
(
X
I
N
)
C
M
5
=
1
C
M
4
=
1
T
h
r
o
u
g
h
m
o
d
e
F
r
e
q
u
e
n
c
y
/
2
m
o
d
e
S
y
s
t
e
m
c
l
o
c
k
:
f
(
X
I
N
)
/
2
C
M
5
=
1
C
M
4
=
0
CM
7
="0"
CM
6
="1"
L
o
w
-
s
p
e
e
d
m
o
d
e
S
y
s
t
e
m
c
l
o
c
k
:
f
(
X
C
I
N
)
/
2
X
I
N
s
t
o
p
,
X
C
I
N
o
s
c
i
l
l
a
t
i
o
n
C
M
7
=
0
,
C
M
6
=
0
L
o
w
-
p
o
w
e
r
d
i
s
s
i
p
a
t
i
o
n
m
o
d
e
S
y
s
t
e
m
c
l
o
c
k
:
f
(
X
C
I
N
)
/
2
CM
7
="1"
CM
7
="0"
CM
6
="0"
S
y
s
t
e
m
c
l
o
c
k
=
M
a
i
n
c
l
o
c
k
f
(
X
I
N
)
R
e
s
e
t
CM
5
CM
4
: Main clock division ratio selection bits
00: X
IN
/8 (frequency/8)
01: X
IN
/4 (frequency/4)
10: X
IN
/2 (frequency/2)
11: X
IN
(through mode)
CM
7
CM
6
: System clock control bits
00: X
IN
stop, X
CIN
oscillation, system clock = X
CIN
01: X
IN
oscillation, X
CIN
stop, system clock = X
IN
10: X
IN
oscillation, X
CIN
oscillation, system clock = X
CIN
11: X
IN
oscillation, X
CIN
oscillation, system clock = X
IN
CPU mode register
(CPUM : address 003B
16
)
b7
b4
1: When the mode is switched from through or frequency/2/4/8 to the low-speed mode,
or the opposite is performed, change CM
7
at first, and then, change CM
6
after the oscillation of
the changed mode is stabilized.
2: The all modes can be switched to the stop mode or the wait mode and return to the source mode
when the stop mode or the wait mode is ended.
3: Timer and LCD operate in the wait mode.
4: When the stop mode is ended, a delay time can be set by connecting timer 1 and timer 2.
N
o
t
e
s
Frequency/4 mode
F
r
e
q
u
e
n
c
y
/
8
m
o
d
e
S
y
s
t
e
m
c
l
o
c
k
:
f
(
X
I
N
)
/
4
C
M
5
=
0
C
M
4
=
1
S
y
s
t
e
m
c
l
o
c
k
:
f
(
X
I
N
)
/
8
C
M
5
=
0
C
M
4
=
0
CM
7
="1"
X
IN
oscillation, X
CIN
oscillation
CM
7
=1, CM
6
=1
T
h
r
o
u
g
h
m
o
d
e
F
r
e
q
u
e
n
c
y
/
2
m
o
d
e
Frequency/4 mode
F
r
e
q
u
e
n
c
y
/
8
m
o
d
e
S
y
s
t
e
m
c
l
o
c
k
:
f
(
X
I
N
)
C
M
5
=
1
C
M
4
=
1
System clock
: f(X
IN
)/2
CM
5
=1
CM
4
=0
S
y
s
t
e
m
c
l
o
c
k
:
f
(
X
I
N
)
/
4
C
M
5
=
0
C
M
4
=
1
System clock
: f(X
IN
)/8
CM
5
=0
CM
4
=0
S
y
s
t
e
m
c
l
o
c
k
=
S
u
b
-
c
l
o
c
k
f
(
X
C
I
N
)
X
I
N
o
s
c
i
l
l
a
t
i
o
n
,
X
C
I
N
o
s
c
i
l
l
a
t
i
o
n
C
M
7
=
1
,
C
M
6
=
1
51
38C2 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
PRELIMINAR
Y
Notice: This is not a final specification.
Some parametric limits are subject to change.
Oscillation External Output Function
The 38C2 group has the oscillation external output function to output
the rectangular waveform of the clock obtained by the oscillation cir-
cuits from P4
1
and P4
0
.
In order to validate the oscillation external output function, set P4
0
or
P4
1
, or both to the output mode (set the corresponding direction reg-
ister to "1").
The level of the X
COUT
external output signal becomes "H" by the
P4
0
/P4
1
oscillation output control bits (bits 0 and 1) of the oscillation
output control register (address 0FF0
16
) in the following states;
the function to output the signal from the X
COUT
pin externally is
selected
the sub-clock (X
CIN
X
COUT
) is in the oscillating or stop mode.
Likewise, the level of the X
OUT
external output signal becomes "H"
by the P4
0
/P4
1
oscillation output control bits (bits 0 and 1) of the
oscillation output control register (address 0FF0
16
) in the following
states;
the function to output the signal from the X
OUT
pin externally is
selected
the main clock (X
IN
X
OUT
) is in the oscillating or stop mode.
Fig. 55 Block diagram of Oscillation output function
Fig. 54 Structure of oscillation output control register
Oscillation output control register
P4
0
/P4
1
oscillation output control bits
b1b0
00: P4
1
, P4
0
= Normal port
01: P4
1
= Normal port, P4
0
= X
OUT
10: P4
1
= Normal port, P4
0
= X
COUT
11: P4
1
= X
COUT
, P4
0
= X
OUT
Not used (return "0" when read)
(Do not write to "1")
(OSCOUT : address 0FF0
16
)
b7
b0
STP instruction
S
R
Q
X
I
N
X
O
U
T
I
n
t
e
r
r
u
p
t
r
e
q
u
e
s
t
I
n
t
e
r
r
u
p
t
d
i
s
a
b
l
e
f
l
a
g
I
R
e
s
e
t
Sy
s
t
e
m
c
l
o
c
k
c
o
n
t
r
o
l
b
i
t
s
P6
1
/X
CIN
P6
2
/X
COUT
System clock control bits
"01"
Sy
s
t
e
m
c
l
o
c
k
c
o
n
t
r
o
l
b
i
t
s
P
4
1
/
O
O
U
T
1
P
4
0
/
O
O
U
T
0
P4
1
direction register
P4
0
direction register
OSCOUT control
P4
1
output latch
P4
0
output latch
O
s
c
i
l
l
a
t
i
o
n
o
u
t
p
u
t
s
e
l
e
c
t
i
o
n
c
i
r
c
u
i
t
"
0
0
"
,
"
1
0
"
,
"
1
1
"
"
0
1
"
"00", "10", "11"
"
0
0
"
"
0
1
"
,
"
1
0
"
,
"
1
1
"
s
Note
When the signal from the X
OUT
pin or X
COUT
pin of the oscillation
circuit is input directly to the circuit except this MCU and used, the
system operation may be unstabilized.
In order to share the oscillation circuit safely, use the clock output
from P4
0
and P4
1
by this function for the circuits except this MCU.
52
38C2 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
PRELIMINAR
Y
Notice: This is not a final specification.
Some parametric limits are subject to change.
NOTES ON PROGRAMMING
Processor Status Register
The contents of the processor status register (PS) after a reset are
undefined, except for the interrupt disable flag (I) which is "1." After a
reset, initialize flags which affect program execution. In particular, it
is essential to initialize the index X mode (T) and the decimal mode
(D) flags because of their effect on calculations.
Interrupts
The contents of the interrupt request bits do not change immediately
after they have been written. After writing to an interrupt request reg-
ister, execute at least one instruction before performing a BBC or
BBS instruction.
Decimal Calculations
To calculate in decimal notation, set the decimal mode flag (D) to
"1," then execute an ADC or SBC instruction. After executing an
ADC or SBC instruction, execute at least one instruction before
executing an SEC, CLC, or CLD instruction.
In decimal mode, the values of the negative (N), overflow (V), and
zero (Z) flags are invalid.
Timers
If a value n (between 0 and 255) is written to a timer latch, the
frequency division ratio is 1/(n+1).
The timers share the one frequency divider to generate the count
source. Accordingly, when each timer starts operating, initializing
the frequency divider is not executed. Therefore, when the frequency
divider is selected for the count source, the delay of the maximum
one cycle of the count source is generated until the timer starts
counting or the waveform is output from timer starts operating. Also,
the count source cannot be checked externally.
Multiplication and Division Instructions
The index X mode (T) and the decimal mode (D) flags do not affect
the MUL and DIV instruction.
The execution of these instructions does not change the contents
of the processor status register.
Ports
The contents of the port direction registers cannot be read. The fol-
lowing cannot be used:
The data transfer instruction (LDA, etc.)
The operation instruction when the index X mode flag (T) is "1"
The addressing mode which uses the value of a direction register
as an index
The bit-test instruction (BBC or BBS, etc.) to a direction register
The read-modify-write instructions (ROR, CLB, or SEB, etc.) to a
direction register.
Use instructions such as LDM and STA, etc., to set the port direction
registers.
Serial I/O
In clock synchronous serial I/O, if the receive side is using an exter-
nal clock and it is to output the S
RDY
signal, set the transmit enable
bit, the receive enable bit, and the S
RDY
output enable bit to "1."
Serial I/O continues to output the final bit from the T
X
D pin after trans-
mission is completed.
A-D Converter
The comparator uses internal capacitors whose charge will be lost if
the clock frequency is too low.
Therefore, make sure that f(X
IN
) is at least on 250 kHz (Note) during
an A-D conversion.
Note: When the frequency divided by 2/4/8 is selected by the AD
conversion clock selection bits, the above frequency is multi-
plied by 2/4/8. Also, when the STP instruction is executed dur-
ing the A-D conversion, the A-D conversion is stopped imme-
diately, the A-D conversion completion bit is set to "1", and the
interrupt request is generated.
LCD
When the LCD power input pin V
L3
is not used, connect it to V
CC
.
Instruction Execution Time
The instruction execution time is obtained by multiplying the number
of cycles shown in the list of machine instructions by the period of the
internal clock
.
53
38C2 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
PRELIMINAR
Y
Notice: This is not a final specification.
Some parametric limits are subject to change.
ELECTRICAL CHARACTERISTICS
Absolute Maximum Ratings
Table 11 Absolute maximum ratings (Mask ROM version)
Parameter
Power source voltage
Input voltage
P0
0
P0
7
, P1
0
P1
7
, P2
0
P2
7,
P3
0
P3
7,
P4
0
P4
7
, P5
0
P5
7,
P6
0
P6
2
Input voltage
V
L1
Input voltage
V
L2
Input voltage
V
L3
Input voltage
RESET, X
IN
, CNV
SS
Output voltage P0
0
P0
7
, P1
0
P1
7
, P2
0
P2
7
Output voltage COM
0
COM
3
Output voltage P3
0
P3
7
, P4
0
P4
7,
P5
0
P5
7
, P6
0
P6
2
Output voltage X
OUT
Power dissipation
Operating temperature
Storage temperature
Symbol
V
CC
V
I
V
I
V
I
V
I
V
I
V
O
V
O
V
O
V
O
P
d
T
opr
T
stg
Conditions
All voltages are based on Vss.
Output transistors are cut off.
At output port
At segment output
Ta = 25
C
Ratings
0.3 to 6.5
0.3 to V
CC
+0.3
0.3 to V
L2
V
L1
to V
L3
V
L2
to 6.5
0.3 to V
CC
+0.3
0.3 to V
CC
+0.3
0.3 to V
L3
+0.3
0.3 to V
L3
+0.3
0.3 to V
CC
+0.3
0.3 to V
CC
+0.3
300
20 to 85
40 to 125
Unit
V
V
V
V
V
V
V
V
V
V
V
mW
C
C
Recommended Operating Conditions
Table 12 Recommended operating conditions (Mask ROM version)
(Vcc = 1.8 to 5.5 V, Ta = 20 to 85
C, unless otherwise noted)
Power source voltage
f(
) = 8 MHz
f(
) = 2 MHz
Low-speed mode
Power source voltage
A-D converter reference voltage
Analog power source voltage
Analog input voltage AN
0
AN
7
"H" input voltage
P0
4
P0
7
, P1
0
P1
7
, P2
0
P2
7
, P3
0
, P3
2
, P3
5
,
P3
6
, P4
0
P4
7
, P5
2
, P5
3
, P6
2
"H" input voltage
P0
0
P0
3
, P3
1
, P3
3
, P3
4
, P3
7
, P5
0
, P5
1,
P5
4
P5
7
, P6
0
, P6
1
"H" input voltage
RESET
"H" input voltage
X
IN
, X
CIN
"L" input voltage
P0
4
P0
7
, P1
0
P1
7
, P2
0
P2
7
, P3
0
, P3
2
, P3
5
,
P3
6
, P4
0
P4
7
, P5
2
, P5
3
, P6
2
"L" input voltage
P0
0
P0
3
, P3
1
, P3
3
, P3
4
, P3
7
, P5
0
, P5
1,
P5
4
P5
7
, P6
0
, P6
1
, CNV
SS
"L" input voltage
RESET
"L" input voltage
X
IN
, X
CIN
V
CC
V
SS
V
REF
AV
SS
V
IA
V
IH
V
IH
V
IH
V
IH
V
IL
V
IL
V
IL
V
IL
Limits
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
Parameter
Min.
4.0
1.8
1.8
V
CC
0.3
AV
SS
0.7V
CC
0.8V
CC
0.9V
CC
65
V
CC
99
100
1.5
0
0
0
0
0
Typ.
5.0
5.0
5.0
0
0
Max.
5.5
5.5
5.5
V
CC
+0.3
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
0.3V
CC
0.2V
CC
0.2V
CC
65
V
CC
99
100
0.4
Symbol
Unit
2.2 V
V
CC
5.5 V
V
CC
2.2 V
2.2 V
V
CC
5.5 V
V
CC
2.2 V
V
CC
54
38C2 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
PRELIMINAR
Y
Notice: This is not a final specification.
Some parametric limits are subject to change.
"H" total peak output current (Note 1)
P0
0
P0
7
, P1
0
P1
7
, P2
0
P2
7
, P3
0
P3
7
"H" total peak output current (Note 1)
P4
0
P4
7
, P5
0
P5
7
, P6
0
P6
2
"L" total peak output current (Note 1)
P0
0
P0
7
, P1
0
P1
7
, P2
0
P2
7
"L" total peak output current (Note 1)
P4
0
P4
7
, P5
0
, P5
1
, P5
4
P5
7
, P6
0
P6
2
"L" total peak output current (Note 1)
P3
0
P3
7
, P5
2
, P5
3
"H" total average output current (Note 1)
P0
0
P0
7
, P1
0
P1
7
, P2
0
P2
7
, P3
0
P3
7
"H" total average output current (Note 1)
P4
0
P4
7
, P5
0
P5
7
, P6
0
P6
2
"L" total average output current (Note 1)
P0
0
P0
7
, P1
0
P1
7
, P2
0
P2
7
"L" total average output current (Note 1)
P4
0
P4
7
, P5
0
, P5
1
, P5
4
P5
7
, P6
0
P6
2
"L" total average output current (Note 1)
P3
0
P3
7
, P5
2
, P5
3
"H" peak output current (Note 2)
P0
0
P0
7
, P1
0
P1
7
, P2
0
P2
7
"H" peak output current (Note 2)
P3
0
P3
7
, P4
1
P4
7
, P5
0
P5
7
, P6
0
P6
2
"L" peak output current (Note 2)
P0
0
P0
7
, P1
0
P1
7
, P2
0
P2
7
"L" peak output current (Note 2)
P4
0
P4
7
, P5
0
, P5
1
, P5
4
P5
7
, P6
0
P6
2
"L" peak output current (Note 2)
P3
0
P3
7
, P5
2
, P5
3
"H" average output current (Note 3)
P0
0
P0
7
, P1
0
P1
7
, P2
0
P2
7
"H" average output current (Note 3)
P4
0
P4
7
, P5
0
P5
7
, P6
0
P6
2
"L" average output current (Note 3)
P0
0
P0
7
, P1
0
P1
7
, P2
0
P2
7
"L" average output current (Note 3)
P4
0
P4
7
, P5
0
, P5
1
, P5
4
P5
7
, P6
0
P6
2
"L" average output current (Note 3)
P3
0
P3
7
, P5
2
, P5
3
I
OH(peak)
I
OH(peak)
I
OL(peak)
I
OL(peak)
I
OL(peak)
I
OH(avg)
I
OH(avg)
I
OL(avg)
I
OL(avg)
I
OL(avg)
I
OH(peak)
I
OH(peak)
I
OL(peak)
I
OL(peak)
I
OL(peak)
I
OH(avg)
I
OH(avg)
I
OL(avg)
I
OL(avg)
I
OL(avg)
Limits
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
Parameter
Min.
Typ.
Max.
Symbol
Unit
20
20
20
20
110
10
10
10
10
90
1.0
5.0
10
10
30
0.5
2.5
5.0
5.0
15
Table 13 Recommended operating conditions
(Vcc = 1.8 to 5.5 V, Ta = 20 to 85C, unless otherwise noted)
Notes 1: The total output current is the sum of all the currents flowing through all the applicable ports. The total average current is an average value measured over
100 ms. The total peak current is the peak value of all the currents.
2: The peak output current is the peak current flowing in each port.
3: The average output current is average value measured over 100 ms.
55
38C2 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
PRELIMINAR
Y
Notice: This is not a final specification.
Some parametric limits are subject to change.
Table 14 Recommended operating conditions (Mask ROM version)
(Vcc = 1.8 to 5.5 V, Ta = 20 to 85C, unless otherwise noted)
Timer X and Timer Y
Input frequency (duty cycle 50%)
System clock
frequency
Main clock input oscillation frequency (Note 1)
Sub-clock input oscillation frequency (Notes 1, 2)
f(CNTR
0
)
f(CNTR
1
)
f(
)
f(X
IN
)
f(X
CIN
)
Limits
MHz
MHz
MHz
MHz
MHz
MHz
kHz
Parameter
Min.
Typ.
32.768
Max.
4.0
(15
V
CC
16)/11
8.0
(30
V
CC
32)/11
8.0
20
V
CC
32
50
Symbol
Unit
(4.0 V
V
CC
5.5 V)
(V
CC
4.0 V)
(4.0 V
V
CC
5.5 V)
(V
CC
4.0 V)
(2.0 V
V
CC
5.5 V)
(V
CC
2.0 V)
Notes 1: When the oscillation frequency has a duty cycle of 50%.
2: When using the microcomputer in low-speed mode, set the clock input oscillation frequency on condition that f(X
CIN
) < f(X
IN
)/3.
I
OH
= 1 mA
I
OH
= 0.25 mA
V
CC
= 1.8 V
I
OH
= 5 mA
I
OH
= 1.5 mA
I
OH
= 1.25 mA
V
CC
= 1.8 V
I
OL
= 10 mA
I
OL
= 3 mA
I
OL
= 2.5 mA
V
CC
= 1.8 V
I
OL
= 15 mA
I
OL
= 4 mA
V
CC
= 1.8 V
V
I
= V
CC
V
I
= V
CC
V
I
= V
CC
V
I
= V
SS
Pull-up "OFF"
V
CC
= 5.0 V, V
I
= V
SS
Pull-up "ON"
V
CC
= 1.8 V, V
I
= V
SS
Pull-up "ON"
V
I
= V
SS
V
I
= V
SS
"H" output voltage
P0
0
P0
7
, P1
0
P1
7
, P2
0
P2
7
"H" output voltage
P3
0
P3
7
, P4
0
P4
7
, P5
0
P5
7
, P6
0
P6
2
"L" output voltage
P0
0
P0
7
, P1
0
P1
7
, P2
0
P2
7,
P4
0
P4
7
,
P5
0
, P5
1
, P5
4
P5
7,
P6
0
P6
2
"L" output voltage
P3
0
P3
7
, P5
2
, P5
3
Hysteresis
INT
0
INT
2
, CNTR
0
, CNTR
1
, P0
0
P0
3
, P5
4
P5
7
Hysteresis
S
CLK1
, S
CLK2
, RxD
1
, RxD
2
Hysteresis
RESET
"H" input current
P0
0
P0
7
, P1
0
P1
7
, P2
0
P2
7
, P3
0
P3
7
, P4
0
P4
7
,
P5
0
P5
7
, P6
0
P6
2
"H" input current
RESET
"H" input current
X
IN
"L" input current
P0
0
P0
7
, P1
0
P1
7
, P2
0
P2
7
, P3
0
P3
7
, P4
0
P4
7
,
P5
0
P5
7
, P6
0
P6
2
"L" input current
RESET
"L" input current
X
IN
Limits
V
V
V
V
V
V
V
V
V
V
V
V
V
A
A
A
A
A
A
A
A
Parameter
Min.
V
CC
2.0
V
CC
0.8
V
CC
2.0
V
CC
0.5
V
CC
0.8
60
5.0
Typ.
0.5
0.5
0.5
4.0
120
20
4.0
Max.
2.0
0.5
0.8
2.0
0.8
5.0
5.0
5.0
240
40
5.0
Symbol
Unit
Test conditions
V
OH
V
OH
V
OL
V
OL
V
T+
V
T-
V
T+
V
T-
V
T+
V
T-
I
IH
I
IH
I
IH
I
IL
I
IL
I
IL
Electrical Characteristics
Table 15 Electrical characteristics (Mask ROM version)
(Vcc = 4.0 to 5.5 V, Ta = 20 to 85C, unless otherwise noted)
56
38C2 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
PRELIMINAR
Y
Notice: This is not a final specification.
Some parametric limits are subject to change.
RAM hold voltage
Power source current
Limits
Parameter
Min.
1.8
Typ.
5.1
1.0
14
6
7
3
0.1
Max.
5.5
7.5
2.0
21
10
12
6
1.0
10
Symbol
Unit
When clock is stopped
Through mode, Vcc = 5 V
f(X
IN
) = 8 MHz
f(X
CIN
) = 32.768 kHz
Output transistors "OFF",
A-D converter in operating
Through mode, Vcc = 5 V
f(X
IN
) = 8 MHz (in WIT state)
f(X
CIN
) = 32.768 kHz
Output transistors "OFF",
A-D converter stopped
Low-speed mode, V
CC
= 5 V,
Ta
55 C
f(X
IN
) = stopped
f(X
CIN
) = 32.768 kHz
Output transistors "OFF"
Low-speed mode, V
CC
= 5 V,
Ta = 25 C
f(X
IN
) = stopped
f(X
CIN
) = 32.768 kHz (in WIT state)
Output transistors "OFF"
Low-speed mode, V
CC
= 3 V,
Ta
55 C
f(X
IN
) = stopped
f(X
CIN
) = 32.768 kHz
Output transistors "OFF"
Low-speed mode, V
CC
= 3 V,
Ta = 25 C
f(X
IN
) = stopped
f(X
CIN
) = 32.768 kHz (in WIT state)
Output transistors "OFF"
All oscillation stopped
(in STP state)
Output transistors "OFF"
Test conditions
V
RAM
I
CC
V
mA
mA
A
A
A
A
A
A
Ta = 25 C
Ta = 85 C
Table 16 Electrical characteristics (Mask ROM version)
(Vcc = 1.8 to 5.5 V, Ta = 20 to 85C, unless otherwise noted)
57
38C2 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
PRELIMINAR
Y
Notice: This is not a final specification.
Some parametric limits are subject to change.
A-D Converter Characteristics
Table 17 A-D converter characteristics (Mask ROM version)
(Vcc = 2.2 to 5.5 V, Vss = AV
SS
= 0 V, Ta = 20 to 85C, Port state = stopped, unless otherwise noted)
Resolution
Differencial non-linearity error
Non-linearity error
Off-set error
Full-scale error
Differencial non-linearity error
Non-linearity error
Off-set error
Full-scale error
Conversion time
Ladder resistor
Reference input current
Analog input current
Unit
Bits
LSB
LSB
s
k
A
A
Limits
Parameter
Min.
12
50
Typ.
35
150
Max.
10
1
1
3
5
1
1
2
3
tc(X
IN
)
121
(Note)
100
200
5.0
Symbol
V
CC
= V
REF
= 5 V
V
CC
= V
REF
= 2.2 V, AD clock frequency = 250 kHz
V
CC
= V
REF
= 2.3 V, AD clock frequency = 500 kHz
V
CC
= V
REF
= 2.4 V, AD clock frequency = 1 MHz
V
CC
= V
REF
= 2.5 V, AD clock frequency = 2 MHz
V
CC
= V
REF
= 2.5 V, AD clock frequency = 4 MHz
V
CC
= V
REF
= 2.6 V, AD clock frequency = 8 MHz
AD conversion clock selection bit :Frequency not divided,
10bitAD mode
V
REF
= 5 V
Test conditions
--
--
T
conv
R
LADDER
IV
REF
I
IA
Note: When "Frequency/2, 4 or 8" is selected by the AD conversion clock selection bit, the above conversion time is multiplied by 2, 4 or 8.
LCD Power Supply Characteristics
Table 18 LCD power supply characteristics (when connecting division resistors for LCD power supply)
(Vcc = 1.8 to 5.5 V, Ta = 20 to 85C, unless otherwise noted)
Division resistor
for LCD power supply
(Note)
Unit
k
Limits
Parameter
Min.
Typ.
200
5
120
90
150
120
170
150
190
170
150
120
170
150
190
170
190
190
Max.
Symbol
RSEL = "10"
RSEL = "11"
LCD drive timing A
LCD circuit division ratio = divided by 1 RSEL = "01"
RSEL = "00"
LCD circuit division ratio = divided by 2 RSEL = "01"
RSEL = "00"
LCD circuit division ratio = divided by 4 RSEL = "01"
RSEL = "00"
LCD circuit division ratio = divided by 8 RSEL = "01"
RSEL = "00"
LCD drive timing B LCD circuit division ratio = divided by 1 RSEL = "01"
RSEL = "00"
LCD circuit division ratio = divided by 2 RSEL = "01"
RSEL = "00"
LCD circuit division ratio = divided by 4 RSEL = "01"
RSEL = "00"
LCD circuit division ratio = divided by 8 RSEL = "01"
RSEL = "00"
Test conditions
R
LCD
Note: The value is the average of each one division resistor.
58
38C2 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
PRELIMINAR
Y
Notice: This is not a final specification.
Some parametric limits are subject to change.
t
w
(RESET)
t
c
(X
IN
)
t
wH
(X
IN
)
t
wL
(X
IN
)
t
c
(CNTR)
t
wH
(CNTR)
t
wL
(CNTR)
t
wH
(INT)
t
wL
(INT)
t
c
(S
CLK
)
t
wH
(S
CLK
)
t
wL
(S
CLK
)
t
su
(RxD-S
CLK
)
t
h
(S
CLK
-RxD)
Reset input "L" pulse width
Main clock input cycle time (X
IN
input)
Main clock input "H" pulse width
Main clock input "L" pulse width
CNTR
0
, CNTR
1
input cycle time
CNTR
0
, CNTR
1
input "H" pulse width
CNTR
0
, CNTR
1
input "L" pulse width
INT
0
INT
2
input "H" pulse width
INT
0
INT
2
input "L" pulse width
Serial I/O1, 2 clock input cycle time (Note)
Serial I/O1, 2 clock input "H" pulse width (Note)
Serial I/O1, 2 clock input "L" pulse width (Note)
Serial I/O1, 2 input setup time
Serial I/O1, 2 input hold time
t
w
(RESET)
t
c
(X
IN
)
t
wH
(X
IN
)
t
wL
(X
IN
)
t
c
(CNTR)
t
wH
(CNTR)
t
wL
(CNTR)
t
wH
(INT)
t
wL
(INT)
t
c
(S
CLK
)
t
wH
(S
CLK
)
t
wL
(S
CLK
)
t
su
(RxD-S
CLK
)
t
h
(S
CLK
-RxD)
Limits
s
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Parameter
Min.
2
125
45
40
250
105
105
80
80
800
370
370
220
100
Typ.
Max.
Symbol
Unit
Limits
s
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Parameter
Min.
2
125
45
40
11000/(15
V
CC
16)
tc(CNTR)/220
tc(CNTR)/220
230
230
2000
950
950
400
200
Typ.
Max.
Symbol
Unit
Reset input "L" pulse width
Main clock input cycle time (X
IN
input)
Main clock input "H" pulse width
Main clock input "L" pulse width
CNTR
0
, CNTR
1
input cycle time
CNTR
0
, CNTR
1
input "H" pulse width
CNTR
0
, CNTR
1
input "L" pulse width
INT
0
INT
2
input "H" pulse width
INT
0
INT
2
input "L" pulse width
Serial I/O1, 2 clock input cycle time (Note)
Serial I/O1, 2 clock input "H" pulse width (Note)
Serial I/O1, 2 clock input "L" pulse width (Note)
Serial I/O1, 2 input setup time
Serial I/O1, 2 input hold time
Table 20 Timing requirements 2
(Vcc = 1.8 to 4.0 V, Vss = 0 V, Ta = 20 to 85C, unless otherwise noted)
Timing Requirements And Switching Characteristics
Table 19 Timing requirements 1
(Vcc = 4.0 to 5.5 V, Vss = 0 V, Ta = 20 to 85C, unless otherwise noted)
Note : When bit 6 of address 0FE0
16
or 0FE3
16
is "1" (clock synchronous).
Divide this value by four when bit 6 of address 0FE0
16
or 0FE3
16
is "0" (UART).
Note : When bit 6 of address 0FE0
16
or 0FE3
16
is "1" (clock synchronous).
Divide this value by four when bit 6 of address 0FE0
16
or 0FE3
16
is "0" (UART).
59
38C2 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
PRELIMINAR
Y
Notice: This is not a final specification.
Some parametric limits are subject to change.
t
wH
(S
CLK
)
t
wL
(S
CLK
)
t
d
(S
CLK
-TxD)
t
V
(S
CLK
-TxD)
t
r
(S
CLK
)
t
f
(S
CLK
)
t
r
(CMOS)
t
f
(CMOS)
t
wH
(S
CLK
)
t
wL
(S
CLK
)
t
d
(S
CLK
-TxD)
t
V
(S
CLK
-TxD)
t
r
(S
CLK
)
t
f
(S
CLK
)
t
r
(CMOS)
t
f
(CMOS)
Limits
Parameter
Min.
t
c
(S
CLK
)/230
t
c
(S
CLK
)/230
30
Typ.
10
10
Max.
140
30
30
30
30
Symbol
Unit
ns
ns
ns
ns
ns
ns
ns
ns
Notes 1: When the P-channel output disable bit (bit 4 of address 0FE1
16
or 0FE4
16
) is "0."
2: The X
OUT
, X
COUT
pins are excluded.
Serial I/O1, 2 clock output "H" pulse width
Serial I/O1, 2 clock output "L" pulse width
Serial I/O1, 2 output delay time
(Note 1)
Serial I/O1, 2 output valid time
(Note 1)
Serial I/O1, 2 clock output rising time
Serial I/O1, 2 clock output falling time
CMOS output rising time
(Note 2)
CMOS output falling time
(Note 2)
Table 21 Switching characteristics 1
(Vcc = 4.0 to 5.5 V, Vss = 0 V, Ta = 20 to 85C, unless otherwise noted)
Limits
ns
ns
ns
ns
ns
ns
ns
ns
Parameter
Min.
t
C
(S
CLK
)/250
t
C
(S
CLK
)/250
30
Typ.
20
20
Max.
350
50
50
50
50
Symbol
Unit
Serial I/O1, 2 clock output "H" pulse width
Serial I/O1, 2 clock output "L" pulse width
Serial I/O1, 2 output delay time
(Note 1)
Serial I/O1, 2 output valid time
(Note 1)
Serial I/O1, 2 clock output rising time
Serial I/O1, 2 clock output falling time
CMOS output rising time
(Note 2)
CMOS output falling time
(Note 2)
Table 22 Switching characteristics 2
(Vcc = 1.8 to 4.0 V, Vss = 0 V, Ta = 20 to 85C, unless otherwise noted)
Notes 1: When the P-channel output disable bit (bit 4 of address 0FE1
16
or 0FE4
16
) is "0."
2: The X
OUT
, X
COUT
pins are excluded.
Fig. 56 Circuit for measuring output switching characteristics
Measurement output pin
100pF
C
M
O
S
o
u
t
p
u
t
Measurement output pin
100pF
N-channel open-drain output (Note)
1
k
Note: When bit 4 of the UART control register
(address 0EF1
16
or 0FE4
16
) is " 1."
(N-channel open-drain output mode)
60
38C2 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
PRELIMINAR
Y
Notice: This is not a final specification.
Some parametric limits are subject to change.
Fig. 57 Timing chart
CNTR
0
,CNTR
1
I
N
T
0
t
o
I
N
T
2
0.2V
CC
t
d
(
S
C
L
K
-
T
X
D
)
t
f
0.2V
CC
0
.
8
V
C
C
0
.
8
V
C
C
t
r
t
s
u
(
R
X
D
-
S
C
L
K
)
t
h
(
S
C
L
K
-
R
X
D
)
t
v
(S
CLK
-T
X
D)
t
C
(S
CLK
)
t
W
L
(
S
C
L
K
)
t
W
H
(
S
C
L
K
)
T
X
D
1
T
X
D
2
R
X
D
1
R
X
D
2
S
CLK1
S
CLK2
0
.
2
V
C
C
t
WL
(X
IN
)
0.8V
CC
t
WH
(X
IN
)
t
C
(
X
I
N
)
X
IN
0.2V
CC
0
.
8
V
C
C
t
W
(
R
E
S
E
T
)
R
E
S
E
T
0
.
2
V
C
C
t
WL
(CNTR)
0.8V
CC
t
WH
(CNTR)
t
C
(
C
N
T
R
)
0
.
2
V
C
C
t
WL
(INT)
0.8V
CC
t
WH
(INT)
61
38C2 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
PRELIMINAR
Y
Notice: This is not a final specification.
Some parametric limits are subject to change.
PACKAGE OUTLINE
QFP64-P-1414-0.80
1.11
Weight(g)
JEDEC Code
EIAJ Package Code
Lead Material
Alloy 42
64P6N-A
Plastic 64pin 14
14mm body QFP
Symbol
Min
Nom
Max
A
A
2
b
c
D
E
H
E
L
L
1
y
b
2
Dimension in Millimeters
H
D
A
1
0.2
0.1
0.5
I
2
1.3
M
D
14.6
M
E
14.6
10
0
0.1
1.4
0.8
0.6
0.4
17.1
16.8
16.5
17.1
16.8
16.5
0.8
14.2
14.0
13.8
14.2
14.0
13.8
0.2
0.15
0.13
0.45
0.35
0.3
2.8
0
3.05
e
e
e
E
c
H
E
1
64
49
32
48
33
17
16
H
D
D
M
D
M
E
A
F
A
1
A
2
L
1
L
y
b
2
I
2
Recommended Mount Pad
Detail F
x
0.2
b
x
M
LQFP64-P-1010-0.50
Weight(g)
JEDEC Code
EIAJ Package Code
Lead Material
Cu Alloy
64P6Q-A
Plastic 64pin 10
10mm body LQFP
0.1
0.2
Symbol
Min
Nom
Max
A
A
2
b
c
D
E
H
E
L
L
1
y
b
2
Dimension in Millimeters
H
D
A
1
0.225
I
2
1.0
M
D
10.4
M
E
10.4
10
0
0.1
1.0
0.7
0.5
0.3
12.2
12.0
11.8
12.2
12.0
11.8
0.5
10.1
10.0
9.9
10.1
10.0
9.9
0.175
0.125
0.105
0.28
0.18
0.13
1.4
0
1.7
e
e
E
H
E
1
64
49
48
33
32
17
16
H
D
D
M
D
M
E
A
F
y
b
2
I
2
Recommended Mount Pad
Lp
0.45
0.6
0.25
0.75
0.08
x
A3
b
x
M
A
1
A
2
L
1
L
Detail F
Lp
A3
c
e
2000 MITSUBISHI ELECTRIC CORP.
0008 Printed in Japan (ROD)
II
New publication, effective Aug. 2000.
Specifications subject to change without notice.
Notes regarding these materials
These materials are intended as a reference to assist our customers in the selection of the Mitsubishi semiconductor product best suited to the customer's application; they do not convey any license under any intellectual property
rights, or any other rights, belonging to Mitsubishi Electric Corporation or a third party.
Mitsubishi Electric Corporation assumes no responsibility for any damage, or infringement of any third-party's rights, originating in the use of any product data, diagrams, charts, programs, algorithms, or circuit application examples
contained in these materials.
All information contained in these materials, including product data, diagrams, charts, programs and algorithms represents information on products at the time of publication of these materials, and are subject to change by
Mitsubishi Electric Corporation without notice due to product improvements or other reasons. It is therefore recommended that customers contact Mitsubishi Electric Corporation or an authorized Mitsubishi Semiconductor product
distributor for the latest product information before purchasing a product listed herein.
The information described here may contain technical inaccuracies or typographical errors. Mitsubishi Electric Corporation assumes no responsibility for any damage, liability, or other loss rising from these inaccuracies or errors.
Please also pay attention to information published by Mitsubishi Electric Corporation by various means, including the Mitsubishi Semiconductor home page (http://www.mitsubishichips.com).
When using any or all of the information contained in these materials, including product data, diagrams, charts, programs, and algorithms, please be sure to evaluate all information as a total system before making a final decision
on the applicability of the information and products. Mitsubishi Electric Corporation assumes no responsibility for any damage, liability or other loss resulting from the information contained herein.
Mitsubishi Electric Corporation semiconductors are not designed or manufactured for use in a device or system that is used under circumstances in which human life is potentially at stake. Please contact Mitsubishi Electric
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The prior written approval of Mitsubishi Electric Corporation is necessary to reprint or reproduce in whole or in part these materials.
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Any diversion or reexport contrary to the export control laws and regulations of Japan and/or the country of destination is prohibited.
Please contact Mitsubishi Electric Corporation or an authorized Mitsubishi Semiconductor product distributor for further details on these materials or the products contained therein.
Keep safety first in your circuit designs!
Mitsubishi Electric Corporation puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. Trouble with semiconductors may lead to
personal injury, fire or property damage. Remember to give due consideration to safety when making your circuit designs, with appropriate measures such as (i) placement of substitutive, auxiliary circuits, (ii) use of non-flammable
material or (iii) prevention against any malfunction or mishap.
HEAD OFFICE: 2-2-3, MARUNOUCHI, CHIYODA-KU, TOKYO 100-8310, JAPAN
38C2 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
PRELIMINAR
Y
Notice: This is not a final specification.
Some parametric limits are subject to change.
Rev.
Rev.
No.
date
1.0
First Edition
000830
1.1
P53 Table 12 Recommended operating condition
000901
Parameter of V
IH
, V
IL
: "X
IN
" (wrong)
"X
IN
, X
CIN
" (correct)
REVISION DESCRIPTION LIST
38C2 GROUP DATA SHEET
(1/1)
Revision Description
PDF 
ZIP