Mitsubishi microcomputers

M16C / 62A Group

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

Description

------Table of Contents------

Description

The M16C/62A group of single-chip microcomputers are built using the high-performance silicon gate

CMOS process using a M16C/60 Series CPU core and are packaged in a 100-pin plastic molded QFP.

These single-chip microcomputers operate using sophisticated instructions featuring a high level of instruc-

tion efficiency. With 1M bytes of address space, they are capable of executing instructions at high speed.

They also feature a built-in multiplier and DMAC, making them ideal for controlling office, communications,

industrial equipment, and other high-speed processing applications.

The M16C/62A group includes a wide range of products with different internal memory types and sizes and

various package types.

Features

· Memory capacity .................................. ROM (See Figure 1.1.4. ROM Expansion)

RAM 3K to 20K bytes

· Shortest instruction execution time ...... 62.5ns (f(X

)=16MH

, V

=5V)

100ns (f(X

)=10MH

, V

=3V, with software one-wait) : Mask ROM, flash memory 5V version

· Supply voltage ..................................... 4.2V to 5.5V (f(X

)=16MH

, without software wait) : Mask ROM, flash memory 5V version

2.7V to 5.5V (f(X

)=10MH

with software one-wait) : Mask ROM, flash memory 5V version

· Low power consumption ...................... 25.5mW ( f(X

)=10MH

, with software one-wait, V

= 3V)

· Interrupts .............................................. 25 internal and 8 external interrupt sources, 4 software

interrupt sources; 7 levels (including key input interrupt)

· Multifunction 16-bit timer ...................... 5 output timers + 6 input timers

· Serial I/O .............................................. 5 channels (3 for UART or clock synchronous, 2 for clock synchro-

nous)

· DMAC .................................................. 2 channels (trigger: 24 sources)

· A-D converter ....................................... 10 bits X 8 channels (Expandable up to 10 channels)

· D-A converter ....................................... 8 bits X 2 channels

· CRC calculation circuit ......................... 1 circuit

· Watchdog timer .................................... 1 line

· Programmable I/O ............................... 87 lines

· Input port ..............................................

_______

1 line (P8

shared with NMI pin)

· Memory expansion .............................. Available (to a maximum of 1M bytes)

· Chip select output ................................ 4 lines

· Clock generating circuit ....................... 2 built-in clock generation circuits

(built-in feedback resistor, and external ceramic or quartz oscillator)

Applications

Audio, cameras, office equipment, communications equipment, portable equipment

Timer ............................................................. 77

Serial I/O ..................................................... 107

A-D Converter ............................................. 148

D-A Converter ............................................. 158

CRC Calculation Circuit .............................. 160

Programmable I/O Ports ............................. 162

Electrical characteristic ............................... 173

Flash memory version ................................. 216

Central Processing Unit (CPU) ..................... 11

Reset ............................................................. 14

Processor Mode ............................................ 21

Clock Generating Circuit ............................... 35

Protection ...................................................... 44

Interrupts ....................................................... 45

Watchdog Timer ............................................ 65

DMAC ........................................................... 67

Mitsubishi microcomputers

M16C / 62A Group

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

Description

9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30

100

REF

OUT

RESET

CNVss

CIN

COUT

BYTE

(/D

/-)

(/D

)

(/D

)

(/D

)

(/D

)

(/D

)

(/D

)

(/D

)

(/-/D

)

/TA2

OUT

/TA3

OUT

/ALE

/TA3

/HOLD

/HLDA

/BCLK

/RD

Vcc

Vss

/RDY/CLK

OUT

/CS1

/CS2

/CS3

AVcc

/CLK

/RxD

/CLK

/RxD

P10

/AN

P10

/AN

P10

/AN

P10

/AN

/DA

/TB3

/DA

/TB4

/ANEX0/CLK4

/ANEX1/S

OUT

/TB1

/TB2

OUT

/TA4

OUT

/CTS

/RTS

/CTS

/RTS

/CLKS

/CLK

/TA1

OUT

/INT

/RxD

/SCL/TA0

/TB5

(Note)

/INT

/NMI

/AD

TRG

/CS0

/WRL/WR

/WRH/BHE

/TB0

/CLK3

/SDA/TA0

OUT

(Note)

/INT

/TA4

/TA2

/INT3

/INT4

/INT5

P10

/AN

/KI

P10

/AN

/KI

P10

/AN

/KI

P10

/AN

/CTS

/RTS

/TA1

Note: P7

and P7

are N channel open-drain output pin.

Pin Configuration

Figures 1.1.1 and 1.1.2 show the pin configurations (top view).

PIN CONFIGURATION (top view)

Package: 100P6S-A

Figure 1.1.1. Pin configuration (top view)

M16C/62A Group

Mitsubishi microcomputers

M16C / 62A Group

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

Description

1 2

8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25

100

REF

OUT

RESET

CNVss

CIN

COUT

BYTE

(/D

/-)

(/D

)

(/D

)

(/D

)

(/D

)

(/D

)

(/D

)

(/D

)

(/-/D

)

/TA2

OUT

/TA3

OUT

/ALE

/TA3

/HOLD

/HLDA

/BCLK

/RD

Vcc

Vss

/RDY/CLK

OUT

/CS1

/CS2

/CS3

AVcc

/CLK

/RxD

/CLK

/RxD

P10

/AN

P10

/AN

P10

/AN

P10

/AN

/DA

/TB3

/DA

/TB4

/ANEX0/CLK4

/ANEX1/S

OUT

/TB1

/TB2

OUT

/TA4

OUT

/CTS

/RTS

/CTS

/RTS

/CLKS

/INT

/NMI

/AD

TRG

/CS0

/WRL/WR

/WRH/BHE

/TB0

/CLK3

/INT

/CLK

/TA1

OUT

/RxD

/SCL/TA0

/TB5

(Note)

/SDA/TA0

OUT

(Note)

/TA2

/CTS

/RTS

/TA1

/INT

P10

/AN

/KI

P10

/AN

/KI

P10

/AN

/KI

P10

/AN

Note: P7

and P7

are N channel open-drain output pin.

Figure 1.1.2. Pin configuration (top view)

Package: 100P6Q-A

PIN CONFIGURATION (top view)

M16C/62A Group

Mitsubishi microcomputers

M16C / 62A Group

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

Description

Block Diagram

Figure 1.1.3 is a block diagram of the M16C/62A group.

Timer

Timer TA0 (16 bits)
Timer TA1 (16 bits)
Timer TA2 (16 bits)
Timer TA3 (16 bits)
Timer TA4 (16 bits)
Timer TB0 (16 bits)
Timer TB1 (16 bits)
Timer TB2 (16 bits)
Timer TB3 (16 bits)
Timer TB4 (16 bits)
Timer TB5 (16 bits)

Internal peripheral functions

Watchdog timer

(15 bits)

DMAC

(2 channels)

D-A converter

(8 bits X 2 channels)

A-D converter

(10 bits

8 channels

Expandable up to 10 channels)

UART/clock synchronous SI/O

(8 bits

3 channels)

System clock generator

-X

OUT

CIN

-X

COUT

M16C/60 series16-bit CPU core

I/O ports

Port P0

Port P1

Port P2

Port P3

Port P4

Port P5

Port P6

R0L

R0H
R1H

R1L

R2
R3
A0
A1
FB

R0L

R0H

R1H

R1L

R2
R3

A0
A1

Registers

ISP

USP

Stack pointer

CRC arithmetic circuit (CCITT )

(Polynomial : X

+1)

Multiplier

Port P10

Port P9

Port P8

Port P7

Memory

Port P8

ROM

(Note 1)

RAM

(Note 2)

Note 1: ROM size depends on MCU type.
Note 2: RAM size depends on MCU type.

FLG

Program counter

Clock synchronous SI/O

(8 bits

2 channels)

Vector table

INTB

Flag register

Figure 1.1.3. Block diagram of M16C/62A group

Mitsubishi microcomputers

M16C / 62A Group

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

Description

Item

Performance

Number of basic instructions

91 instructions

Shortest instruction execution time

62.5ns(f(X

)=16MH

, V

=5V)

100ns (f(X

)=10MH

, V

=3V, with software one-wait)

: Mask ROM, flash memory 5V version

Memory

ROM

(See the figure 1.1.4. ROM Expansion)

capacity

RAM

3K to 20K bytes

I/O port

P0 to P10 (except P8

)

8 bits x 10, 7 bits x 1

Input port

1 bit x 1

Multifunction TA0, TA1, TA2, TA3, TA4

16 bits x 5

timer

TB0, TB1, TB2, TB3, TB4, TB5

16 bits x 6

Serial I/O

UART0, UART1, UART2

(UART or clock synchronous) x 3

SI/O3, SI/O4

(Clock synchronous) x 2

A-D converter

10 bits x (8 + 2) channels

D-A converter

8 bits x 2

DMAC

2 channels (trigger: 24 sources)

CRC calculation circuit

CRC-CCITT

Watchdog timer

15 bits x 1 (with prescaler)

Interrupt

25 internal and 8 external sources, 4 software sources, 7 levels

Clock generating circuit

2 built-in clock generation circuits

(built-in feedback resistor, and external ceramic or quartz oscillator)

Supply voltage

4.2V to 5.5V (f(X

)=16MH

, without software wait)

: Mask ROM, flash memory 5V version

2.7V to 5.5V (f(X

)=10MH

with software one-wait)

: Mask ROM, flash memory 5V version

Power consumption

25.5mW (f(X

) = 10MH

, V

=3V with software one-wait)

I/O

I/O withstand voltage

characteristics Output current

5mA

Memory expansion

Available (to a maximum of 1M bytes)

Device configuration

CMOS high performance silicon gate

Package

100-pin plastic mold QFP

Table 1.1.1. Performance outline of M16C/62A group

Performance Outline

Table 1.1.1 is a performance outline of M16C/62A group.

Mitsubishi microcomputers

M16C / 62A Group

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

Description

Mitsubishi plans to release the following products in the M16C/62A group:

(1) Support for mask ROM version, external ROM version, and flash memory version

(2) ROM capacity

(3) Package

100P6S-A

: Plastic molded QFP (mask ROM, and flash memory versions)

100P6Q-A

: Plastic molded QFP(mask ROM, and flash memory versions)

The M16C/62A group products currently supported are listed in Table 1.1.2.

Table 1.1.2. M16C/62A group

ROM Size

(Byte)

External

ROM

128K

96K

64K

32K

M30620M8A-XXXFP/GP
M30622M8A-XXXFP/GP

M30620MAA-XXXFP/GP
M30622MAA-XXXFP/GP

M30620MCA-XXXFP/GP
M30622MCA-XXXFP/GP

Mask ROM version

Flash memory version

M30624FGAFP/GP

256K

M30624MGA-XXXFP/GP

M30622M4A-XXXFP/GP

External ROM version

M30620SAFP/GP
M30622SAFP/GP

M30620FCAFP/GP

RAM capacity

ROM capacity

Package type

Remarks

Type No.

March. 2001

M30622M4A-XXXFP

3K byte

100P6S-A

M30622M4A-XXXGP

100P6Q-A

M30620M8A-XXXFP

64K byte

10K byte

100P6S-A

Mask ROM version

M30620M8A-XXXGP

100P6Q-A

M30622M8A-XXXFP

4K byte

100P6S-A

M30622M8A-XXXGP

100P6Q-A

M30620MAA-XXXFP

10K byte

100P6S-A

3K byte

M30622SAFP

External ROM
version

M30622SAGP

100P6Q-A

100P6S-A

10K byte

M30620MCA-XXXGP

M30620MCA-XXXFP

M30622MCA-XXXFP

M30622MCA-XXXGP

5K byte

128K byte

100P6S-A

100P6Q-A

100P6S-A

100P6Q-A

100P6S-A

M30620SAFP

10K byte

100P6Q-A

M30620SAGP

M30620MAA-XXXGP

96K byte

100P6Q-A

M30622MAA-XXXFP

5K byte

100P6S-A

M30622MAA-XXXGP

100P6Q-A

M30624MGA-XXXFP

20K byte

100P6S-A

M30624MGA-XXXGP

100P6Q-A

256K byte

M30624FGAFP

M30624FGAGP

20K byte

256K byte

Flash memory
5V version

100P6S-A

100P6Q-A

32K byte

: Under development

M30620FCAFP

M30620FCAGP

10K byte

128K byte

100P6S-A

100P6Q-A

Figure 1.1.4. ROM expansion

Mitsubishi microcomputers

M16C / 62A Group

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

Pin Description

, V

CNV

OUT

BYTE

REF

to P0

to D

to P1

to D

to P2

to A

to P3

to A

to P4

Signal name

Power supply
input

CNV

Reset input

Clock input

Clock output

External data
bus width
select input

Analog power
supply input

Reference
voltage input

I/O port P0

I/O port P1

I/O port P2

I/O port P3

I/O port P4

Supply 2.7V to 5.5 V to the V

pin. Supply 0 V to the V

pin.

Function

This pin switches between processor modes. Connect this pin to the
V

pin when after a reset you want to start operation in single-chip

mode (memory expansion mode) or the V

pin when starting

operation in microprocessor mode.

A "L" on this input resets the microcomputer.

These pins are provided for the main clock generating circuit.Connect
a ceramic resonator or crystal between the X

and the X

OUT

pins. To

use an externally derived clock, input it to the X

pin and leave the

OUT

pin open.

This pin selects the width of an external data bus. A 16-bit width is
selected when this input is "L"; an 8-bit width is selected when this
input is "H". This input must be fixed to either "H" or "L". Connect this
pin to the V

pin when not using external data bus.

This pin is a power supply input for the A-D converter. Connect this
pin to V

This pin is a reference voltage input for the A-D converter.

This is an 8-bit CMOS I/O port. It has an input/output port direction
register that allows the user to set each pin for input or output
individually. When used for input in single-chip mode, the port can be
set to have or not have a pull-up resistor in units of four bits by
software. In memory expansion and microprocessor modes, selection
of the internal pull-resistor is not available.

When set as a separate bus, these pins input and output data (D

This is an 8-bit I/O port equivalent to P0. P1

to P1

also function as

external interrupt pins as selected by software.

When set as a separate bus, these pins input and output data

This is an 8-bit I/O port equivalent to P0.

These pins output 8 low-order address bits (A

If the external bus is set as an 8-bit wide multiplexed bus, these pins
input and output data (D

) and output 8 low-order address bits

) separated in time by multiplexing.

If the external bus is set as a 16-bit wide multiplexed bus, these pins
input and output data (D

) and output address (A

) separated

in time by multiplexing. They also output address (A

This is an 8-bit I/O port equivalent to P0.

These pins output 8 middle-order address bits (A

If the external bus is set as a 16-bit wide multiplexed bus, these pins
input and output data (D

) and output address (A

) separated in time

by multiplexing. They also output address (A

This is an 8-bit I/O port equivalent to P0.

Pin name

Input

Output

Input

Input/output

I/O type

Analog power
supply input

Input/output

Output

Input/output

Output

Input/output

Output

Input/output

Output

Input/output

Output
Output

to A

to CS

These pins output A

and CS

signals. A

are 4 high-

order address bits. CS

are chip select signals used to specify an

access space.

RESET

Pin Description

Pin Description

Mitsubishi microcomputers

M16C / 62A Group

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

Pin Description

Signal name

Function

Pin name

I/O type

I/O port P5

Input/output

Input/output
Input/output

Input/output

Input

Input/output

I/O port P6

I/O port P7

I/O port P8

I/O port P9

I/O port P10

to P5

to P6

to P7

to P8

to P9

P10

to P10

This is an 8-bit I/O port equivalent to P0. In single-chip mode, P5

this port outputs a divide-by-8 or divide-by-32 clock of X

or a clock of

the same frequency as X

CIN

as selected by software.

Output
Output
Output
Output
Output
Input

Output
Input

This is an 8-bit I/O port equivalent to P0. When used for input in single-
chip, memory expansion, and microprocessor modes, the port can be
set to have or not have a pull-up resistor in units of four bits by
software. Pins in this port also function as UART0 and UART1 I/O pins
as selected by software.

This is an 8-bit I/O port equivalent to P6 (P7

and P7

are N channel

open-drain output). Pins in this port also function as timer A

timer B5 or UART2 I/O pins as selected by software.

This is an 8-bit I/O port equivalent to P6. Pins in this port also function
as SI/O3, 4 I/O pins, Timer B0B4 input pins, D-A converter output pins,
A-D converter extended input pins, or A-D trigger input pins as selected
by software.

This is an 8-bit I/O port equivalent to P6. Pins in this port also function
as A-D converter input pins as selected by software. Furthermore, P10

P10

also function as input pins for the key input interrupt function.

WRL / WR,
WRH / BHE,
RD,
BCLK,
HLDA,
HOLD,

ALE,
RDY

Output WRL, WRH (WR and BHE), RD, BCLK, HLDA, and ALE
signals. WRL and WRH, and BHE and WR can be switched using
software control.
WRL, WRH, and RD selected
With a 16-bit external data bus, data is written to even addresses
when the WRL signal is "L" and to the odd addresses when the WRH
signal is "L". Data is read when RD is "L".
WR, BHE, and RD selected
Data is written when WR is "L". Data is read when RD is "L". Odd
addresses are accessed when BHE is "L". Use this mode when using
an 8-bit external data bus.
While the input level at the HOLD pin is "L", the microcomputer is
placed in the hold state. While in the hold state, HLDA outputs a "L"
level. ALE is used to latch the address. While the input level of the
RDY pin is "L", the microcomputer is in the ready state.

to P8

, P8

, and P8

are I/O ports with the same functions as P6.

Using software, they can be made to function as the I/O pins for timer
A4 and the input pins for external interrupts. P8

and P8

can be set

using software to function as the I/O pins for a sub clock generation
circuit. In this case, connect a quartz oscillator between P8

COUT

pin) and P8

CIN

pin). P8

is an input-only port that also functions

for NMI. The NMI interrupt is generated when the input at this pin
changes from "H" to "L". The NMI function cannot be cancelled using
software. The pull-up cannot be set for this pin.

Mitsubishi microcomputers

M16C / 62A Group

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

Memory

Operation of Functional Blocks

The M16C/62A group accommodates certain units in a single chip. These units include ROM and RAM to

store instructions and data and the central processing unit (CPU) to execute arithmetic/logic operations.

Also included are peripheral units such as timers, serial I/O, D-A converter, DMAC, CRC calculation circuit,

A-D converter, and I/O ports.

The following explains each unit.

Memory

Figure 1.3.1 is a memory map of the M16C/62A group. The address space extends the 1M bytes from

address 00000

to FFFFF

. From FFFFF

down is ROM. For example, in the M30622MCA-XXXFP,

there is 128K bytes of internal ROM from E0000

to FFFFF

. The vector table for fixed interrupts such as

_______

the reset and NMI are mapped to FFFDC

to FFFFF

. The starting address of the interrupt routine is

stored here. The address of the vector table for timer interrupts, etc., can be set as desired using the

internal register (INTB). See the section on interrupts for details.

From 00400

up is RAM. For example, in the M30622MCA-XXXFP, 5K bytes of internal RAM is mapped

to the space from 00400

to 017FF

. In addition to storing data, the RAM also stores the stack used when

calling subroutines and when interrupts are generated.

The SFR area is mapped to 00000

to 003FF

. This area accommodates the control registers for periph-

eral devices such as I/O ports, A-D converter, serial I/O, and timers, etc. Figures 1.6.1 to 1.6.3 are location

of peripheral unit control registers. Any part of the SFR area that is not occupied is reserved and cannot be

used for other purposes.

The special page vector table is mapped to FFE00

to FFFDB

. If the starting addresses of subroutines

or the destination addresses of jumps are stored here, subroutine call instructions and jump instructions

can be used as 2-byte instructions, reducing the number of program steps.

In memory expansion mode and microprocessor mode, a part of the spaces are reserved and cannot be

used. For example, in the M30622MCA-XXXFP, the following spaces cannot be used.

· The space between 01800

and 03FFF

(Memory expansion and microprocessor modes)

· The space between D0000

and DFFFF

(Memory expansion mode)

Figure 1.3.1. Memory map

00000

YYYYY

FFFFF

00400

04000

XXXXX

D0000

External area

Internal ROM area

SFR area

For details, see Figures

1.6.1 to 1.6.3

Internal RAM area

Internal reserved

area (Note 1)

Internal reserved

area (Note 2)

FFE00

FFFDC

FFFFF

Note 1: During memory expansion and microprocessor modes, can not be used.
Note 2: In memory expansion mode, can not be used.
Note 3: These memory maps show an instance in which PM13 is set to 0; but in the

case of products in which the internal RAM and the internal ROM are expanded
to over 15 Kbytes and 192 Kbytes, respectively, they show an instance in which
PM13 is set to 1.

Undefined instruction

Overflow

BRK instruction

Address match

Single step

Watchdog timer

Reset

Special page

vector table

DBC
NMI

Address YYYYY

3K bytes

00FFF

053FF

017FF

013FF

Address XXXXX

ROM size

02BFF

5K bytes

4K bytes

10K bytes

20K bytes

RAM size

32K bytes

C0000

E8000

F0000

E0000

96K bytes

64K bytes

128K bytes

256K bytes

F8000

Mitsubishi microcomputers

M16C / 62A Group

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

CPU

Central Processing Unit (CPU)

The CPU has a total of 13 registers shown in Figure 1.4.1. Seven of these registers (R0, R1, R2, R3, A0,

A1, and FB) come in two sets; therefore, these have two register banks.

(1) Data registers (R0, R0H, R0L, R1, R1H, R1L, R2, and R3)

Data registers (R0, R1, R2, and R3) are configured with 16 bits, and are used primarily for transfer and

arithmetic/logic operations.

Registers R0 and R1 each can be used as separate 8-bit data registers, high-order bits as (R0H/R1H),

and low-order bits as (R0L/R1L). In some instructions, registers R2 and R0, as well as R3 and R1 can

use as 32-bit data registers (R2R0/R3R1).

(2) Address registers (A0 and A1)

Address registers (A0 and A1) are configured with 16 bits, and have functions equivalent to those of data

registers. These registers can also be used for address register indirect addressing and address register

relative addressing.

In some instructions, registers A1 and A0 can be combined for use as a 32-bit address register (A1A0).

b15

(Note)

b15

(Note)

b15

(Note)

b15

(Note)

b15

(Note)

b15

(Note)

b15

Data
registers

Address
registers

Frame base
registers

b15

b19

Program counter

Interrupt table
register

User stack pointer

Interrupt stack
pointer

Static base
register

Flag register

INTB

USP

ISP

FLG

Note: These registers consist of two register banks.

IPL

Figure 1.4.1. Central processing unit register

Mitsubishi microcomputers

M16C / 62A Group

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

CPU

(3) Frame base register (FB)

Frame base register (FB) is configured with 16 bits, and is used for FB relative addressing.

(4) Program counter (PC)

Program counter (PC) is configured with 20 bits, indicating the address of an instruction to be executed.

(5) Interrupt table register (INTB)

Interrupt table register (INTB) is configured with 20 bits, indicating the start address of an interrupt vector

table.

(6) Stack pointer (USP/ISP)

Stack pointer comes in two types: user stack pointer (USP) and interrupt stack pointer (ISP), each config-

ured with 16 bits.

Your desired type of stack pointer (USP or ISP) can be selected by a stack pointer select flag (U flag).

This flag is located at the position of bit 7 in the flag register (FLG).

(7) Static base register (SB)

Static base register (SB) is configured with 16 bits, and is used for SB relative addressing.

(8) Flag register (FLG)

Flag register (FLG) is configured with 11 bits, each bit is used as a flag. Figure 1.4.2 shows the flag

· Bit 0: Carry flag (C flag)

This flag retains a carry, borrow, or shift-out bit that has occurred in the arithmetic/logic unit.

· Bit 1: Debug flag (D flag)

This flag enables a single-step interrupt.

When this flag is "1", a single-step interrupt is generated after instruction execution. This flag is

cleared to "0" when the interrupt is acknowledged.

· Bit 2: Zero flag (Z flag)

This flag is set to "1" when an arithmetic operation resulted in 0; otherwise, cleared to "0".

· Bit 3: Sign flag (S flag)

This flag is set to "1" when an arithmetic operation resulted in a negative value; otherwise, cleared to "0".

· Bit 4: Register bank select flag (B flag)

This flag chooses a register bank. Register bank 0 is selected when this flag is "0" ; register bank 1 is

selected when this flag is "1".

· Bit 5: Overflow flag (O flag)

This flag is set to "1" when an arithmetic operation resulted in overflow; otherwise, cleared to "0".

· Bit 6: Interrupt enable flag (I flag)

This flag enables a maskable interrupt.

An interrupt is disabled when this flag is "0", and is enabled when this flag is "1". This flag is cleared to

"0" when the interrupt is acknowledged.

Mitsubishi microcomputers

M16C / 62A Group

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

CPU

· Bit 7: Stack pointer select flag (U flag)

Interrupt stack pointer (ISP) is selected when this flag is "0" ; user stack pointer (USP) is selected

when this flag is "1".

This flag is cleared to "0" when a hardware interrupt is acknowledged or an INT instruction of software

interrupt Nos. 0 to 31 is executed.

· Bits 8 to 11: Reserved area

· Bits 12 to 14: Processor interrupt priority level (IPL)

Processor interrupt priority level (IPL) is configured with three bits, for specification of up to eight

processor interrupt priority levels from level 0 to level 7.

If a requested interrupt has priority greater than the processor interrupt priority level (IPL), the interrupt

is enabled.

· Bit 15: Reserved area

The C, Z, S, and O flags are changed when instructions are executed. See the software manual for

details.

Figure 1.4.2. Flag register (FLG)

Carry flag

Debug flag

Zero flag

Sign flag

Overflow flag

Interrupt enable flag

Stack pointer select flag

Reserved area

Processor interrupt priority level

Reserved area

Flag register (FLG)

IPL

b15

Mitsubishi microcomputers

M16C / 62A Group

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

Reset

Figure 1.5.2. Reset sequence

Reset

There are two kinds of resets; hardware and software. In both cases, operation is the same after the reset.

(See "Software Reset" for details of software resets.) This section explains on hardware resets.

When the supply voltage is in the range where operation is guaranteed, a reset is effected by holding the

reset pin level "L" (0.2V

max.) for at least 20 cycles. When the reset pin level is then returned to the "H"

level while main clock is stable, the reset status is cancelled and program execution resumes from the

address in the reset vector table.

Figure 1.5.1 shows the example reset circuit. Figure 1.5.2 shows the reset sequence.

Figure 1.5.1. Example reset circuit

BCLK

Address

Microprocessor

mode BYTE = "H"

Microprocessor

mode BYTE = "L"

Content of reset vector

Single chip

mode

BCLK 24cycles

FFFFC

FFFFD

FFFFE

Content of reset vector

FFFFC

FFFFE

Content of reset vector

FFFFE

RESET

CS0

FFFFC

More than 20 cycles are needed

RESET

0.8V

RESET

4.0V

Example when V

= 5V

Mitsubishi microcomputers

M16C / 62A Group

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

Reset

____________

Table 1.5.1 shows the statuses of the other pins while the RESET pin level is "L". Figures 1.5.3 and 1.5.4

show the internal status of the microcomputer immediately after the reset is cancelled.

____________

Table 1.5.1. Pin status when RESET pin level is "L"

Status

CNV

= V

CNV

= V

BYTE = V

Pin name

P2, P3, P4

to P4

P6, P7, P8

to P8

, P8

, P9, P10

Input port (floating)

Data input (floating)

Address output (undefined)

BCLK output

ALE output ("L" level is output)

CS0 output ("H" level is output)

WR output ("H" level is output)

RD output ("H" level is output)

RDY input (floating)

Input port (floating)

BCLK output

BHE output (undefined)

HLDA output (The output value
depends on the input to the
HOLD pin)

HOLD input (floating)

Data input (floating)

Address output (undefined)

CS0 output ("H" level is output)

Input port (floating)
(pull-up resistor is on)

Input port (floating)

RDY input (floating)

ALE output ("L" level is output)

HOLD input (floating)

HLDA output (The output value
depends on the input to the
HOLD pin)

RD output ("H" level is output)

BHE output (undefined)

WR output ("H" level is output)

Input port (floating)
(pull-up resistor is on)

Mitsubishi microcomputers

M16C / 62A Group

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

Reset

Figure 1.5.3. Device's internal status after a reset is cleared

x : Nothing is mapped to this bit
? : Undefined

The content of other registers and RAM is undefined when the microcomputer is reset. The initial values must therefore be set.

Note 1: When the V

level is applied to the CNV

pin, it is 03

at a reset.

Note 2: "00

" is read out when set bit 7 (SDDS) of the UART2 special mode register ( address 0377

) to "1".

(1)

(0004

)···

Processor mode register 0 (Note 1)

(2)

(0005

)···

Processor mode register 1

(3)

(0006

)···

System clock control register 0

(4)

(0007

)···

System clock control register 1

(5)

(0008

)···

Chip select control register

(6)

(0009

)···

Address match interrupt enable register

(7) Protect register

(000A

)···

(9)

(000F

)···

Watchdog timer control register

? ? ? ?

(11)

(0014

)···

Address match interrupt register 1

(0015

)···

(0016

)···

0 0 0

(12)

(002C

)···

DMA0 control register

0 0 0 0 0 ? 0 0

(13)

(003C

)···

DMA1 control register

0 0 0 0 0 ? 0 0

(21)

(004B

)···

DMA0 interrupt control register

? 0 0 0

(22)

(004C

)···

DMA1 interrupt control register

? 0 0 0

(23)

(004D

)···

Key input interrupt control register

? 0 0 0

(20)

(004A

)···

Bus collision detection interrupt
control register

0 0 0

(8)

(0010

)···

Address match interrupt register 0

(0011

)···

(0012

)···

0 0 0

(10)

(14)

(0044

)···

INT3 interrupt control register

0 0 ? 0 0 0

(15)

(0045

)···

Timer B5 interrupt control register

? 0 0 0

(16)

(0046

)···

Timer B4 interrupt control register

? 0 0 0

(17)

(0047

)···

Timer B3 interrupt control register

? 0 0 0

(18)

(0048

)···

SI/O4 interrupt control register

0 0 ? 0 0 0

(19)

(0049

)···

SI/O3 interrupt control register

0 0 ? 0 0 0

(24)

A-D conversion interrupt control register

(25)

(26)

UART2 transmit interrupt control register

UART2 receive interrupt control register

(004E

)···

? 0 0 0

(004F

)···

(0050

)···

? 0 0 0

(27)

(28)

(29)

(30)

UART0 transmit interrupt control register

UART0 receive interrupt control register

UART1 transmit interrupt control register

UART1 receive interrupt control register

(31)

(32)

(33)

(34)

(35)

(36)

(37)

Timer A0 interrupt control register

Timer A1 interrupt control register

Timer A2 interrupt control register

Timer A3 interrupt control register

Timer A4 interrupt control register

Timer B0 interrupt control register

Timer B1 interrupt control register

(38)

Timer B2 interrupt control register

(39)

INT0 interrupt control register

(40)

INT1 interrupt control register

(41)

INT2 interrupt control register

(45)

Three-phase output buffer register 0

(46)

Three-phase output buffer register 1

Three-phase PWM control register 0

(43)Three-phase PWM control register 1

(44)

(42)

Timer B3,4,5 count start flag

(47)

Timer B3 mode register

(48)

Timer B4 mode register

(49)

Timer B5 mode register

(50)

Interrupt cause select register

UART2 transmit/receive control register 1

UART2 transmit/receive control register 0

(0378

)···

(037D

)···

(037C

)···

0 0 0

0 0 0 0 1

0 1 0

0 0 0 0 0

(57)

UART2 transmit/receive mode register

(55)

(56)

(52)

SI/O4 control register

(54) UART2 special mode register

(0051

)···

(0052

)···

(0053

)···

(0054

)···

(0055

)···

(0056

)···

(0057

)···

(0058

)···

(0059

)···

(005A

)···

(005B

)···

(005C

)···

(005D

)···

(005E

)···

(005F

)···

(034A

)···

(034B

)···

(0348

)···

(0349

)···

(0340

)···

(035B

)···

(035C

)···

(035D

)···

(035F

)···

(0366

)···

(0377

)···

(0362

)···

SI/O3 control register

? 0 0 0

0 0

? 0 0 0

0 0

? 0 0 0

0 0

0 0 ?

0 0 0 0

0 0 ?

0 0 0 0

0 0 ?

0 0 0 0

(51)

0 0 0

(53) UART2 special mode register 2

(0376

)···

UART2 special mode register 3 (Note 2)

(0375

)···

Mitsubishi microcomputers

M16C / 62A Group

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

Reset

(0383

)···

Trigger select flag

(0384

)···

Up-down flag

(62)

(61)

(0396

)···

Timer A0 mode register

(63)

(0397

)···

Timer A1 mode register

(64)

(0398

)···

Timer A2 mode register

(67)

(039B

)···

Timer B0 mode register

(68)

(039C

)···

Timer B1 mode register

(69)

(039D

)···

Timer B2 mode register

(70)

(65)

(0399

)···

Timer A3 mode register

(66)

(039A

)···

Timer A4 mode register

(0382

)···

One-shot start flag

(60)

0 ?

0 0 0 0

0 0 ?

0 0 0 0

0 0 ?

0 0 0 0

(03AC

)···

UART1 transmit/receive control register 0

(75)

(03AD

)···

UART1 transmit/receive control register 1

(76)

(03B0

)···

UART transmit/receive control register 2

(77)

(03A0

)···

UART0 transmit/receive mode register

(71)

(03A4

)···

UART0 transmit/receive control register 0

(72)

(03A5

)···

UART0 transmit/receive control register 1

(73)

0 0 0

1 0 0 0

0 0 0

0 0 1 0

(03A8

)···

UART1 transmit/receive mode register

(74)

0 0 0

1 0 0 0

0 0 0

0 0 1 0

0 0 0 0

(03D7

)···

A-D control register 1

0 0 0

Count start flag

(0380

)···

(0381

)···

Clock prescaler reset flag

(58)

(59)

x : Nothing is mapped to this bit
? : Undefined

The content of other registers and RAM is undefined when the microcomputer is reset. The initial values
must therefore be set.

Note1: When the V

level is applied to the CNV

pin, it is 02

at a reset.

Note2: This register is only exist in flash memory version.

(03E2

)···

Port P0 direction register

(84)

(03E3

)···

Port P1 direction register

(85)

(03E6

)···

Port P2 direction register

(86)

(03E7

)···

Port P3 direction register

(87)

(03EA

)···

Port P4 direction register

(88)

(03EB

)···

Port P5 direction register

(89)

(03EE

)···

Port P6 direction register

(90)

(03EF

)···

Port P7 direction register

(91)

(03F2

)···

Port P8 direction register

(92)

(03F3

)···

Port P9 direction register

(93)

(03F6

)···

Port P10 direction register

(94)

(03FC

)···

Pull-up control register 0

(95)

(03FD

)···

Pull-up control register 1(Note1)

(96)

(03FE

)···

Pull-up control register 2

(97)

Port control register

(98)

0 0

(03DC

)···

D-A control register

(83)

Frame base register (FB)

(101)

Address registers (A0/A1)

(100)

Interrupt table register (INTB)

(102)

User stack pointer (USP)

(103)

Interrupt stack pointer (ISP)

(104)

Static base register (SB)

(105)

Flag register (FLG)

(106)

0000

00000

0000

Data registers (R0/R1/R2/R3)

(99)

0000

(03FF

)···

(03B6

)···

Flash memory control register 1 (Note2)

(78)

(107)

(03B7

)···

Flash memory control register 0 (Note2)

(03BA

)···

DMA1 cause select register

(03D4

)···

A-D control register 2

(80)

(03D6

)···

A-D control register 0

(81)

(82)

0 0 0

0 ? ? ?

0 0 0 0

(03B8

)···

DMA0 cause select register

(79)

0 0 0 1

? ? ? ?

? ? ?

(108)

Figure 1.5.4. Device's internal status after a reset is cleared

Mitsubishi microcomputers

M16C / 62A Group

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

SFR

Figure 1.6.1. Location of peripheral unit control registers (1)

0000

0001

0002

0003

0004

0005

0006

0007

0008

0009

000A

000B

000C

000D

000E

000F

0010

0011

0012

0013

0014

0015

0016

0017

0018

0019

001A

001B

001C

001D

001E

001F

0020

0021

0022

0023

0024

0025

0026

0027

0028

0029

002A

002B

002C

002D

002E

002F

0030

0031

0032

0033

0034

0035

0036

0037

0038

0039

003A

003B

003C

003D

003E

003F

0040

0041

0042

0043

0044

0045

0046

0047

0048

0049

004A

004B

004C

004D

004E

004F

0050

0051

0052

0053

0054

0055

0056

0057

0058

0059

005A

005B

005C

005D

005E

005F

0060

0061

0062

0063

0064

0065

032A

032B

032C

032D

032E

032F

0330

0331

0332

0333

0334

0335

0336

0337

0338

0339

033A

033B

033C

033D

033E

033F

DMA0 control register (DM0CON)

DMA0 source pointer (SAR0)

DMA0 transfer counter (TCR0)

DMA1 control register (DM1CON)

DMA1 source pointer (SAR1)

DMA1 transfer counter (TCR1)

DMA1 destination pointer (DAR1)

Watchdog timer start register (WDTS)
Watchdog timer control register (WDC)

Processor mode register 0 (PM0)

Address match interrupt register 0 (RMAD0)

Address match interrupt register 1 (RMAD1)

Chip select control register (CSR)

System clock control register 0 (CM0)
System clock control register 1 (CM1)

Address match interrupt enable register (AIER)
Protect register (PRCR)

Processor mode register 1(PM1)

DMA0 destination pointer (DAR0)

Timer A1 interrupt control register (TA1IC)

UART0 transmit interrupt control register (S0TIC)

Timer A0 interrupt control register (TA0IC)

Timer A2 interrupt control register (TA2IC)

UART0 receive interrupt control register (S0RIC)
UART1 transmit interrupt control register (S1TIC)
UART1 receive interrupt control register (S1RIC)

DMA1 interrupt control register (DM1IC)

DMA0 interrupt control register (DM0IC)

Key input interrupt control register (KUPIC)
A-D conversion interrupt control register (ADIC)

Bus collision detection interrupt control register (BCNIC)

UART2 transmit interrupt control register (S2TIC)
UART2 receive interrupt control register (S2RIC)

INT1 interrupt control register (INT1IC)

Timer B0 interrupt control register (TB0IC)

Timer B2 interrupt control register (TB2IC)

Timer A3 interrupt control register (TA3IC)

INT2 interrupt control register (INT2IC)

INT0 interrupt control register (INT0IC)

Timer B1 interrupt control register (TB1IC)

Timer A4 interrupt control register (TA4IC)

INT3 interrupt control register (INT3IC)
Timer B5 interrupt control register (TB5IC)
Timer B4 interrupt control register (TB4IC)
Timer B3 interrupt control register (TB3IC)
SI/O4 interrupt control register (S4IC)
INT5 interrupt control register (INT5IC)
SI/O3 interrupt control register (S3IC)
INT4 interrupt control register (INT4IC)

Note 1: Locations in the SFR area where nothing is allocated are reserved areas. Do not access these areas for read or write.

Mitsubishi microcomputers

M16C / 62A Group

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

SFR

Figure 1.6.2. Location of peripheral unit control registers (2)

0380

0381

0382

0383

0384

0385

0386

0387

0388

0389

038A

038B

038C

038D

038E

038F

0390

0391

0392

0393

0394

0395

0396

0397

0398

0399

039A

039B

039C

039D

039E

039F

03A0

03A1

03A2

03A3

03A4

03A5

03A6

03A7

03A8

03A9

03AA

03AB

03AC

03AD

03AE

03AF

03B0

03B1

03B2

03B3

03B4

03B5

03B6

03B7

03B8

03B9

03BA

03BB

03BC

03BD

03BE

03BF

0340

0341

0342

0343

0344

0345

0346

0347

0348

0349

034A

034B

034C

034D

034E

034F

0350

0351

0352

0353

0354

0355

0356

0357

0358

0359

035A

035B

035C

035D

035E

035F

0360

0361

0362

0363

0364

0365

0366

0367

0368

0369

036A

036B

036C

036D

036E

036F

0370

0371

0372

0373

0374

0375

0376

0377

0378

0379

037A

037B

037C

037D

037E

037F

Timer A1-1 register (TA11)

Timer A2-1 register (TA21)

Dead time timer(DTT)

Timer B2 interrupt occurrence frequency set counter(ICTB2)

Three-phase PWM control register 0(INVC0)
Three-phase PWM control register 1(INVC1)

Three-phase output buffer register 0(IDB0)
Three-phase output buffer register 1(IDB1)

Timer B3 register (TB3)

Timer B4 register (TB4)

Timer B5 register (TB5)

Timer B3, 4, 5 count start flag (TBSR)

Timer B3 mode register (TB3MR)
Timer B4 mode register (TB4MR)
Timer B5 mode register (TB5MR)

Interrupt cause select register (IFSR)

Timer A0 (TA0)

Timer A1 (TA1)

Timer A2 (TA2)

Timer B0 (TB0)

Timer B1 (TB1)

Timer B2 (TB2)

Count start flag (TABSR)

One-shot start flag (ONSF)

Timer A0 mode register (TA0MR)
Timer A1 mode register (TA1MR)
Timer A2 mode register (TA2MR)

Timer B0 mode register (TB0MR)
Timer B1 mode register (TB1MR)
Timer B2 mode register (TB2MR)

Up-down flag (UDF)

Timer A3 (TA3)

Timer A4 (TA4)

Timer A3 mode register (TA3MR)
Timer A4 mode register (TA4MR)

Trigger select register (TRGSR)

Clock prescaler reset flag (CPSRF)

UART0 transmit/receive mode register (U0MR)

UART0 transmit buffer register (U0TB)

UART0 receive buffer register (U0RB)

UART1 transmit/receive mode register (U1MR)

UART1 transmit buffer register (U1TB)

UART1 receive buffer register (U1RB)

UART0 bit rate generator (U0BRG)

UART0 transmit/receive control register 0 (U0C0)

UART0 transmit/receive control register 1 (U0C1)

UART1 bit rate generator (U1BRG)

UART1 transmit/receive control register 0 (U1C0)

UART1 transmit/receive control register 1 (U1C1)

DMA1 request cause select register (DM1SL)

DMA0 request cause select register (DM0SL)

CRC data register (CRCD)

CRC input register (CRCIN)

SI/O3

transmit/receive register

(S3TRR)

SI/O4

transmit/receive register

(S4TRR)

SI/O3 control register (S3C)
SI/O3

bit rate generator

(S3BRG)

SI/O4

bit rate generator

(S4BRG)

SI/O4 control register (S4C)

UART2 special mode register (U2SMR)

UART2 receive buffer register (U2RB)

UART2 transmit buffer register (U2TB)

UART2 transmit/receive control register 0 (U2C0)

UART2 transmit/receive mode register (U2MR)

UART2 transmit/receive control register 1 (U2C1)

UART2 bit rate generator (U2BRG)

UART transmit/receive control register 2 (UCON)

Timer A4-1 register (TA41)

UART2 special mode register 2(U2SMR2)

Note 1: This register is only exist in flash memory version.
Note 2: Locations in the SFR area where nothing is allocated are reserved areas. Do not access these areas for

read or write.

Flash memory control register 0 (FMR0) (Note1)

Flash memory control register 1 (FMR1) (Note1)

UART2 special mode register 3(U2SMR3)

Mitsubishi microcomputers

M16C / 62A Group

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

SFR

Figure 1.6.3. Location of peripheral unit control registers (3)

03C0

03C1

03C2

03C3

03C4

03C5

03C6

03C7

03C8

03C9

03CA

03CB

03CC

03CD

03CE

03CF

03D0

03D1

03D2

03D3

03D4

03D5

03D6

03D7

03D8

03D9

03DA

03DB

03DC

03DD

03DE

03DF

03E0

03E1

03E2

03E3

03E4

03E5

03E6

03E7

03E8

03E9

03EA

03EB

03EC

03ED

03EE

03EF

03F0

03F1

03F2

03F3

03F4

03F5

03F6

03F7

03F8

03F9

03FA

03FB

03FC

03FD

03FE

03FF

A-D register 7 (AD7)

A-D register 0 (AD0)

A-D register 1 (AD1)

A-D register 2 (AD2)

A-D register 3 (AD3)

A-D register 4 (AD4)

A-D register 5 (AD5)

A-D register 6 (AD6)

Port P0 (P0)

Port P0 direction register (PD0)

Port P1 (P1)

Port P1 direction register (PD1)

Port P2 (P2)

Port P2 direction register (PD2)

Port P3 (P3)

Port P3 direction register (PD3)

Port P4 (P4)

Port P4 direction register (PD4)

Port P5 (P5)

Port P5 direction register (PD5)

Port P6 (P6)

Port P6 direction register (PD6)

Port P7 (P7)

Port P7 direction register (PD7)

Port P8 (P8)

Port P8 direction register (PD8)

Port P9 (P9)

Port P9 direction register (PD9)
Port P10 (P10)

Port P10 direction register (PD10)

Pull-up control register 0 (PUR0)
Pull-up control register 1 (PUR1)
Pull-up control register 2 (PUR2)

A-D control register 0 (ADCON0)
A-D control register 1 (ADCON1)
D-A register 0 (DA0)

D-A register 1 (DA1)

D-A control register (DACON)

A-D control register 2 (ADCON2)

Port control register (PCR)

Note : Locations in the SFR area where nothing is allocated are reserved

areas. Do not access these areas for read or write.

Mitsubishi microcomputers

M16C / 62A Group

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

Software Reset

Software Reset

Writing "1" to bit 3 of the processor mode register 0 (address 0004

) applies a (software) reset to the

microcomputer. A software reset has the same effect as a hardware reset. The contents of internal RAM

are preserved.

Software Reset

Processor Mode

(1) Types of Processor Mode

One of three processor modes can be selected: single-chip mode, memory expansion mode, and micro-

processor mode. The functions of some pins, the memory map, and the access space differ according to

the selected processor mode.

· Single-chip mode

In single-chip mode, only internal memory space (SFR, internal RAM, and internal ROM) can be

accessed. However, after the reset has been released and the operation of shifting from the micropro-

cessor mode has started ("H" applied to the CNV

pin), the internal ROM area cannot be accessed

even if the CPU shifts to the single-chip mode.

Ports P0 to P10 can be used as programmable I/O ports or as I/O ports for the internal peripheral

functions.

· Memory expansion mode

In memory expansion mode, external memory can be accessed in addition to the internal memory

space (SFR, internal RAM, and internal ROM). However, after the reset has been released and the

operation of shifting from the microprocessor mode has started ("H" applied to the CNV

pin), the

internal ROM area cannot be accessed even if the CPU shifts to the memory expansion mode.

In this mode, some of the pins function as the address bus, the data bus, and as control signals. The

number of pins assigned to these functions depends on the bus and register settings. (See "Bus

Settings" for details.)

· Microprocessor mode

In microprocessor mode, the SFR, internal RAM, and external memory space can be accessed. The

internal ROM area cannot be accessed.

In this mode, some of the pins function as the address bus, the data bus, and as control signals. The

number of pins assigned to these functions depends on the bus width and register settings. (See "Bus

Settings" for details.)

(2) Setting Processor Modes

The processor mode is set using the CNV

pin and the processor mode bits (bits 1 and 0 at address

0004

). Do not set the processor mode bits to "10

Regardless of the level of the CNV

pin, changing the processor mode bits selects the mode. Therefore,

never change the processor mode bits when changing the contents of other bits. Do not change the

processor mode bits simultaneously with other bits when changing the processor mode bits "01

" or

"11

". Change the processor mode bits after changing the other bits. Also do not attempt to shift to or from

the microprocessor mode within the program stored in the internal ROM area.

· Applying V

to CNV

pin

The microcomputer begins operation in single-chip mode after being reset. Memory expansion mode

is selected by writing "01

" to the processor mode bits.

· Applying V

to CNV

pin

The microcomputer starts to operate in microprocessor mode after being reset.

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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

Processor Mode

Figure 1.7.1. Processor mode register 0 and 1

Processor mode register 0 (Note 1)

Symbol

Address

When reset

PM0

0004

(Note 2)

Bit name

Function

Bit symbol

0 0: Single-chip mode
0 1: Memory expansion mode
1 0: Do not set
1 1: Microprocessor mode

b1 b0

PM03

PM01

PM00

Processor mode bit

PM02

R/W mode select bit

0 : RD,BHE,WR
1 : RD,WRH,WRL

Software reset bit

The device is reset when this bit is set
to "1". The value of this bit is "0" when
read.

PM04

0 0 : Multiplexed bus is not used
0 1 : Allocated to CS2 space
1 0 : Allocated to CS1 space
1 1 : Allocated to entire space (Note4)

b5 b4

Multiplexed bus space
select bit

PM05

PM06

PM07

Port P4

to P4

function

select bit (Note 3)

0 : Address output
1 : Port function
(Address is not output)

BCLK output disable bit

0 : BCLK is output
1 : BCLK is not output
(Pin is left floating)

Note 1: Set bit 1 of the protect register (address 000A

) to "1" when writing new

values to this register.

Note 2: If the V

voltage is applied to the CNV

, the value of this register when

reset is 03

. (PM00 and PM01 both are set to "1".)

Note 3: Valid in microprocessor and memory expansion modes.
Note 4: If the entire space is of multiplexed bus in memory expansion mode, choose an 8-

bit width.The processor operates using the separate bus after reset is revoked, so the entire
space multiplexed bus cannot be chosen in microprocessor mode.
P3

to P3

become a port if the entire space multiplexed bus is chosen, so only 256 bytes can

be used in each chip select.

Processor mode register 1 (Note 1)

Symbol

Address

When reset

PM1

0005

00000XX0

Bit name

Function

Bit symbol

Nothing is assigned.

In an attempt to write to these bits, write "0". The value, if read, turns
out to be

indeterminate.

Reserved bit

Must always be set to "0"

Note 1: Set bit 1 of the protect register (address 000A

) to "1" when writing new values to this register.

Note 2: When the reset is revoked, this bit is set to "0". To expand the internal area, set this bit to "1"

in user program. And the top of user program must be allocated to D0000

or subsequent

address.

PM17

Wait bit

0 : No wait state
1 : Wait state inserted

Reserved bit

Must always be set to "0"

Internal reserved area
expansion bit (Note 2)

PM13

0: The internal RAM area is 15 kbytes
or less and the internal ROM area is
192 kbytes or less
1: Expands the internal RAM area
and internal ROM area to over 15
kbytes and to over 192 kbytes
respectively. (Note 2)

0 0

Reserved bit

Must always be set to "0"

Reserved bit

Must always be set to "0"

Figure 1.7.1 shows the processor mode register 0 and 1.

Figure 1.7.2 shows the memory maps applicable for each of the modes.

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Processor Mode

Single-chip mode

SFR area

Internal

RAM area

Inhibited

Internal

ROM area

Microprocessor mode

SFR area

Internal

RAM area

External

area

Internally

reserved area

00000

00400

XXXXX

YYYYY

FFFFF

D0000

External area :

Accessing this area allows the user to
access a device connected externally
to the microcomputer.

04000

Memory expansion mode

SFR area

Internal

RAM area

External

area

Internal

ROM area

Internally

reserved area

Internally

reserved area

Note : These memory maps show an instance in which PM13 is set to 0; but in the case of products in which the
internal RAM and the internal ROM are expanded to over 15 Kbytes and 192 Kbytes, respectively, they show
an instance in which PM13 is set to 1.

Address YYYYY

3K bytes

00FFF

053FF

017FF

013FF

Address XXXXX

ROM size

02BFF

5K bytes

4K bytes

10K bytes

20K bytes

RAM size

32K bytes

C0000

E8000

F0000

E0000

96K bytes

64K bytes

128K bytes

256K bytes

F8000

Figure 1.7.2. Memory maps in each processor mode (without memory area expansion, normal mode)

Internal Reserved Area Expansion Bit (PM13)

This bit expands the internal RAM area and the internal ROM area, and changes the chip select area. In

M30624MGA/FGA, for example, to set this bit to "1" expands the internal RAM area and the internal ROM

area to 20 Kbytes and 256 Kbytes respectively. Refer to Figure 1.7.3 for the chip select area. When the

reset is revoked, this bit is set to "0". To expand the internal area, set this bit to "1" in user program. And

the top of user program must be allocated to D0000

or subsequent address.

In the case of the product in which the internal ROM is 192 Kbytes or less and the internal RAM is 15

Kbytes or less, set this bit to "0" when this product is used in the memory expansion mode or the micro-

processor mode. When the product is used in the single chip mode, the internal area is not expanded and

any action is not affected, even if this bit is set to "1".

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Processor Mode

SFR area

(1K bytes)

Internal RAM area

(15K bytes)

External area

00000

00400

FFFFF

D0000

08000

Internal RAM area

(15K bytes)

External area

Internal ROM area

(192K bytes)

CS3

(16K bytes)

CS2

(128K bytes)

CS1

(32K bytes)

CS0

Memory expansion mode

: 640K bytes
Microprocessor mode
: 832K bytes

28000

30000

04000

Internal reserved area expansion bit="0"

SFR area

(1K bytes)

After reset

SFR area

(1K bytes)

00000

00400

FFFFF

C0000

08000

Internal RAM area

(20K bytes)

Internal ROM area

(256K bytes)

CS3

(8K bytes)

CS2

(128K bytes)

CS1

(32K bytes)

CS0

Memory expansion mode
: 576K bytes
Microprocessor mode
: 832K bytes

28000

30000

05400

Internal reserved area expansion bit="1" (Note)

SFR area

(1K bytes)

After reset, and set the

Internal reserved area expansion bit to "1"

06000

BFFFF

CFFFF

Note: When the reset is revoked, this bit is set to "0". Therefore, the top
of the user program must be allocated to D0000

or subsequent address.

Memory expansion

mode

Microprocessor

mode

Memory expansion

mode

Microprocessor

mode

Internal RAM area

(20K bytes)

Internal reserved area

External area

Internal reserved area

Figure 1.7.3. Memory location and chip select area in each processor mode

Figure 1.7.3 shows the memory maps and the chip selection areas effected by PM13 (the internal re-

served area expansion bit) in each processor mode for the product having an internal RAM of more than

15K bytes and a ROM of more than 192K bytes.

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Bus Settings

Bus Settings

The BYTE pin and bits 4 to 6 of the processor mode register 0 (address 0004

) are used to change the bus settings.

Table 1.8.1 shows the factors used to change the bus settings.

Bus setting

Switching factor

Switching external address bus width

Bit 6 of processor mode register 0

Switching external data bus width

BYTE pin

Switching between separate and multiplex bus

Bits 4 and 5 of processor mode register 0

(1) Selecting external address bus width

The address bus width for external output in the 1M bytes of address space can be set to 16 bits (64K

bytes address space) or 20 bits (1M bytes address space). When bit 6 of the processor mode register 0

is set to "1", the external address bus width is set to 16 bits, and P2 and P3 become part of the address

bus. P4

to P4

can be used as programmable I/O ports. When bit 6 of processor mode register 0 is set

to "0", the external address bus width is set to 20 bits, and P2, P3, and P4

to P4

become part of the

address bus.

(2) Selecting external data bus width

The external data bus width can be set to 8 or 16 bits. (Note, however, that only the separate bus can be

set.) When the BYTE pin is "L", the bus width is set to 16 bits; when "H", it is set to 8 bits. (The internal bus

width is permanently set to 16 bits.) While operating, fix the BYTE pin either to "H" or to "L".

(3) Selecting separate/multiplex bus

The bus format can be set to multiplex or separate bus using bits 4 and 5 of the processor mode register 0.

· Separate bus

In this mode, the data and address are input and output separately. The data bus can be set using the

BYTE pin to be 8 or 16 bits. When the BYTE pin is "H", the data bus is set to 8 bits and P0 functions as

the data bus and P1 as a programmable I/O port. When the BYTE pin is "L", the data bus is set to 16

bits and P0 and P1 are both used for the data bus.

When the separate bus is used for access, a software wait can be selected.

· Multiplex bus

In this mode, data and address I/O are time multiplexed. With the BYTE pin = "H", the 8 bits from D

are multiplexed with A

to A

With the BYTE pin = "L", the 8 bits from D

to D

are multiplexed with A

to A

. D

to D

are not

multiplexed. In this case, the external devices connected to the multiplexed bus are mapped to the

microcomputer's even addresses (every 2nd address). To access these external devices, access the

even addresses as bytes.

The ALE signal latches the address. It is output from P5

Before using the multiplex bus for access, be sure to insert a software wait.

If the entire space is of multiplexed bus in memory expansion mode, choose an 8-bit width.

The processor operates using the separate bus after reset is revoked, so the entire space multiplexed

bus cannot be chosen in microprocessor mode.

to P3

become a port if the entire space multiplexed bus is chosen, so only 256 bytes can be used

in each chip select.

Table 1.8.1. Factors for switching bus settings

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Bus Settings

I/O port

ALE

I/O port

RDY

to P0

I/O port

Data bus

I/O port

Either CS1 or CS2 is for
multiplexed bus and others
are for separate bus

(separate bus)

multiplexed

bus for the

entire

space

Single-chip

mode

Memory expansion mode/microprocessor modes

Memory

expansion mode

Data bus width
BYTE pin level

Port P4

to P4

function select bit = 0

"01", "10"

"00"

"11" (Note 1)

8 bit

"H"

8 bits

"H"

16 bits

"L"

8 bits

"H"

16 bits

"L"

Note 1: If the entire space is of multiplexed bus in memory expansion mode, choose an 8-bit width.

The processor operates using the separate bus after reset is revoked, so the entire space multiplexed bus cannot be
chosen in microprocessor mode.
P3

to P3

become a port if the entire space multiplexed bus is chosen, so only 256 bytes can be used

in each chip select.

Note 2: Address bus when in separate bus mode.

Processor mode

Multiplexed bus
space select bit

CS (chip select) or programmable I/O port

(For details, refer to "Bus control")

Outputs RD, WRL, WRH, and BCLK or RD, BHE, WR, and BCLK

(For details, refer to "Bus control")

Port P4

to P4

function select bit = 1

to P1

I/O port

Data bus

I/O port

Data bus

I/O port

to P2

I/O port

Address bus

/data bus

(Note 2)

/data bus

(Note 2)

/data bus

I/O port

Address bus

/data bus

(Note 2)

/data bus

I/O port

Address bus

/data bus

(Note 2)

to P3

I/O port

Address bus

I/O port

to P4

I/O port

to P4

I/O port

Address bus

I/O port

to P4

I/O port

to P5

I/O port

HLDA

I/O port

HOLD

Table 1.8.2. Pin functions for each processor mode

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Bus Control

Bus Control

The following explains the signals required for accessing external devices and software waits. The signals

required for accessing the external devices are valid when the processor mode is set to memory expansion

mode and microprocessor mode. The software waits are valid in all processor modes.

(1) Address bus/data bus

The address bus consists of the 20 pins A

to A

for accessing the 1M bytes of address space.

The data bus consists of the pins for data I/O. When the BYTE pin is "H", the 8 ports D

to D

function

as the data bus. When BYTE is "L", the 16 ports D

to D

function as the data bus.

When a change is made from single-chip mode to memory expansion mode, the value of the address

bus is undefined until external memory is accessed.

(2) Chip select signal

The chip select signal is output using the same pins as P4

to P4

. Bits 0 to 3 of the chip select control

) set each pin to function as a port or to output the chip select signal. The chip

select control register is valid in memory expansion mode and microprocessor mode. In single-chip

mode, P4

to P4

function as programmable I/O ports regardless of the value in the chip select control

_______

In microprocessor mode, only CS0 outputs the chip select signal after the reset state has been can-

_______

celled. CS1 to CS3 function as input ports. Figure 1.9.1 shows the chip select control register.

The chip select signal can be used to split the external area into as many as four blocks. Tables 1.9.1

and 1.9.2 show the external memory areas specified using the chip select signal.

Processor mode

Memory expansion mode

Chip select signal

CS0

CS1

CS2

CS3

30000

CFFFF

(640K bytes)

Microprocessor mode

28000

2FFFF

(32K bytes)

08000

27FFF

(128K bytes)

04000

07FFF

(16K bytes)

30000

FFFFF

(832K bytes)

Table 1.9.1. External areas specified by the chip select signals

(A product having an internal RAM equal to or less than 15K bytes and a ROM equal to or less than 192K bytes)(Note)

Note :Be sure to set bit 3 (PM13) of processor mode register 1 to "0".

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Bus Control

Function

Bit symbol

Bit name

Chip select control register

Symbol

Address When

reset

CSR

0008

CS1

CS0

CS3

CS2

CS0 output enable bit

CS1 output enable bit

CS2 output enable bit

CS3 output enable bit

CS1W

CS0W

CS3W

CS2W

CS0 wait bit

CS1 wait bit

CS2 wait bit

CS3 wait bit

0 : Chip select output disabled

(Normal port pin)

1 : Chip select output enabled

0 : Wait state inserted
1 : No wait state

Figure 1.9.1. Chip select control register

Processor mode

Memory expansion mode

Chip select signal

CS0

CS1

CS2

CS3

30000

to CFFFF

(640K bytes)

28000

2FFFF

(32K bytes)

08000

27FFF

(128K bytes)

When PM13=0

Microprocessor mode

30000

to BFFFF

(576K bytes)

03000

to FFFFF

(816K bytes)

When PM13=0

When PM13=1

04000

07FFF

(16K bytes)

06000

07FFF

(8K bytes)

Table 1.9.2. External areas specified by the chip select signals

(A product having an internal RAM of more than 15K bytes and a ROM of more than 192K bytes)

The timing of the chip select signal changing to "L"(active) is synchronized with the address bus. But the

timing of the chip select signal changing to "H" depends on the area which will be accessed in the next

cycle. Figure 1.9.2 shows the output example of the address bus and chip select signal.

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Bus Control

Figure 1.9.2. Output Examples about Address Bus and Chip Select Signal (Separated Bus without

Wait)

Example 1) After access the external area, both the address signal and

the chip select signal change concurrently in the next cycle.

In this example, after access to the external area(i), an access to the area
indicated by the other chip select signal(j) will occur in the next cycle. In
this case, both the address bus and the chip select signal change between
the two cycles.

Note : These examples show the address bus and chip select signal within the successive two cycles.
According to the combination of these examples, the chip select can be elongated to over 2cycles.

BCLK

Read/Write

signal

Data bus

Address bus

Chip select

(CS i)

Access to the
External Area( i )

Chip select

(CS j)

Access to the Other
External Area( j )

Address

Data

Example 2) After access the external area, only the chip select signal

changes in the next cycle (the address bus does not change).

In this example, an access to the internal ROM or the internal RAM in the
next cycle will occur, after access to the external area. In this case, the
chip select signal changes between the two cycles, but the address does
not change.

Example 4) After access the external area, either the address signal and

the chip select signal do not change in the next cycle.

In this example, any access to any area does not occur in the next cycle
(either instruction prefetch does not occur). In this case,either the address
bus and chip select signal do not change between the two cycles.

Example 3) After access the external area, only the address bus changes

in the next cycle (the chip select signal does not change).

In this example, after access to the external area(i), an access to the area
indicated by the same chip select signal(i) will occur in the next cycle. In
this case, the address bus changes between the two cycles, but the chip
select signal does not change.

BCLK

Access to the
External Area

Internal ROM/RAM
Access

Read/Write

signal

Data bus

Address bus

Chip select

Address

Data

BCLK

Access to the
External Area

No Access

Read/Write

signal

Data bus

Address bus

Chip select

Address

Data

BCLK

Access to the
External Area( i )

Access to the Same
External Area( i )

Read/Write

signal

Data bus

Address bus

Chip select

(CS i)

Address

Data

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Bus Control

_____

______

________

Table 1.9.4. Operation of RD, WR, and BHE signals

Status of external data bus

BHE

Write 1 byte of data to odd address

Read 1 byte of data from odd address

Write 1 byte of data to even address

Read 1 byte of data from even address

Data bus width

H / L

8-bit

(BYTE = "H")

Write data to both even and odd addresses

Read data from both even and odd addresses

Write 1 byte of data

Read 1 byte of data

16-bit

(BYTE = "L")

Not used

Status of external data bus

Read data

Write 1 byte of data to even address

Write 1 byte of data to odd address

Write data to both even and odd addresses

WRH

WRL

Data bus width

16-bit

(BYTE = "L")

_____

________

_________

Table 1.9.3. Operation of RD, WRL, and WRH signals

(3) Read/write signals

With a 16-bit data bus (BYTE pin ="L"), bit 2 of the processor mode register 0 (address 0004

) select the

_____ ________

______

_____

________

_________

combinations of RD, BHE, and WR signals or RD, WRL, and WRH signals. With an 8-bit data bus (BYTE

_____

______

_______

pin = "H"), use the combination of RD, WR, and BHE signals. (Set bit 2 of the processor mode register 0

(address 0004

) to "0".) Tables 1.9.3 and 1.9.4 show the operation of these signals.

_____

______

________

After a reset has been cancelled, the combination of RD, WR, and BHE signals is automatically selected.

_____ _________

_________

When switching to the RD, WRL, and WRH combination, do not write to external memory until bit 2 of the

processor mode register 0 (address 0004

) has been set (Note).

Note: Before attempting to change the contents of the processor mode register 0, set bit 1 of the protect

) to "1".

(4) ALE signal

The ALE signal latches the address when accessing the multiplex bus space. Latch the address when the

ALE signal falls.

When BYTE pin = "H"

When BYTE pin = "L"

ALE

Address

Data (Note 1)

Address (Note 2)

to D

to A

ALE

Address

Data (Note 1)

Address

to D

to A

Address

Note 1: Floating when reading.
Note 2: When multiplexed bus for the entire space is selected, these are I/O ports.

Figure 1.9.3. ALE signal and address/data bus

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Bus Control

_____

________

Figure 1.9.4. Example of RD signal extended by RDY signal

BCLK

(i=0 to 3)

RDY

tsu(RDY - BCLK)

BCLK

(i=0 to 3)

RDY

tsu(RDY - BCLK)

In an instance of separate bus

In an instance of multiplexed bus

Accept timing of RDY signal

: Wait using RDY signal

: Wait using software

Accept timing of RDY signal

________

Note: The RDY signal cannot be received immediately prior to a software wait.

Table 1.9.5. Microcomputer status in wait state (Note)

Item

Status

Oscillation

___

_____

R/W signal, address bus, data bus, CS

________

Maintain status when RDY signal received

__________

ALE signal, HLDA, programmable I/O ports

Internal peripheral circuits

________

(5) The RDY signal

________

RDY is a signal that facilitates access to an external device that requires long access time. As shown in

________

Figure 1.9.4, if an "L" is being input to the RDY at the BCLK falling edge, the bus turns to the wait state. If

________

an "H" is being input to the RDY pin at the BCLK falling edge, the bus cancels the wait state. Table 1.9.5

shows the state of the microcomputer with the bus in the wait state, and Figure 1.9.4 shows an example

____

________

in which the RD signal is prolonged by the RDY signal.

________

The RDY signal is valid when accessing the external area during the bus cycle in which bits 4 to 7 of the

________

chip select control register (address 0008

) are set to "0". The RDY signal is invalid when setting "1" to

________

all bits 4 to 7 of the chip select control register (address 0008

), but the RDY pin should be treated as

properly as in non-using.

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Bus Control

Table 1.9.6. Microcomputer status in hold state

Item

Status

Oscillation

___

_____

_______

R/W signal, address bus, data bus, CS, BHE

Floating

Programmable I/O ports

P0, P1, P2, P3, P4, P5

Floating

P6, P7, P8, P9, P10

Maintains status when hold signal is received

__________

HLDA

Output "L"

Internal peripheral circuits

ON (but watchdog timer stops)

ALE signal

Undefined

__________

HOLD > DMAC > CPU

(6) Hold signal

The hold signal is used to transfer the bus privileges from the CPU to the external circuits. Inputting "L" to

__________

the HOLD pin places the microcomputer in the hold state at the end of the current bus access. This status

__________

is maintained and "L" is output from the HLDA pin as long as "L" is input to the HOLD pin. Table 1.9.6

shows the microcomputer status in the hold state.

__________

Bus-using priorities are given to HOLD, DMAC, and CPU in order of decreasing precedence.

Figure 1.9.5. Bus-using priorities

(7) External bus status when the internal area is accessed

Table 1.9.7 shows the external bus status when the internal area is accessed.

Table 1.9.7. External bus status when the internal area is accessed

Item

SFR accessed

Internal ROM/RAM accessed

Address bus

Address output

Maintain status before accessed

address of external area

Data bus

When read

Floating

When write

Output data

Undefined

RD, WR, WRL, WRH

RD, WR, WRL, WRH output

Output "H"

BHE

BHE output

Maintain status before accessed

status of external area

Output "H"

ALE

Output "L"

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Bus Control

(9) Software wait

A software wait can be inserted by setting the wait bit (bit 7) of the processor mode register 1 (address

0005

) (Note) and bits 4 to 7 of the chip select control register (address 0008

A software wait is inserted in the internal ROM/RAM area and in the external memory area by setting the

wait bit of the processor mode register 1. When set to "0", each bus cycle is executed in one BCLK cycle.

When set to "1", each bus cycle is executed in two or three BCLK cycles. After the microcomputer has been

reset, this bit defaults to "0". When set to "1", a wait is applied to all memory areas (two or three BCLK

cycles), regardless of the contents of bits 4 to 7 of the chip select control register. Set this bit after referring

to the recommended operating conditions (main clock input oscillation frequency) of the electric character-

________

istics. However, when the user is using the RDY signal, the relevant bit in the chip select control register's

bits 4 to 7 must be set to "0".

When the wait bit of the processor mode register 1 is "0", software waits can be set independently for

each of the 4 areas selected using the chip select signal. Bits 4 to 7 of the chip select control register

_______

correspond to chip selects CS0 to CS3. When one of these bits is set to "1", the bus cycle is executed in

one BCLK cycle. When set to "0", the bus cycle is executed in two or three BCLK cycles. These bits

default to "0" after the microcomputer has been reset.

The SFR area is always accessed in two BCLK cycles regardless of the setting of these control bits. Also,

insert a software wait if using the multiplex bus to access the external memory area.

Table 1.9.8 shows the software wait and bus cycles. Figure 1.9.6 shows example of bus timing when

using software waits.

Note: Before attempting to change the contents of the processor mode register 1, set bit 1 of the protect

) to "1".

Area

Bus status

Wait bit

Bits 4 to 7 of chip select

control register

Bus cycle

Invalid

2 BCLK cycles

External
memory

area

Separate bus

1 BCLK cycle

Separate bus

2 BCLK cycles

Separate bus

0 (Note)

2 BCLK cycles

Multiplex bus

3 BCLK cycles

Multiplex bus

3 BCLK cycles

0 (Note)

SFR

Internal

ROM/RAM

Invalid

1 BCLK cycle

Invalid

2 BCLK cycles

Note: When using the RDY signal, always set to "0".

Table 1.9.8. Software waits and bus cycles

(8) BCLK output

The user can choose the BCLK output by use of bit 7 of processor mode register 0 (0004

) (Note).

When set to "1", the output floating.

Note: Before attempting to change the contents of the processor mode register 0, set bit 1 of the protect

) to "1".

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Clock Generating Circuit

Figure 1.10.2. Examples of sub-clock

Table 1.10.1. Main clock and sub-clock generating circuits

Clock Generating Circuit

The clock generating circuit contains two oscillator circuits that supply the operating clock sources to the

CPU and internal peripheral units.

Example of oscillator circuit

Figure 1.10.1 shows some examples of the main clock circuit, one using an oscillator connected to the

circuit, and the other one using an externally derived clock for input. Figure 1.10.2 shows some examples

of sub-clock circuits, one using an oscillator connected to the circuit, and the other one using an externally

derived clock for input. Circuit constants in Figures 1.10.1 and 1.10.2 vary with each oscillator used. Use

the values recommended by the manufacturer of your oscillator.

Figure 1.10.1. Examples of main clock

Main clock generating circuit

Sub-clock generating circuit

Use of clock

· CPU's operating clock source

· Internal peripheral units'

· Timer A/B's count clock

operating clock source

source

Usable oscillator

Ceramic or crystal oscillator

Crystal oscillator

Pins to connect oscillator

, X

OUT

CIN

, X

COUT

Oscillation stop/restart function

Available

Oscillator status immediately after reset

Oscillating

Stopped

Other

Externally derived clock can be input

Microcomputer

(Built-in feedback resistor)

OUT

Externally derived clock

Open

Vcc

Vss

Microcomputer

(Built-in feedback resistor)

OUT

(Note)

Note: Insert a damping resistor if required. The resistance will vary depending on the oscillator and the oscillation drive

capacity setting. Use the value recommended by the maker of the oscillator.
When the oscillation drive capacity is set to low, check that oscillation is stable. Also, if the oscillator manufacturer's
data sheet specifies that a feedback resistor be added external to the chip, insert a feedback resistor between X

and X

OUT

following the instruction.

Microcomputer

(Built-in feedback resistor)

CIN

COUT

Externally derived clock

Open

Vcc

Vss

Note: Insert a damping resistor if required. The resistance will vary depending on the oscillator and the oscillation drive

CIN

and X

COUT

following the instruction.

Microcomputer

(Built-in feedback resistor)

CIN

COUT

(Note)

CIN

COUT

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Clock Generating Circuit

The following paragraphs describes the clocks generated by the clock generating circuit.

(1) Main clock

The main clock is generated by the main clock oscillation circuit. After a reset, the clock is divided by 8 to

the BCLK. The clock can be stopped using the main clock stop bit (bit 5 at address 0006

). Stopping the

clock, after switching the operating clock source of CPU to the sub-clock, reduces the power dissipation.

After the oscillation of the main clock oscillation circuit has stabilized, the drive capacity of the main clock

oscillation circuit can be reduced using the X

-X

OUT

drive capacity select bit (bit 5 at address 0007

Reducing the drive capacity of the main clock oscillation circuit reduces the power dissipation. This bit

changes to "1" when shifting from high-speed/medium-speed mode to stop mode and at a reset. When

shifting from low-speed/low power dissipation mode to stop mode, the value before stop mode is re-

tained.

(2) Sub-clock

The sub-clock is generated by the sub-clock oscillation circuit. No sub-clock is generated after a reset.

After oscillation is started using the port X

select bit (bit 4 at address 0006

), the sub-clock can be

selected as the BCLK by using the system clock select bit (bit 7 at address 0006

). However, be sure

that the sub-clock oscillation has fully stabilized before switching.

After the oscillation of the sub-clock oscillation circuit has stabilized, the drive capacity of the sub-clock

oscillation circuit can be reduced using the X

CIN

-X

COUT

drive capacity select bit (bit 3 at address 0006

Reducing the drive capacity of the sub-clock oscillation circuit reduces the power dissipation. This bit

changes to "1" when shifting to stop mode and at a reset.

When the X

CIN

COUT

is used, set ports P8

and P8

as the input ports without pull-up.

(3) BCLK

The BCLK is the clock that drives the CPU, and is f

or the clock is derived by dividing the main clock by

1, 2, 4, 8, or 16. The BCLK is derived by dividing the main clock by 8 after a reset. The BCLK signal can

be output from BCLK pin by the BCLK output disable bit (bit 7 at address 0004

) in the memory expan-

sion and the microprocessor modes.

The main clock division select bit 0(bit 6 at address 0006

) changes to "1" when shifting from high-

speed/medium-speed to stop mode and at reset. When shifting from low-speed/low power dissipation

mode to stop mode, the value before stop mode is retained.

(4) Peripheral function clock(f

, f

1SIO2

, f

8SIO2

32SIO2

)

The clock for the peripheral devices is derived from the main clock or by dividing it by 1, 8, or 32. The

peripheral function clock is stopped by stopping the main clock or by setting the WAIT peripheral function

clock stop bit (bit 2 at 0006

) to "1" and then executing a WAIT instruction.

(5) f

C32

This clock is derived by dividing the sub-clock by 32. It is used for the timer A and timer B counts.

(6) f

This clock has the same frequency as the sub-clock. It is used for the BCLK and for the watchdog timer.

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Clock Generating Circuit

Figure 1.10.4 shows the system clock control registers 0 and 1.

Figure 1.10.4. Clock control registers 0 and 1

System clock control register 0 (Note 1)

Symbol

Address

When reset

CM0

0006

Bit name

Function

Bit symbol

0 0 : I/O port P5

0 1 : f

output

1 0 : f

output

1 1 : f

output

b1 b0

CM07

CM05

CM04

CM03

CM01

CM02

CM00

CM06

Clock output function
select bit
(Valid only in single-chip
mode)

WAIT peripheral function
clock stop bit

0 : Do not stop peripheral function clock in wait mode
1 : Stop peripheral function clock in wait mode (Note 8)

CIN

-X

COUT

drive capacity

select bit (Note 2)

0 : LOW
1 : HIGH

Port X

select bit

0 : I/O port
1 : X

CIN

-X

COUT

generation (Note 9)

Main clock (X

-X

OUT

)

stop bit (Note 3, 4, 5)

0 : On
1 : Off

Main clock division select
bit 0 (Note 7)

0 : CM16 and CM17 valid
1 : Division by 8 mode

System clock select bit
(Note 6)

0 : X

, X

OUT

1 : X

CIN

, X

COUT

Note 1: Set bit 0 of the protect register (address 000A

) to "1" before writing to this register.

Note 2: Changes to "1" when shiffing to stop mode and at a reset.
Note 3: When entering low power dissipation mode, main clock stops by using this bit. To stop the main clock, when the

sub clock oscillation is stable, set system clock select bit (CM07) to "1" before setting this bit to "1".

Note 4: When inputting external clock, only clock oscillation buffer is stopped and clock input is acceptable.
Note 5: If this bit is set to "1", X

OUT

turns "H". The built-in feedback resistor remains being connected, so X

turns

pulled up to X

OUT

("H") via the feedback resistor.

Note 6: Set port X

select bit (CM04) to "1" and stabilize the sub-clock oscillating before setting this bit from "0" to "1".

Do not write to both bits at the same time. And also, set the main clock stop bit (CM05) to "0" and stabilize the
main clock oscillating before setting this bit from "1" to "0".

Note 7: This bit changes to "1" when shifting from high-speed/medium-speed mode to stop mode and at a reset. When

shifting from low-speed/low power dissipation mode to stop mode, the value before stop mode is retained.

Note 8: f

C32

is not included.

Do not set to

"1"

when using low-speed or low power dissipation mode.

Note 9: When the X

CIN

COUT

is used, set ports P8

and P8

as the input ports without pull-up.

System clock control register 1 (Note 1)

Symbol

Address

When reset

CM1

0007

Bit name

Function

Bit symbol

CM10

All clock stop control bit
(Note4)

0 : Clock on
1 : All clocks off (stop mode)

Note 1: Set bit 0 of the protect register (address 000A

) to

"1" before writing to this register.

Note 2: This bit changes to "1" when shifting from high-speed/medium-speed mode to stop mode and at a reset. When

shifting from low-speed/low power dissipation mode to stop mode, the value before stop mode is retained.

Note 3: Can be selected when bit 6 of the system clock control register 0 (address 0006

) is

"0". If

"1", division mode is

fixed at 8.

Note 4: If this bit is set to "1", X

OUT

turns "H", and the built-in feedback resistor is cut off. X

CIN

and X

COUT

turn high-

impedance state.

CM15

-X

OUT

drive capacity

select bit (Note 2)

0 : LOW
1 : HIGH

CM16

CM17

Reserved bit

Always set to

"0"

Reserved bit

Always set to

"0"

Main clock division
select bit 1 (Note 3)

0 0 : No division mode
0 1 : Division by 2 mode
1 0 : Division by 4 mode
1 1 : Division by 16 mode

b7 b6

Reserved bit

Always set to

"0"

Reserved bit

Always set to

"0"

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Clock Generating Circuit

Memory expansion mode

Single-chip mode

Microprocessor mode

_______

Address bus, data bus, CS0 to CS3,

Retains status before stop mode

________

BHE

_____

______

________

_________

RD, WR, WRL, WRH

"H"

__________

HLDA, BCLK

"H"

ALE

"H"

Port

Retains status before stop mode Retains status before stop mode

CLK

OUT

When fc selected

Valid only in single-chip mode

"H"

When f

, f

selected

Valid only in single-chip mode

Retains status before stop mode

Table 1.10.2. Port status during stop mode

Clock Output

In single-chip mode, the clock output function select bits (bits 0 and 1 at address 0006

) enable f

, f

, or

fc to be output from the P5

/CLK

OUT

pin. When the WAIT peripheral function clock stop bit (bit 2 at address

0006

) is set to "1", the output of f

and f

stops when a WAIT instruction is executed.

Stop Mode

Writing "1" to the all-clock stop control bit (bit 0 at address 0007

) stops all oscillation and the microcom-

puter enters stop mode. In stop mode, the content of the internal RAM is retained provided that V

re-

mains above 2V.

Because the oscillation , BCLK, f

to f

, f

1SIO2

to f

32SIO2

, f

C32

, and f

stops in stop mode, peripheral

functions such as the A-D converter and watchdog timer do not function. However, timer A and timer B

operate provided that the event counter mode is set to an external pulse, and UARTi(i = 0 to 2), SI/O3,4

functions provided an external clock is selected. Table 1.10.2 shows the status of the ports in stop mode.

Stop mode is cancelled by a hardware reset or an interrupt. If an interrupt is to be used to cancel stop mode,

that interrupt must first have been enabled, and the priority level of the interrupt which is not used to cancel

must have been changed to 0. If returning by an interrupt, that interrupt routine is executed. If only a

_______

hardware reset or an NMI interrupt is used to cancel stop mode, change the priority level of all interrupt to

0, then shift to stop mode.

When shifting from high-speed/medium-speed mode to stop mode and at a reset, the main clock division

select bit 0 (bit 6 at address 0006

) is set to "1". When shifting from low-speed/low power dissipation mode

to stop mode, the value before stop mode is retained.

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Wait Mode

Table 1.10.3. Port status during wait mode

Memory expansion mode

Single-chip mode

Microprocessor mode

_______

Address bus, data bus, CS0 to CS3,

Retains status before wait mode

________

BHE

_____

______

________

_________

RD, WR, WRL, WRH

"H"

__________

HLDA,BCLK

"H"

ALE

"H"

Port

Retains status before wait mode

CLK

OUT

When f

selected

Valid only in single-chip mode

Does not stop

When f

, f

selected Valid only in single-chip mode

Does not stop when the WAIT

peripheral function clock stop

bit is "0".

When the WAIT peripheral

function clock stop bit is "1",

the status immediately prior

to entering wait mode is main-

tained.

Wait Mode

When a WAIT instruction is executed, the BCLK stops and the microcomputer enters the wait mode. In this

mode, oscillation continues but the BCLK and watchdog timer stop. Writing "1" to the WAIT peripheral

function clock stop bit and executing a WAIT instruction stops the clock being supplied to the internal

peripheral functions, allowing power dissipation to be reduced. However, peripheral function clock f

C32

does not stop so that the peripherals using f

C32

do not contribute to the power saving. When the MCU

running in low-speed or low power dissipation mode, do not enter WAIT mode with this bit set to "1". Table

1.10.3 shows the status of the ports in wait mode.

Wait mode is cancelled by a hardware reset or an interrupt. If an interrupt is used to cancel wait mode, that

interrupt must first have been enabled, and the priority level of the interrupt which is not used to cancel must

have been changed to 0. If returning by an interrupt, the clock in which the WAIT instruction executed is set

to BCLK by the microcomputer, and the action is resumed from the interrupt routine. If only a hardware

_______

reset or an NMI interrupt is used to cancel wait mode, change the priority level of all interrupt to 0,then shift

to wait mode.

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Status Transition of BCLK

Invalid

Division by 2 mode

Invalid

Division by 4 mode

Invalid

Division by 8 mode

Invalid

Division by 16 mode

Invalid

No-division mode

Invalid

Low-speed mode

Invalid

Low power dissipation mode

Status Transition of BCLK

Power dissipation can be reduced and low-voltage operation achieved by changing the count source for

BCLK. Table 1.10.4 shows the operating modes corresponding to the settings of system clock control

registers 0 and 1.

When reset, the device starts in division by 8 mode. The main clock division select bit 0(bit 6 at address

0006

) changes to "1" when shifting from high-speed/medium-speed to stop mode and at a reset. When

shifting from low-speed/low power dissipation mode to stop mode, the value before stop mode is retained.

The following shows the operational modes of BCLK.

(1) Division by 2 mode

The main clock is divided by 2 to obtain the BCLK.

(2) Division by 4 mode

The main clock is divided by 4 to obtain the BCLK.

(3) Division by 8 mode

The main clock is divided by 8 to obtain the BCLK. When reset, the device starts operating from this

mode. Before the user can go from this mode to no division mode, division by 2 mode, or division by 4

mode, the main clock must be oscillating stably. When going to low-speed or lower power consumption

mode, make sure the sub-clock is oscillating stably.

(4) Division by 16 mode

The main clock is divided by 16 to obtain the BCLK.

(5) No-division mode

The main clock is divided by 1 to obtain the BCLK.

(6) Low-speed mode

is used as the BCLK. Note that oscillation of both the main and sub-clocks must have stabilized before

transferring from this mode to another or vice versa. At least 2 to 3 seconds are required after the sub-

clock starts. Therefore, the program must be written to wait until this clock has stabilized immediately

after powering up and after stop mode is cancelled.

(7) Low power dissipation mode

is the BCLK and the main clock is stopped.

Note : Before the count source for BCLK can be changed from X

to X

CIN

or vice versa, the clock to which

the count source is going to be switched must be oscillating stably. Allow a wait time in software for

the oscillation to stabilize before switching over the clock.

CM17

CM16

CM07

CM06

CM05

CM04

Operating mode of BCLK

Table 1.10.4. Operating modes dictated by settings of system clock control registers 0 and 1

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Power control

Power control

The following is a description of the three available power control modes:

Modes

Power control is available in three modes.

(a) Normal operation mode

· High-speed mode

Divide-by-1 frequency of the main clock becomes the BCLK. The CPU operates with the BCLK.

Each peripheral function operates according to its assigned clock.

· Medium-speed mode

Divide-by-2, divide-by-4, divide-by-8, or divide-by-16 frequency of the main clock becomes the

BCLK. The CPU operates with the BCLK. Each peripheral function operates according to its as-

signed clock.

· Low-speed mode

becomes the BCLK. The CPU operates according to the f

clock. The f

clock is supplied by the

subclock. Each peripheral function operates according to its assigned clock.

· Low power dissipation mode

The main clock operating in low-speed mode is stopped. The CPU operates according to the f

clock. The f

clock is supplied by the subclock. The only peripheral functions that operate are those

with the subclock selected as the count source.

(b) Wait mode

The CPU operation is stopped. The oscillators do not stop.

(c) Stop mode

All oscillators stop. The CPU and all built-in peripheral functions stop. This mode, among the three

modes listed here, is the most effective in decreasing power consumption.

Figure 1.10.5 is the state transition diagram of the above modes.

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Power control

Figure 1.10.5. State transition diagram of Power control mode

Transition of stop mode, wait mode

Transition of normal mode

Reset

Medium-speed mode

(divided-by-8 mode)

Interrupt

CM10 = "1"

All oscillators stopped

CPU operation stopped

Medium-speed mode

(divided-by-8 mode)

BCLK : f(X

)/8

CM07 = "0" CM06 = "1"

Low-speed mode

High-speed mode

Main clock is oscillating

Sub clock is stopped

Main clock is oscillating

Sub clock is stopped

Main clock is stopped

Sub clock is oscillating

Main clock is oscillating

Sub clock is oscillating

Low power dissipation mode

High-speed/medium-

speed mode

Low-speed/low power

dissipation mode

Normal mode

Stop mode

All oscillators stopped

Wait mode

CPU operation stopped

Interrupt

WAIT
instruction

Interrupt

WAIT
instruction

Interrupt

WAIT
instruction

CM10 = "1"

Interrupt

CM10 = "1"

BCLK : f(X

)/2

CM07 = "0" CM06 = "0"
CM17 = "0" CM16 = "1"

Medium-speed mode

(divided-by-2 mode)

BCLK : f(X

)/16

CM07 = "0" CM06 = "0"
CM17 = "1" CM16 = "1"

Medium-speed mode
(divided-by-16 mode)

BCLK : f(X

)/4

CM07 = "0" CM06 = "0"
CM17 = "1" CM16 = "0"

Medium-speed mode

(divided-by-4 mode)

BCLK : f(X

)

CM07 = "0" CM06 = "0"
CM17 = "0" CM16 = "0"

BCLK : f(X

)/8

Medium-speed mode

(divided-by-8 mode)

CM07 = "0"
CM06 = "1"

High-speed mode

BCLK : f(X

)/2

CM07 = "0" CM06 = "0"
CM17 = "0" CM16 = "1"

Medium-speed mode

(divided-by-2 mode)

BCLK : f(X

)/16

CM07 = "0" CM06 = "0"
CM17 = "1" CM16 = "1"

Medium-speed mode
(divided-by-16 mode)

BCLK : f(X

)/4

CM07 = "0" CM06 = "0"
CM17 = "1" CM16 = "0"

Medium-speed mode

(divided-by-4 mode)

BCLK : f(X

)

CM07 = "0" CM06 = "0"
CM17 = "0" CM16 = "0"

BCLK : f(X

CIN

)

CM07 = "1"

BCLK : f(X

CIN

)

CM07 = "1"

Main clock is oscillating

Sub clock is oscillating

CM07 = "0"
(Note 1, 3)

CM07 = "0" (Note 1)
CM06 = "1"
CM04 = "0"

CM07 = "1"
(Note 2)

CM07 = "0" (Note 1)
CM06 = "0" (Note 3)
CM04 = "1"

CM07 = "1" (Note 2)
CM05 = "1"

CM05 = "0"

CM05 = "1"

CM04 = "0"

CM04 = "1"

CM06 = "0"
(Notes 1,3)

CM06 = "1"

CM04 = "0"

CM04 = "1"
(Notes 1, 3)

Note 1: Switch clock after oscillation of main clock is sufficiently stable.
Note 2: Switch clock after oscillation of sub clock is sufficiently stable.
Note 3: Change CM06 after changing CM17 and CM16.
Note 4: Transit in accordance with arrow.

(Refer to the following for the transition of normal mode.)

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Protection

Protection

The protection function is provided so that the values in important registers cannot be changed in the event

that the program runs out of control. Figure 1.10.6 shows the protect register. The values in the processor

mode register 0 (address 0004

), processor mode register 1 (address 0005

), system clock control reg-

ister 0 (address 0006

), system clock control register 1 (address 0007

), port P9 direction register (ad-

dress 03F3

) , SI/O3 control register (address 0362

) and SI/O4 control register (address 0366

) can

only be changed when the respective bit in the protect register is set to "1". Therefore, important outputs

can be allocated to port P9.

If, after "1" (write-enabled) has been written to the port P9 direction register and SI/Oi control register

(i=3,4) write-enable bit (bit 2 at address 000A

), a value is written to any address, the bit automatically

reverts to "0" (write-inhibited). However, the system clock control registers 0 and 1 write-enable bit (bit 0 at

000A

) and processor mode register 0 and 1 write-enable bit (bit 1 at 000A

) do not automatically return

to "0" after a value has been written to an address. The program must therefore be written to return these

bits to "0".

Protect register

Symbol

Address

When reset

PRCR

000A

XXXXX000

Bit name

Bit symbol

0 : Write-inhibited
1 : Write-enabled

PRC1

PRC0

PRC2

Enables writing to processor mode
registers 0 and 1 (addresses 0004

and 0005

)

Function

0 : Write-inhibited
1 : Write-enabled

Enables writing to system clock
control registers 0 and 1 (addresses
0006

and 0007

)

Enables writing to port P9 direction
register (address 03F3

) and SI/Oi

control register (i=3,4) (addresses
0362

and 0366

) (Note

)

0 : Write-inhibited
1 : Write-enabled

Nothing is assigned.
In an attempt to write to these bits, write "0". The value, if read, turns out to be
indeterminate.

Note: Writing a value to an address after "1" is written to this bit returns the bit

to "0" . Other bits do not automatically return to "0" and they must therefore
be reset by the program.

Figure 1.10.6. Protect register

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Interrupt

Software Interrupts

A software interrupt occurs when executing certain instructions. Software interrupts are non-maskable

interrupts.

· Undefined instruction interrupt

An undefined instruction interrupt occurs when executing the UND instruction.

· Overflow interrupt

An overflow interrupt occurs when executing the INTO instruction with the overflow flag (O flag) set to

"1". The following are instructions whose O flag changes by arithmetic:

ABS, ADC, ADCF, ADD, CMP, DIV, DIVU, DIVX, NEG, RMPA, SBB, SHA, SUB

· BRK interrupt

A BRK interrupt occurs when executing the BRK instruction.

· INT interrupt

An INT interrupt occurs when specifying one of software interrupt numbers 0 through 63 and execut-

ing the INT instruction. Software interrupt numbers 0 through 31 are assigned to peripheral I/O inter-

rupts, so executing the INT instruction allows executing the same interrupt routine that a peripheral I/

O interrupt does.

The stack pointer (SP) used for the INT interrupt is dependent on which software interrupt number is

involved.

So far as software interrupt numbers 0 through 31 are concerned, the microcomputer saves the stack

pointer assignment flag (U flag) when it accepts an interrupt request. If change the U flag to "0" and

select the interrupt stack pointer (ISP), and then execute an interrupt sequence. When returning from

the interrupt routine, the U flag is returned to the state it was before the acceptance of interrupt re-

quest. So far as software numbers 32 through 63 are concerned, the stack pointer does not make a

shift.

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Interrupt

Hardware Interrupts

Hardware interrupts are classified into two types -- special interrupts and peripheral I/O interrupts.

(1) Special interrupts

Special interrupts are non-maskable interrupts.

· Reset

____________

Reset occurs if an "L" is input to the RESET pin.

_______

· NMI interrupt

_______

An NMI interrupt occurs if an "L" is input to the NMI pin.

________

· DBC interrupt

This interrupt is exclusively for the debugger, do not use it in other circumstances.

· Watchdog timer interrupt

Generated by the watchdog timer.

· Single-step interrupt

This interrupt is exclusively for the debugger, do not use it in other circumstances. With the debug

flag (D flag) set to "1", a single-step interrupt occurs after one instruction is executed.

· Address match interrupt

An address match interrupt occurs immediately before the instruction held in the address indicated by

the address match interrupt register is executed with the address match interrupt enable bit set to "1".

If an address other than the first address of the instruction in the address match interrupt register is set,

no address match interrupt occurs.

(2) Peripheral I/O interrupts

A peripheral I/O interrupt is generated by one of built-in peripheral functions. Built-in peripheral func-

tions are dependent on classes of products, so the interrupt factors too are dependent on classes of

products. The interrupt vector table is the same as the one for software interrupt numbers 0 through

31 the INT instruction uses. Peripheral I/O interrupts are maskable interrupts.

· Bus collision detection interrupt

This is an interrupt that the serial I/O bus collision detection generates.

· DMA0 interrupt, DMA1 interrupt

These are interrupts that DMA generates.

· Key-input interrupt

___

A key-input interrupt occurs if an "L" is input to the KI pin.

· A-D conversion interrupt

This is an interrupt that the A-D converter generates.

· UART0, UART1, UART2/NACK, SI/O3 and SI/O4 transmission interrupt

These are interrupts that the serial I/O transmission generates.

· UART0, UART1, UART2/ACK, SI/O3 and SI/O4 reception interrupt

These are interrupts that the serial I/O reception generates.

· Timer A0 interrupt through timer A4 interrupt

These are interrupts that timer A generates

· Timer B0 interrupt through timer B5 interrupt

These are interrupts that timer B generates.

________

· INT0 interrupt through INT5 interrupt

______

An INT interrupt occurs if either a rising edge or a falling edge or a both edge is input to the INT pin.

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Interrupt

Interrupt source

Vector table addresses

Remarks

Address (L) to address (H)

Undefined instruction

FFFDC

to FFFDF

Interrupt on UND instruction

Overflow

FFFE0

to FFFE3

Interrupt on INTO instruction

BRK instruction

FFFE4

to FFFE7

If the vector contains FF

, program execution starts from

the address shown by the vector in the variable vector table

Address match

FFFE8

to FFFEB

There is an address-matching interrupt enable bit

Single step (Note)

FFFEC

to FFFEF

Do not use

Watchdog timer

FFFF0

to FFFF3

________

DBC (Note)

FFFF4

to FFFF7

Do not use

_______

NMI

FFFF8

to FFFFB

_______

External interrupt by input to NMI pin

Reset

FFFFC

to FFFFF

Note: Interrupts used for debugging purposes only.

Figure 1.11.2. Format for specifying interrupt vector addresses

Mid address

Low address

0 0 0 0

High address

0 0 0 0

Vector address + 0

Vector address + 1

Vector address + 2

Vector address + 3

LSB

MSB

Interrupts and Interrupt Vector Tables

If an interrupt request is accepted, a program branches to the interrupt routine set in the interrupt vector

table. Set the first address of the interrupt routine in each vector table. Figure 1.11.2 shows the format for

specifying the address.

Two types of interrupt vector tables are available -- fixed vector table in which addresses are fixed and

variable vector table in which addresses can be varied by the setting.

· Fixed vector tables

The fixed vector table is a table in which addresses are fixed. The vector tables are located in an area

extending from FFFDC

to FFFFF

. One vector table comprises four bytes. Set the first address of

interrupt routine in each vector table. Table 1.11.1 shows the interrupts assigned to the fixed vector

tables and addresses of vector tables.

Table 1.11.1. Interrupts assigned to the fixed vector tables and addresses of vector tables

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Interrupt

Table 1.11.2. Interrupts assigned to the variable vector tables and addresses of vector tables

Software interrupt number

Interrupt source

Vector table address

Address (L) to address (H)

Remarks

Cannot be masked I flag

+0 to +3 (Note 1)

BRK instruction

Software interrupt number 0

+44 to +47 (Note 1)

Software interrupt number 11

+48 to +51 (Note 1)

Software interrupt number 12

+52 to +55 (Note 1)

Software interrupt number 13

+56 to +59 (Note 1)

Software interrupt number 14

+68 to +71 (Note 1)

Software interrupt number 17

+72 to +75 (Note 1)

Software interrupt number 18

+76 to +79 (Note 1)

Software interrupt number 19

+80 to +83 (Note 1)

Software interrupt number 20

+84 to +87 (Note 1)

Software interrupt number 21

+88 to +91 (Note 1)

Software interrupt number 22

+92 to +95 (Note 1)

Software interrupt number 23

+96 to +99 (Note 1)

Software interrupt number 24

+100 to +103 (Note 1)

Software interrupt number 25

+104 to +107 (Note 1)

Software interrupt number 26

+108 to +111 (Note 1)

Software interrupt number 27

+112 to +115 (Note 1)

Software interrupt number 28

+116 to +119 (Note 1)

Software interrupt number 29

+120 to +123 (Note 1)

Software interrupt number 30

+124 to +127 (Note 1)

Software interrupt number 31

+128 to +131 (Note 1)

Software interrupt number 32

+252 to +255 (Note 1)

Software interrupt number 63

Note 1: Address relative to address in interrupt table register (INTB).
Note 2: It is selected by interrupt request cause bit (bit 6, 7 in address 035F

Note 3: When IIC mode is selected, NACK and ACK interrupts are selected.

Cannot be masked I flag

+40 to +43 (Note 1)

Software interrupt number 10

+60 to +63 (Note 1)

Software interrupt number 15

+64 to +67 (Note 1)

Software interrupt number 16

+20 to +23 (Note 1)

Software interrupt number 5

+24 to +27 (Note 1)

Software interrupt number 6

+28 to +31 (Note 1)

Software interrupt number 7

+32 to +35 (Note 1)

Software interrupt number 8

+16 to +19 (Note 1)

INT3

Software interrupt number 4

+36 to +39 (Note 1)

SI/O3/INT4

Software interrupt number 9

SI/O4/INT5

Timer B3

Timer B4

Timer B5

(Note 2)

DMA0

DMA1

Key input interrupt

A-D

UART0 transmit

UART0 receive

UART1 transmit

UART1 receive

Timer A0

Timer A1

Timer A2

Timer A3

Timer A4

Timer B0

Timer B1

Timer B2

INT0

INT1

INT2

Software interrupt

Bus collision detection

UART2 transmit/NACK (Note 3)

UART2 receive/ACK (Note 3)

· Variable vector tables

The addresses in the variable vector table can be modified, according to the user's settings. Indicate

the first address using the interrupt table register (INTB). The 256-byte area subsequent to the ad-

dress the INTB indicates becomes the area for the variable vector tables. One vector table comprises

four bytes. Set the first address of the interrupt routine in each vector table. Table 1.11.2 shows the

interrupts assigned to the variable vector tables and addresses of vector tables.

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Interrupt

Figure 1.11.3. Interrupt control registers

Symbol

Address

When reset

INTiIC(i=3)

0044

XX00X000

SiIC/INTjIC (i=4, 3)

0048

, 0049

XX00X000

(j=5, 4)

0048

, 0049

XX00X000

INTiIC(i=0 to 2)

005D

to 005F

XX00X000

Bit name

Function

Bit symbol

ILVL0

POL

Nothing is assigned.

In an attempt to write to these bits, write "0". The value, if read, turns
out to be indeterminate.

Interrupt priority level
select bit

Interrupt request bit

Polarity select bit

Reserved bit

0: Interrupt not requested
1: Interrupt requested

0 : Selects falling edge
1 : Selects rising edge

Always set to "0"

ILVL1

ILVL2

Note 1: This bit can only be accessed for reset (= 0), but cannot be accessed for set (= 1).
Note 2: To rewrite the interrupt control register, do so at a point that does not generate the

interrupt request for that register. For details, see the precautions for interrupts.

(Note 1)

Interrupt control register (Note2)

Bit name

Function

Bit symbol

Symbol

Address

When reset

TBiIC(i=3 to 5)

0045

to 0047

XXXXX000

BCNIC

004A

XXXXX000

DMiIC(i=0, 1)

004B

, 004C

XXXXX000

KUPIC

004D

XXXXX000

ADIC

004E

XXXXX000

SiTIC(i=0 to 2)

0051

, 0053

, 004F

XXXXX000

SiRIC(i=0 to 2)

0052

, 0054

, 0050

XXXXX000

TAiIC(i=0 to 4)

0055

to 0059

XXXXX000

TBiIC(i=0 to 2)

005A

to 005C

XXXXX000

ILVL0

Interrupt priority level
select bit

Interrupt request bit

0 : Interrupt not requested
1 : Interrupt requested

ILVL1

ILVL2

Nothing is assigned.

In an attempt to write to these bits, write "0". The value, if read, turns
out to be indeterminate.

(Note 1)

Note 1: This bit can only be accessed for reset (= 0), but cannot be accessed for set (= 1).
Note 2: To rewrite the interrupt control register, do so at a point that does not generate the

interrupt request for that register. For details, see the precautions for interrupts.

0 0 0 : Level 0 (interrupt disabled)
0 0 1 : Level 1
0 1 0 : Level 2
0 1 1 : Level 3
1 0 0 : Level 4
1 0 1 : Level 5
1 1 0 : Level 6
1 1 1 : Level 7

b2 b1 b0

0 0 0 : Level 0 (interrupt disabled)
0 0 1 : Level 1
0 1 0 : Level 2
0 1 1 : Level 3
1 0 0 : Level 4
1 0 1 : Level 5
1 1 0 : Level 6
1 1 1 : Level 7

b2 b1 b0

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Interrupt

Interrupt Enable Flag (I flag)

The interrupt enable flag (I flag) controls the enabling and disabling of maskable interrupts. Setting this

flag to "1" enables all maskable interrupts; setting it to "0" disables all maskable interrupts. This flag is set

to "0" after reset.

Interrupt Request Bit

The interrupt request bit is set to "1" by hardware when an interrupt is requested. After the interrupt is

accepted and jumps to the corresponding interrupt vector, the request bit is set to "0" by hardware. The

interrupt request bit can also be set to "0" by software. (Do not set this bit to "1").

Table 1.11.4. Interrupt levels enabled according

to the contents of the IPL

Table 1.11.3. Settings of interrupt priority

levels

Interrupt priority

level select bit

Interrupt priority

level

Priority

order

0 0 0

0 0 1

0 1 0

0 1 1

1 0 0

1 0 1

1 1 0

1 1 1

Level 0 (interrupt disabled)

Level 1

Level 2

Level 3

Level 4

Level 5

Level 6

Level 7

Low

High

b2 b1 b0

Enabled interrupt priority levels

0 0 0

0 0 1

0 1 0

0 1 1

1 0 0

1 0 1

1 1 0

1 1 1

Interrupt levels 1 and above are enabled

Interrupt levels 2 and above are enabled

Interrupt levels 3 and above are enabled

Interrupt levels 4 and above are enabled

Interrupt levels 5 and above are enabled

Interrupt levels 6 and above are enabled

Interrupt levels 7 and above are enabled

All maskable interrupts are disabled

IPL

Interrupt Priority Level Select Bit and Processor Interrupt Priority Level (IPL)

Set the interrupt priority level using the interrupt priority level select bit, which is one of the component bits

of the interrupt control register. When an interrupt request occurs, the interrupt priority level is compared

with the IPL. The interrupt is enabled only when the priority level of the interrupt is higher than the IPL.

Therefore, setting the interrupt priority level to "0" disables the interrupt.

Table 1.11.3 shows the settings of interrupt priority levels and Table 1.11.4 shows the interrupt levels

enabled, according to the contents of the IPL.

The following are conditions under which an interrupt is accepted:

· interrupt enable flag (I flag) = "1"

· interrupt request bit = "1"

· interrupt priority level > IPL

The interrupt enable flag (I flag), the interrupt request bit, the interrupt priority select bit, and the IPL are

independent, and they are not affected by one another.

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Interrupt

Example 1:

INT_SWITCH1:

FCLR

; Disable interrupts.

AND.B

#00h, 0055h

; Clear TA0IC int. priority level and int. request bit.

NOP

; Four NOP instructions are required when using HOLD function.

NOP
FSET

; Enable interrupts.

Example 2:

INT_SWITCH2:

FCLR

; Disable interrupts.

AND.B

#00h, 0055h

; Clear TA0IC int. priority level and int. request bit.

MOV.W MEM, R0

; Dummy read.

FSET

; Enable interrupts.

Example 3:

INT_SWITCH3:

PUSHC FLG

; Push Flag register onto stack

FCLR

; Disable interrupts.

AND.B

#00h, 0055h

; Clear TA0IC int. priority level and int. request bit.

POPC

FLG

; Enable interrupts.

The reason why two NOP instructions (four when using the HOLD function) or dummy read are inserted
before FSET I in Examples 1 and 2 is to prevent the interrupt enable flag I from being set before the
interrupt control register is rewritten due to effects of the instruction queue.

Rewrite the interrupt control register

To rewrite the interrupt control register, do so at a point that does not generate the interrupt request for

that register. If there is possibility of the interrupt request occur, rewrite the interrupt control register after

the interrupt is disabled. The program examples are described as follow:

When a instruction to rewrite the interrupt control register is executed but the interrupt is disabled, the

interrupt request bit is not set sometimes even if the interrupt request for that register has been gener-

ated. This will depend on the instruction. If this creates problems, use the below instructions to change

the register.

Instructions : AND, OR, BCLR, BSET

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Interrupt

Interrupt Sequence

An interrupt sequence -- what are performed over a period from the instant an interrupt is accepted to the

instant the interrupt routine is executed -- is described here.

If an interrupt occurs during execution of an instruction, the processor determines its priority when the

execution of the instruction is completed, and transfers control to the interrupt sequence from the next

cycle. If an interrupt occurs during execution of either the SMOVB, SMOVF, SSTR or RMPA instruction,

the processor temporarily suspends the instruction being executed, and transfers control to the interrupt

sequence.

In the interrupt sequence, the processor carries out the following in sequence given:

(1) CPU gets the interrupt information (the interrupt number and interrupt request level) by reading ad-

dress 00000

. After this, the corresponding interrupt request bit becomes "0".

(2) Saves the content of the flag register (FLG) as it was immediately before the start of interrupt sequence

in the temporary register (Note) within the CPU.

(3) Sets the interrupt enable flag (I flag), the debug flag (D flag), and the stack pointer select flag (U flag) to

"0" (the U flag, however does not change if the INT instruction, in software interrupt numbers 32

through 63, is executed)

(4) Saves the content of the temporary register (Note) within the CPU in the stack area.

(5) Saves the content of the program counter (PC) in the stack area.

(6) Sets the interrupt priority level of the accepted instruction in the IPL.

After the interrupt sequence is completed, the processor resumes executing instructions from the first

address of the interrupt routine.

Note: This register cannot be utilized by the user.

Interrupt Response Time

'Interrupt response time' is the period between the instant an interrupt occurs and the instant the first

instruction within the interrupt routine has been executed. This time comprises the period from the

occurrence of an interrupt to the completion of the instruction under execution at that moment (a) and the

time required for executing the interrupt sequence (b). Figure 1.11.4 shows the interrupt response time.

Instruction

Interrupt sequence

Instruction in

interrupt routine

Time

Interrupt response time

(a)

(b)

Interrupt request acknowledged

Interrupt request generated

(a) Time from interrupt request is generated to when the instruction then under execution is completed.
(b) Time in which the instruction sequence is executed.

Figure 1.11.4. Interrupt response time

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Interrupt

Interrupt sources without priority levels

Value set in the IPL

_______

Watchdog timer, NMI

Other

Not changed

Variation of IPL when Interrupt Request is Accepted

If an interrupt request is accepted, the interrupt priority level of the accepted interrupt is set in the IPL.

If an interrupt request, that does not have an interrupt priority level, is accepted, one of the values shown

in Table 1.11.6 is set in the IPL.

Table 1.11.6. Relationship between interrupts without interrupt priority levels and IPL

Stack pointer (SP) value

Interrupt vector address

16-Bit bus, without wait

8-Bit bus, without wait

Even

Odd (Note 2)

Even

Odd

Even

Odd

18 cycles (Note 1)

19 cycles (Note 1)

20 cycles (Note 1)

Table 1.11.5. Time required for executing the interrupt sequence

Reset

Indeterminate

The indeterminate segment is dependent on the queue buffer.
If the queue buffer is ready to take an instruction, a read cycle occurs.

Indeterminate

SP-2

contents

SP-4

contents

vec

contents

vec+2

contents

Interrupt

information

Address

0000

Indeterminate

SP-2

SP-4

vec

vec+2

BCLK

Address bus

Data bus

Time (a) is dependent on the instruction under execution. Thirty cycles is the maximum required for the

DIVX instruction (without wait).

Time (b) is as shown in Table 1.11.5.

________

Note 1: Add 2 cycles in the case of a DBC interrupt; add 1 cycle in the case either of an address match

interrupt or of a single-step interrupt.

Note 2: Locate an interrupt vector address in an even address, if possible.

Figure 1.11.5. Time required for executing the interrupt sequence

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Interrupt

Saving Registers

In the interrupt sequence, only the contents of the flag register (FLG) and that of the program counter

(PC) are saved in the stack area.

First, the processor saves the four higher-order bits of the program counter, and 4 upper-order bits and 8

lower-order bits of the FLG register, 16 bits in total, in the stack area, then saves 16 lower-order bits of the

program counter. Figure 1.11.6 shows the state of the stack as it was before the acceptance of the

interrupt request, and the state the stack after the acceptance of the interrupt request.

Save other necessary registers at the beginning of the interrupt routine using software. Using the

PUSHM instruction alone can save all the registers except the stack pointer (SP).

Address

Content of previous stack

Stack area

[SP]
Stack pointer
value before
interrupt occurs

m 1

m 2

m 3

m 4

Stack status before interrupt request
is acknowledged

Stack status after interrupt request
is acknowledged

Content of previous stack

m + 1

MSB

LSB

m 1

m 2

m 3

m 4

Address

Flag register (FLG

)

Content of previous stack

Stack area

Flag register

(FLG

)

Program

counter (PC

)

[SP]
New stack
pointer value

Content of previous stack

m + 1

MSB

LSB

Program counter (PC

)

Program counter (PC

)

Figure 1.11.6. State of stack before and after acceptance of interrupt request

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Interrupt

Figure 1.11.7. Operation of saving registers

(2) Stack pointer (SP) contains odd number

[SP]

(Odd)

[SP] 1 (Even)

[SP] 2(Odd)

[SP] 3 (Even)

[SP] 4(Odd)

[SP] 5 (Even)

Address

Sequence in which order
registers are saved

(2)

(1)

Finished saving registers
in four operations.

(3)

(4)

(1) Stack pointer (SP) contains even number

[SP]

(Even)

[SP] 1(Odd)

[SP] 2 (Even)

[SP] 3(Odd)

[SP] 4 (Even)

[SP] 5 (Odd)

Note: [SP] denotes the initial value of the stack pointer (SP) when interrupt request is acknowledged.

After registers are saved, the SP content is [SP] minus 4.

Address

Program counter (PC

)

Stack area

Flag register (FLG

)

Program counter (PC

)

Sequence in which order
registers are saved

(2) Saved simultaneously,

all 16 bits

(1) Saved simultaneously,

all 16 bits

Finished saving registers
in two operations.

Program counter (PC

)

Stack area

Flag register (FLG

)

Program counter (PC

)

Saved simultaneously,
all 8 bits

Flag register

(FLG

)

Program

counter (PC

)

Flag register

(FLG

)

Program

counter (PC

)

The operation of saving registers carried out in the interrupt sequence is dependent on whether the

content of the stack pointer (Note) , at the time of acceptance of an interrupt request, is even or odd. If

the content of the stack pointer (Note) is even, the content of the flag register (FLG) and the content of the

program counter (PC) are saved, 16 bits at a time. If odd, their contents are saved in two steps, 8 bits at

a time. Figure 1.11.7 shows the operation of the saving registers.

Note: When any INT instruction in software numbers 32 to 63 has been executed, this is the stack pointer

indicated by the U flag. Otherwise, it is the interrupt stack pointer (ISP).

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Interrupt

Interrupt Priority

If there are two or more interrupt requests occurring at a point in time within a single sampling (checking

whether interrupt requests are made), the interrupt assigned a higher priority is accepted.

Assign an arbitrary priority to maskable interrupts (peripheral I/O interrupts) using the interrupt priority level

select bit. If the same interrupt priority level is assigned, however, the interrupt assigned a higher hardware

priority is accepted.

Priorities of the special interrupts, such as Reset (dealt with as an interrupt assigned the highest priority),

watchdog timer interrupt, etc. are regulated by hardware.

Figure 1.11.8 shows the priorities of hardware interrupts.

Software interrupts are not affected by the interrupt priority. If an instruction is executed, control branches

invariably to the interrupt routine.

Returning from an Interrupt Routine

Executing the REIT instruction at the end of an interrupt routine returns the contents of the flag register

(FLG) as it was immediately before the start of interrupt sequence and the contents of the program counter

(PC), both of which have been saved in the stack area. Then control returns to the program that was being

executed before the acceptance of the interrupt request, so that the suspended process resumes.

Return the other registers saved by software within the interrupt routine using the POPM or similar instruc-

tion before executing the REIT instruction.

Interrupt resolution circuit

When two or more interrupts are generated simultaneously, this circuit selects the interrupt with the highest

priority level. Figure 1.11.9 shows the circuit that judges the interrupt priority level.

Figure 1.11.8. Hardware interrupts priorities

_______

________

Reset > NMI > DBC > Watchdog timer > Peripheral I/O > Single step > Address match

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______

INT Interrupt

______

INT Interrupt

________

INT0 to INT5 are triggered by the edges of external inputs. The edge polarity is selected using the polarity

select bit.

________

Of interrupt control registers, 0048

is used both as serial I/O4 and external interrupt INT5 input control

________

is used both as serial I/O3 and as external interrupt INT4 input control register. Use the

interrupt request cause select bits - bits 6 and 7 of the interrupt request cause select register (035F

) - to

specify which interrupt request cause to select. After having set an interrupt request cause, be sure to clear

the corresponding interrupt request bit before enabling an interrupt.

Either of the interrupt control registers - 0048

, 0049

- has the polarity-switching bit. Be sure to set this bit

to "0" to select an serial I/O as the interrupt request cause.

As for external interrupt input, an interrupt can be generated both at the rising edge and at the falling edge

by setting "1" in the INTi interrupt polarity switching bit of the interrupt request cause select register

(035F

). To select both edges, set the polarity switching bit of the corresponding interrupt control register

to `falling edge' ("0").

Figure 1.11.10 shows the Interrupt request cause select register.

Figure 1.11.10. Interrupt request cause select register

Interrupt request cause select register

Bit name

Function

Bit symbol

Symbol

Address

When reset

IFSR

035F

IFSR0

INT0 interrupt polarity
switching bit

0 : SIO3
1 : INT4

0 : SIO4
1 : INT5

0 : One edge
1 : Two edges

INT1 interrupt polarity
switching bit

INT2 interrupt polarity
switching bit

INT3 interrupt polarity
switching bit

INT4 interrupt polarity
switching bit

INT5 interrupt polarity
switching bit

0 : One edge
1 : Two edges

Interrupt request cause
select bit

IFSR1

IFSR2

IFSR3

IFSR4

IFSR5

IFSR6

IFSR7

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________

NMI Interrupt

Interrupt control circuit

Key input interrupt control register

(address 004D

)

Key input interrupt
request

P10

/KI

P10

/KI

P10

/KI

P10

/KI

Port P10

-P10

pull-up

select bit

Port P10

direction

Pull-up
transistor

Port P10

direction register

Port P10

direction

Port P10

direction

Port P10

direction

Pull-up
transistor

Figure 1.11.11. Block diagram of key input interrupt

______

NMI Interrupt

______

An NMI interrupt is generated when the input to the P8

/NMI pin changes from "H" to "L". The NMI interrupt

is a non-maskable external interrupt. The pin level can be checked in the port P8

03F0

This pin cannot be used as a normal port input.

Key Input Interrupt

If the direction register of any of P10

to P10

is set for input and a falling edge is input to that port, a key

input interrupt is generated. A key input interrupt can also be used as a key-on wakeup function for cancel-

ling the wait mode or stop mode. However, if you intend to use the key input interrupt, do not use P10

P10

as A-D input ports. Figure 1.11.11 shows the block diagram of the key input interrupt. Note that if an

"L" level is input to any pin that has not been disabled for input, inputs to the other pins are not detected as

an interrupt.

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Address Match Interrupt

Address Match Interrupt

An address match interrupt is generated when the address match interrupt address register contents match

the program counter value. Two address match interrupts can be set, each of which can be enabled and

disabled by an address match interrupt enable bit. Address match interrupts are not affected by the inter-

rupt enable flag (I flag) and processor interrupt priority level (IPL). For an address match interrupt, the value

of the program counter (PC) that is saved to the stack area varies depending on the instruction being

executed. Note that when using the external data bus in width of 8 bits, the address match interrupt cannot

be used for external area.

Figure 1.11.12 shows the address match interrupt-related registers.

Bit name

Bit symbol

Symbol

Address When

reset

AIER

0009

XXXXXX00

Address match interrupt enable register

Function

Address match interrupt 0

enable bit

0 : Interrupt disabled
1 : Interrupt enabled

AIER0

Address match interrupt 1

enable bit

AIER1

Symbol

Address

When reset

RMAD0

0012

to 0010

X00000

RMAD1

0016

to 0014

X00000

Nothing is assigned.
In an attempt to write to these bits, write "0". The value, if read, turns out to
be indeterminated.

Address setting register for address match interrupt

Function

Values that can be set

Address match interrupt register i (i = 0, 1)

00000

to FFFFF

Nothing is assigned.
In an attempt to write to these bits, write "0". The value, if read, turns out to
be indeterminated.

0 : Interrupt disabled
1 : Interrupt enabled

b0 b7

(b19)

(b16)

(b15)

(b8)

(b23)

Figure 1.11.12. Address match interrupt-related registers

Mitsubishi microcomputers

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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

Precautions for Interrupts

Precautions for Interrupts

(1) Reading address 00000

· When maskable interrupt is occurred, CPU reads the interrupt information (the interrupt number and

interrupt request level) in the interrupt sequence.

The interrupt request bit of the certain interrupt written in address 00000

will then be set to "0".

Even if the address 00000

is read out by software, "0" is set to the enabled highest priority interrupt

source request bit. Therefore interrupt can be canceled and unexpected interrupt can occur.

Do not read address 00000

by software.

(2) Setting the stack pointer

· The value of the stack pointer immediately after reset is initialized to 0000

. Accepting an interrupt

before setting a value in the stack pointer may become a factor of runaway. Be sure to set a value in

_______

the stack pointer before accepting an interrupt. When using the NMI interrupt, initialize the stack

pointer at the beginning of a program. Concerning the first instruction immediately after reset, generat-

_______

ing any interrupts including the NMI interrupt is prohibited.

_______

(3) The NMI interrupt

_______

·The NMI interrupt can not be disabled. Be sure to connect NMI pin to Vcc via a pull-up resistor if

unused. Be sure to work on it.

_______

· The NMI pin also serves as P8

, which is exclusively input. Reading the contents of the P8 register

allows reading the pin value. Use the reading of this pin only for establishing the pin level at the time

_______

when the NMI interrupt is input.

_______

· Do not reset the CPU with the input to the NMI pin being in the "L" state.

_______

· Do not attempt to go into stop mode with the input to the NMI pin being in the "L" state. With the input to

_______

the NMI being in the "L" state, the CM10 is fixed to "0", so attempting to go into stop mode is turned

down.

_______

· Do not attempt to go into wait mode with the input to the NMI pin being in the "L" state. With the input to

_______

the NMI pin being in the "L" state, the CPU stops but the oscillation does not stop, so no power is saved.

In this instance, the CPU is returned to the normal state by a later interrupt.

_______

· Signals input to the NMI pin require an "L" level of 1 clock or more, from the operation clock of the CPU.

(4) External interrupt

________

· Either an "L" level or an "H" level of at least 250 ns width is necessary for the signal input to pins INT

________

through INT

regardless of the CPU operation clock.

________

· When the polarity of the INT

to INT

pins is changed, the interrupt request bit is sometimes set to "1".

After changing the polarity, set the interrupt request bit to "0". Figure 1.11.13 shows the procedure for

______

changing the INT interrupt generate factor.

Mitsubishi microcomputers

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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

Precautions for Interrupts

______

Figure 1.11.13. Switching condition of INT interrupt request

Set the interrupt priority level to level 0

(Disable INT

interrupt)

Set the polarity select bit

Clear the interrupt request bit to "0"

Set the interrupt priority level to level 1 to 7

(Enable the accepting of INTi interrupt request)

Clear the interrupt enable flag to "0"

(Disable interrupt)

Set the interrupt enable flag to "1"

(Enable interrupt)

Note: Execute the setting above individually. Don't execute two or
more settings at once(by one instruction).

Example 1:

INT_SWITCH1:

FCLR

; Disable interrupts.

AND.B

#00h, 0055h

; Clear TA0IC int. priority level and int. request bit.

NOP

; Four NOP instructions are required when using HOLD function.

NOP
FSET

; Enable interrupts.

Example 2:

INT_SWITCH2:

FCLR

; Disable interrupts.

AND.B

#00h, 0055h

; Clear TA0IC int. priority level and int. request bit.

MOV.W MEM, R0

; Dummy read.

FSET

; Enable interrupts.

Example 3:

INT_SWITCH3:

PUSHC FLG

; Push Flag register onto stack

FCLR

; Disable interrupts.

AND.B

#00h, 0055h

; Clear TA0IC int. priority level and int. request bit.

POPC

FLG

; Enable interrupts.

(5) Rewrite the interrupt control register

· To rewrite the interrupt control register, do so at a point that does not generate the interrupt request for

that register. If there is possibility of the interrupt request occur, rewrite the interrupt control register after

the interrupt is disabled. The program examples are described as follow:

· When a instruction to rewrite the interrupt control register is executed but the interrupt is disabled, the

interrupt request bit is not set sometimes even if the interrupt request for that register has been gener-

ated. This will depend on the instruction. If this creates problems, use the below instructions to change

the register.

Instructions : AND, OR, BCLR, BSET

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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

Watchdog Timer

Watchdog Timer

The watchdog timer has the function of detecting when the program is out of control. Therefore, we recom-

mend using the watchdog timer to improve reliability of a system.The watchdog timer is a 15-bit counter

which down-counts the clock derived by dividing the BCLK using the prescaler. A watchdog timer interrupt

is generated when an underflow occurs in the watchdog timer. When X

is selected for the BCLK

bit 7 of

the watchdog timer control register (address 000F

) selects the prescaler division ratio (by 16 or by 128).

When X

CIN

is selected as the BCLK, the prescaler is set for division by 2 regardless of bit 7 of the watchdog

timer control register (address 000F

). Thus the watchdog timer's period can be calculated as given

below. The watchdog timer's period is, however, subject to an error due to the prescaler.

BCLK

Write to the watchdog timer
start register
(address 000E

)

RESET

Watchdog timer
interrupt request

Watchdog timer

Set to
"7FFF

1/128

1/16

"CM07 = 0"
"WDC7 = 1"

"CM07 = 0"
"WDC7 = 0"

"CM07 = 1"

HOLD

1/2

Prescaler

For example, suppose that BCLK runs at 16 MHz and that 16 has been chosen for the dividing ratio of the

prescaler, then the watchdog timer's period becomes approximately 32.8 ms.

The watchdog timer is initialized by writing to the watchdog timer start register (address 000E

) and when

a watchdog timer interrupt request is generated. The prescaler is initialized only when the microcomputer is

reset. After a reset is cancelled, the watchdog timer and prescaler are both stopped. The count is started by

writing to the watchdog timer start register (address 000E

). In stop mode, wait mode and hold state, the

watchdog timer and prescaler are stopped. Counting is resumed from the held value when the modes or

state are released.

Figure 1.12.1 shows the block diagram of the watchdog timer. Figure 1.12.2 shows the watchdog timer-

related registers.

With X

chosen for BCLK

Watchdog timer period =

prescaler dividing ratio (16 or 128) X watchdog timer count (32768)

BCLK

Figure 1.12.1. Block diagram of watchdog timer

With X

CIN

chosen for BCLK

Watchdog timer period =

prescaler dividing ratio (2) X watchdog timer count (32768)

BCLK

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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

DMAC

DMAC

This microcomputer has two DMAC (direct memory access controller) channels that allow data to be sent to

memory without using the CPU. DMAC shares the same data bus with the CPU. The DMAC is given a

higher right of using the bus than the CPU, which leads to working the cycle stealing method. On this

account, the operation from the occurrence of DMA transfer request signal to the completion of 1-word (16-

bit) or 1-byte (8-bit) data transfer can be performed at high speed. Figure 1.13.1 shows the block diagram

of the DMAC. Table 1.13.1 shows the DMAC specifications. Figures 1.13.2 to 1.13.4 show the registers

used by the DMAC.

Figure 1.13.1. Block diagram of DMAC

Data bus low-order bits

DMA latch high-order bits

DMA latch low-order bits

DMA0 source pointer SAR0(20)

DMA0 destination pointer DAR0 (20)

DMA0 forward address pointer (20) (Note)

Data bus high-order bits

Address bus

DMA1 destination pointer DAR1 (20)

DMA1 source pointer SAR1 (20)

DMA1 forward address pointer (20) (Note)

DMA0 transfer counter reload register TCR0 (16)

DMA0 transfer counter TCR0 (16)

DMA1 transfer counter reload register TCR1 (16)

DMA1 transfer counter TCR1 (16)

(addresses 0029

, 0028

)

(addresses 0039

, 0038

)

(addresses 0022

to 0020

)

(addresses 0026

to 0024

)

(addresses 0032

to 0030

)

(addresses 0036

to 0034

)

Note: Pointer is incremented by a DMA request.

Either a write signal to the software DMA request bit or an interrupt request signal is used as a DMA transfer

request signal. But the DMA transfer is affected neither by the interrupt enable flag (I flag) nor by the

interrupt priority level. The DMA transfer doesn't affect any interrupts either.

If the DMAC is active (the DMA enable bit is set to 1), data transfer starts every time a DMA transfer request

signal occurs. If the cycle of the occurrences of DMA transfer request signals is higher than the DMA

transfer cycle, there can be instances in which the number of transfer requests doesn't agree with the

number of transfers. For details, see the description of the DMA request bit.

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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

DMAC

Item

Specification

No. of channels

2 (cycle steal method)

Transfer memory space

· From any address in the 1M bytes space to a fixed address
· From a fixed address to any address in the 1M bytes space
· From a fixed address to a fixed address

(Note that DMA-related registers [0020

to 003F

] cannot be accessed)

Maximum No. of bytes transferred

128K bytes (with 16-bit transfers) or 64K bytes (with 8-bit transfers)

DMA request factors (Note)

________

Falling edge of INT0 or INT1 or both edge
Timer A0 to timer A4 interrupt requests
Timer B0 to timer B5 interrupt requests
UART0 transfer and reception interrupt requests
UART1 transfer and reception interrupt requests
UART2 transfer and reception interrupt requests
Serial I/O3, 4 interrpt requests
A-D conversion interrupt requests
Software triggers

Channel priority

DMA0 takes precedence if DMA0 and DMA1 requests are generated simultaneously

Transfer unit

8 bits or 16 bits

Transfer address direction

forward/fixed (forward direction cannot be specified for both source and
destination simultaneously)

Transfer mode

· Single transfer mode

After the transfer counter underflows, the DMA enable bit turns to

"0", and the DMAC turns inactive

· Repeat transfer mode

After the transfer counter underflows, the value of the transfer counter
reload register is reloaded to the transfer counter.

The DMAC remains active unless a "0" is written to the DMA enable bit.

DMA interrupt request generation timing When an underflow occurs in the transfer counter

Active

When the DMA enable bit is set to "1", the DMAC is active.

When the DMAC is active, data transfer starts every time a DMA
transfer request signal occurs.

Inactive

· When the DMA enable bit is set to "0", the DMAC is inactive.

· After the transfer counter underflows in single transfer mode
At the time of starting data transfer immediately after turning the DMAC active, the
value of one of source pointer and destination pointer - the one specified for the
forward direction - is reloaded to the forward direction address pointer, and the value
of the transfer counter reload register is reloaded to the transfer counter.

Writing to register

Registers specified for forward direction transfer are always write enabled.
Registers specified for fixed address transfer are write-enabled when
the DMA enable bit is "0".

Reading the register

Can be read at any time.
However, when the DMA enable bit is "1", reading the register set up as the

forward register is the same as reading the value of the forward address pointer.

Table 1.13.1. DMAC specifications

Note: DMA transfer is not effective to any interrupt. DMA transfer is affected neither by the interrupt enable

flag (I flag) nor by the interrupt priority level.

Reload timing for forward ad-

dress pointer and transfer

counter

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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

DMAC

DMA0 request cause select register

Symbol

Address

When reset

DM0SL

03B8

Function

Bit symbol

DMA request cause

select bit

DSEL0

DSEL1

DSEL2

DSEL3

Nothing is assigned.
In an attempt to write to these bits, write "0". The value, if read, turns out to be "0".

Software DMA
request bit

If software trigger is selected, a
DMA request is generated by
setting this bit to "1" (When read,
the value of this bit is always "0")

DSR

b3 b2 b1 b0

0 0 0 0 : Falling edge of INT0 pin
0 0 0 1 : Software trigger
0 0 1 0 : Timer A0
0 0 1 1 : Timer A1
0 1 0 0 : Timer A2
0 1 0 1 : Timer A3
0 1 1 0 : Timer A4 (DMS=0)

/two edges of INT0 pin (DMS=1)

0 1 1 1 : Timer B0 (DMS=0)

Timer B3 (DMS=1)

1 0 0 0 : Timer B1 (DMS=0)

Timer B4 (DMS=1)

1 0 0 1 : Timer B2 (DMS=0)

Timer B5 (DMS=1)

1 0 1 0 : UART0 transmit
1 0 1 1 : UART0 receive
1 1 0 0 : UART2 transmit
1 1 0 1 : UART2 receive
1 1 1 0 : A-D conversion
1 1 1 1 : UART1 transmit

Bit name

DMA request cause
expansion select bit

DMS

0 : Normal
1 : Expanded cause

Figure 1.13.2. DMAC register (1)

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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

DMAC

DMAi control register

Symbol

Address

When reset

DMiCON(i=0,1)

002C

, 003C

00000X00

Bit name

Function

Bit symbol

Transfer unit bit select bit

0 : 16 bits
1 : 8 bits

DMBIT

DMASL

DMAS

DMAE

Repeat transfer mode

select bit

0 : Single transfer
1 : Repeat transfer

DMA request bit (Note 1)

0 : DMA not requested
1 : DMA requested

0 : Disabled
1 : Enabled

0 : Fixed
1 : Forward

DMA enable bit

Source address direction
select bit (Note 3)

Destination address
direction select bit (Note 3)

0 : Fixed
1 : Forward

DSD

DAD

Nothing is assigned.
In an attempt to write to these bits, write "0". The value, if read, turns out to be "0".

Note 1: DMA request can be cleared by resetting the bit.
Note 2: This bit can only be set to "0".
Note 3: Source address direction select bit and destination address direction select bit

cannot be set to "1" simultaneously.

(Note 2)

DMA1 request cause select register

Symbol

Address

When reset

DM1SL

03BA

Function

Bit symbol

DMA request cause

select bit

DSEL0

DSEL1

DSEL2

DSEL3

Nothing is assigned.
In an attempt to write to these bits, write "0". The value, if read, turns out to be "0".

Software DMA
request bit

If software trigger is selected, a
DMA request is generated by
setting this bit to "1" (When read,
the value of this bit is always "0")

DSR

b3 b2 b1 b0

0 0 0 0 : Falling edge of INT1 pin
0 0 0 1 : Software trigger
0 0 1 0 : Timer A0
0 0 1 1 : Timer A1
0 1 0 0 : Timer A2
0 1 0 1 : Timer A3(DMS=0)

/serial I/O3 (DMS=1)

0 1 1 0 : Timer A4 (DMS=0)

/serial I/O4 (DMS=1)

0 1 1 1 : Timer B0 (DMS=0)

/two edges of INT1 (DMS=1)

1 0 0 0 : Timer B1
1 0 0 1 : Timer B2
1 0 1 0 : UART0 transmit
1 0 1 1 : UART0 receive
1 1 0 0 : UART2 transmit
1 1 0 1 : UART2 receive
1 1 1 0 : A-D conversion
1 1 1 1 : UART1 receive

Bit name

DMA request cause
expansion select bit

DMS

0 : Normal
1 : Expanded cause

Figure 1.13.3. DMAC register (2)

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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

DMAC

(b8)

(b15)

Function

R W

· Transfer counter
Set a value one less than the transfer count

Symbol

Address

When reset

TCR0

0029

, 0028

Indeterminate

TCR1

0039

, 0038

Indeterminate

DMAi transfer counter (i = 0, 1)

Transfer count

specification

0000

to FFFF

(b23)

(b8)

(b16)(b15)

(b19)

Function

R W

· Source pointer
Stores the source address

Symbol

Address

When reset

SAR0

0022

to 0020

Indeterminate

SAR1

0032

to 0030

Indeterminate

DMAi source pointer (i = 0, 1)

Transfer address

specification

00000

to FFFFF

Nothing is assigned.
In an attempt to write to these bits, write "0". The value, if read, turns out to be "0".

Symbol

Address

When reset

DAR0

0026

to 0024

Indeterminate

DAR1

0036

to 0034

Indeterminate

(b8)

(b15)

(b16)

(b19)

Function

R W

· Destination pointer
Stores the destination address

DMAi destination pointer (i = 0, 1)

Transfer address

specification

00000

to FFFFF

(b23)

Nothing is assigned.
In an attempt to write to these bits, write "0". The value, if read, turns out to be "0".

Figure 1.13.4. DMAC register (3)

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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

DMAC

(1) Transfer cycle

The transfer cycle consists of the bus cycle in which data is read from memory or from the SFR area

(source read) and the bus cycle in which the data is written to memory or to the SFR area (destination

write). The number of read and write bus cycles depends on the source and destination addresses. In

memory expansion mode and microprocessor mode, the number of read and write bus cycles also de-

pends on the level of the BYTE pin. Also, the bus cycle itself is longer when software waits are inserted.

(a) Effect of source and destination addresses

When 16-bit data is transferred on a 16-bit data bus, and the source and destination both start at odd

addresses, there are one more source read cycle and destination write cycle than when the source

and destination both start at even addresses.

(b) Effect of BYTE pin level

When transferring 16-bit data over an 8-bit data bus (BYTE pin = "H") in memory expansion mode and

microprocessor mode, the 16 bits of data are sent in two 8-bit blocks. Therefore, two bus cycles are

required for reading the data and two are required for writing the data. Also, in contrast to when the

CPU accesses internal memory, when the DMAC accesses internal memory (internal ROM, internal

RAM, and SFR), these areas are accessed using the data size selected by the BYTE pin.

(c) Effect of software wait

When the SFR area or a memory area with a software wait is accessed, the number of cycles is

increased for the wait by 1 bus cycle. The length of the cycle is determined by BCLK.

Figure 1.13.5 shows the example of the transfer cycles for a source read. For convenience, the destina-

tion write cycle is shown as one cycle and the source read cycles for the different conditions are shown.

In reality, the destination write cycle is subject to the same conditions as the source read cycle, with the

transfer cycle changing accordingly. When calculating the transfer cycle, remember to apply the respec-

tive conditions to both the destination write cycle and the source read cycle. For example (2) in Figure

1.13.5, if data is being transferred in 16-bit units on an 8-bit bus, two bus cycles are required for both the

source read cycle and the destination write cycle.

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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

DMAC

BCLK

Address
bus

RD signal

WR signal

Data
bus

CPU use

Source

Destination

Dummy
cycle

(1) 8-bit transfers

16-bit transfers and the source address is even.

BCLK

Address
bus

RD signal

WR signal

Data
bus

CPU use

Source

Destination

Dummy
cycle

(3) One wait is inserted into the source read under the conditions in (1)

BCLK

Address
bus

RD signal

WR signal

Data
bus

CPU use

Source

Destination

Dummy
cycle

Source + 1

(2) 16-bit transfers and the source address is odd

Transferring 16-bit data on an 8-bit data bus (In this case, there are also two destination cycles).

BCLK

Address
bus

RD signal

WR signal

Data
bus

CPU use

Source

Destination

Dummy
cycle

Source + 1

(4) One wait is inserted into the source read under the conditions in (2)

(When 16-bit data is transferred on an 8-bit data bus, there are two destination cycles).

Note: The same timing changes occur with the respective conditions at the destination as at the source.

Figure 1.13.5. Example of the transfer cycles for a source read

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DMAC

DMA enable bit

Setting the DMA enable bit to "1" makes the DMAC active. The DMAC carries out the following operations

at the time data transfer starts immediately after DMAC is turned active.

(1) Reloads the value of one of the source pointer and the destination pointer - the one specified for the

forward direction - to the forward direction address pointer.

(2) Reloads the value of the transfer counter reload register to the transfer counter.

Thus overwriting "1" to the DMA enable bit with the DMAC being active carries out the operations given

above, so the DMAC operates again from the initial state at the instant "1" is overwritten to the DMA

enable bit.

DMA request bit

The DMAC can generate a DMA transfer request signal triggered by a factor chosen in advance out of

DMA request factors for each channel.

DMA request factors include the following.

* Factors effected by using the interrupt request signals from the built-in peripheral functions and software

DMA factors (internal factors) effected by a program.

* External factors effected by utilizing the input from external interrupt signals.

For the selection of DMA request factors, see the descriptions of the DMAi factor selection register.

The DMA request bit turns to "1" if the DMA transfer request signal occurs regardless of the DMAC's state

(regardless of whether the DMA enable bit is set to "1" or "0"). It turns to "0" immediately before data

transfer starts.

In addition, it can be set to "0" by use of a program, but cannot be set to "1".

There can be instances in which a change in DMA request factor selection bit causes the DMA request bit

to turn to "1". So be sure to set the DMA request bit to "0" after the DMA request factor selection bit is

changed.

The DMA request bit turns to "1" if a DMA transfer request signal occurs, and turns to "0" immediately

before data transfer starts. If the DMAC is active, data transfer starts immediately, so the value of the

DMA request bit, if read by use of a program, turns out to be "0" in most cases. To examine whether the

DMAC is active, read the DMA enable bit.

Here follows the timing of changes in the DMA request bit.

(1) Internal factors

Except the DMA request factors triggered by software, the timing for the DMA request bit to turn to "1" due

to an internal factor is the same as the timing for the interrupt request bit of the interrupt control register to

turn to "1" due to several factors.

Turning the DMA request bit to "0" due to an internal factor is timed to be effected immediately before the

transfer starts.

(2) External factors

_______

An external factor is a factor caused to occur by the leading edge of input from the INTi pin (i depends on

which DMAC channel is used).

_______

Selecting the INTi pins as external factors using the DMA request factor selection bit causes input from

these pins to become the DMA transfer request signals.

The timing for the DMA request bit to turn to "1" when an external factor is selected synchronizes with the

signal's edge applicable to the function specified by the DMA request factor selection bit (synchronizes

_______

with the trailing edge of the input signal to each INTi pin, for example).

With an external factor selected, the DMA request bit is timed to turn to "0" immediately before data

transfer starts similarly to the state in which an internal factor is selected.

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DMAC

(3) The priorities of channels and DMA transfer timing

If a DMA transfer request signal falls on a single sampling cycle (a sampling cycle means one period from

the leading edge to the trailing edge of BCLK), the DMA request bits of applicable channels concurrently

turn to "1". If the channels are active at that moment, DMA0 is given a high priority to start data transfer.

When DMA0 finishes data transfer, it gives the bus right to the CPU. When the CPU finishes single bus

access, then DMA1 starts data transfer and gives the bus right to the CPU.

An example in which DMA transfer is carried out in minimum cycles at the time when DMA transfer

request signals due to external factors concurrently occur.

Figure 1.13.6 An example of DMA transfer effected by external factors.

BCLK

DMA0

DMA1

DMA0
request bit

DMA1
request bit

CPU

INT0

INT1

Obtainment
of the bus
right

An example in which DMA transmission is carried out in minimum
cycles at the time when DMA transmission request signals due to
external factors concurrently occur.

Figure 1.13.6. An example of DMA transfer effected by external factors

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Timer

Timer

There are eleven 16-bit timers. These timers can be classified by function into timers A (five) and timers B

(six). All these timers function independently. Figures 1.14.1 and 1.14.2 show the block diagram of timers.

· Timer mode
· One-shot timer mode
· PWM mode

· Event counter mode

TA0

TA1

TA2

TA3

TA4

Timer A0

Timer A1

Timer A2

Timer A3

Timer A4

C32

Timer A0 interrupt

Timer A1 interrupt

Timer A2 interrupt

Timer A3 interrupt

Timer A4 interrupt

Noise

filter

Noise

filter

Noise

filter

Noise

filter

Noise

filter

1/32

C32

1/8

1/4

CIN

Clock prescaler reset flag (bit 7
at address 0381

) set to "1"

Reset

Clock prescaler

Timer B2 overflow

Note 1: The TA0

pin (P7

) is shared with RxD

and the TB5

pin, so be careful.

Figure 1.14.1. Timer A block diagram

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Timer A

Timer A

Figure 1.14.3 shows the block diagram of timer A. Figures 1.14.4 to 1.14.6 show the timer A-related

registers.

Except in event counter mode, timers A0 through A4 all have the same function. Use the timer Ai mode

Timer A has the four operation modes listed as follows:

· Timer mode: The timer counts an internal count source.

· Event counter mode: The timer counts pulses from an external source or a timer over flow.

· One-shot timer mode: The timer stops counting when the count reaches "0000

· Pulse width modulation (PWM) mode: The timer outputs pulses of a given width.

Figure 1.14.4. Timer A-related registers (1)

Count start flag

(Address 0380

)

Up count/down count

TAi

Addresses

TAj

TAk

Timer A0

0387

0386

Timer A4

Timer A1

0389

0388

Timer A0

Timer A2

038B

038A

Timer A1

Timer A3

038D

038C

Timer A2

Timer A4

Timer A4 038F

038E

Timer A3

Timer A0

Always down count except
in event counter mode

Reload register (16)

Counter (16)

Low-order
8 bits

High-order
8 bits

Clock source
selection

· Timer
(gate function)

· Timer
· One shot
· PWM

External
trigger

TAi

(i = 0 to 4)

TB2 overflow

· Event counter

C32

Clock selection

TAj overflow

(j = i 1. Note, however, that j = 4 when i = 0)

Pulse output

Toggle flip-flop

TAi

OUT

(i = 0 to 4)

Data bus low-order bits

Data bus high-order bits

Up/down flag

Down count

(Address 0384

)

TAk overflow

(k = i + 1. Note, however, that k = 0 when i = 4)

Polarity

selection

Timer Ai mode register

Symbol

Address

When reset

TAiMR(i=0 to 4)

0396

to 039A

Bit name

Function

Bit symbol

0 0 : Timer mode
0 1 : Event counter mode
1 0 : One-shot timer mode
1 1 : Pulse width modulation

(PWM) mode

b1 b0

TCK1

MR3

MR2

MR1

TMOD1

MR0

TMOD0

TCK0

Function varies with each operation mode

Count source select bit
(Function varies with each operation mode)

Operation mode select bit

Figure 1.14.3. Block diagram of timer A

Mitsubishi microcomputers

M16C / 62A Group

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

Timer A

Figure 1.14.5. Timer A-related registers (2)

Timer A4 up/down flag

Timer A3 up/down flag

Timer A2 up/down flag

Timer A1 up/down flag

Timer A0 up/down flag

Timer A2 two-phase pulse
signal processing select bit

Timer A3 two-phase pulse
signal processing select bit

Timer A4 two-phase pulse
signal processing select bit

Symbol

Address

When reset

UDF

0384

TA4P

TA3P

TA2P

Up/down flag (Note 1)

Bit name

Function

Bit symbol

TA4UD

TA3UD

TA2UD

TA1UD

TA0UD

0 : Down count
1 : Up count

This specification becomes valid
when the up/down flag content is
selected for up/down switching
cause

0 : two-phase pulse signal

processing disabled

1 : two-phase pulse signal

processing enabled (Note 2)

When not using the two-phase
pulse signal processing function,
set the select bit to "0"

Symbol

Address

When reset

TABSR

0380

Count start flag

Bit name

Function

Bit symbol

Timer B2 count start flag

Timer B1 count start flag

Timer B0 count start flag

Timer A4 count start flag

Timer A3 count start flag

Timer A2 count start flag

Timer A1 count start flag

Timer A0 count start flag

0 : Stops counting
1 : Starts counting

TB2S

TB1S

TB0S

TA4S

TA3S

TA2S

TA1S

TA0S

Symbol

Address

When reset

TA0

0387

,0386

Indeterminate

TA1

0389

,0388

Indeterminate

TA2

038B

,038A

Indeterminate

TA3

038D

,038C

Indeterminate

TA4

038F

,038E

Indeterminate

b0 b7

(b15)

(b8)

Timer Ai register (Note 1)

· Timer mode

0000

to FFFF

Counts an internal count source

Function

Values that can be set

· Event counter mode

0000

to FFFF

Counts pulses from an external source or timer overflow

· One-shot timer mode

0000

to FFFF

Counts a one shot width

(Note 2,4)

· Pulse width modulation mode (16-bit PWM)
Functions as a 16-bit pulse width modulator

· Pulse width modulation mode (8-bit PWM)
Timer low-order address functions as an 8-bit
prescaler and high-order address functions as an 8-bit
pulse width modulator

0000

to FFFE

(Note 3,4)

Note 1: Read and write data in 16-bit units.
Note 2: When the timer Ai register is set to "0000

", the counter does not

operate and the timer Ai interrupt request is not generated. When
the pulse is set to output, the pulse does not output from the TAi

OUT

pin.

Note 3: When the timer Ai register is set to "0000

", the pulse width

modulator does not operate and the output level of the TAi

OUT

remains "L" level, therefore the timer Ai interrupt request is not
generated. This also occurs in the 8-bit pulse width modulator mode
when the significant 8 high-order bits in the timer Ai register are set
to "00

Note 4: Use MOV instruction to write to this register.

to FE

(High-order address)

to FF

(Low-order address)

(Note 3,4)

Note 1: Use MOV instruction to write to this register.
Note 2: Set the TAi

and TAi

OUT

pins correspondent port direction registers to "0".

Mitsubishi microcomputers

M16C / 62A Group

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

Timer A

Symbol

Address

When reset

CPSRF

0381

0XXXXXXX

Clock prescaler reset flag

Bit name

Function

Bit symbol

Clock prescaler reset flag

0 : No effect
1 : Prescaler is reset
(When read, the value is "0")

CPSR

Nothing is assigned.
In an attempt to write to these bits, write "0". The value, if read, turns out to be
indeterminate.

TA1TGL

Symbol

Address

When reset

TRGSR

0383

Timer A1 event/trigger
select bit

0 0 :

Input on TA1

is selected (Note)

0 1 : TB2 overflow is selected
1 0 : TA0 overflow is selected
1 1 : TA2 overflow is selected

Trigger select register

Bit name

Function

Bit symbol

0 0 :

Input on TA2

is selected (Note)

0 1 : TB2 overflow is selected
1 0 : TA1 overflow is selected
1 1 : TA3 overflow is selected

0 0 :

Input on TA3

is selected (Note)

0 1 : TB2 overflow is selected
1 0 : TA2 overflow is selected
1 1 : TA4 overflow is selected

0 0 :

Input on TA4

is selected (Note)

0 1 : TB2 overflow is selected
1 0 : TA3 overflow is selected
1 1 : TA0 overflow is selected

Timer A2 event/trigger
select bit

Timer A3 event/trigger
select bit

Timer A4 event/trigger
select bit

TA1TGH

TA2TGL

TA2TGH

TA3TGL

TA3TGH

TA4TGL

TA4TGH

b1 b0

b3 b2

b5 b4

b7 b6

Note: Set the corresponding port direction register to "0".

TA1OS

TA2OS

TA0OS

One-shot start flag

Symbol

Address

When reset

ONSF

0382

00X00000

Timer A0 one-shot start flag

Timer A1 one-shot start flag

Timer A2 one-shot start flag

Timer A3 one-shot start flag

Timer A4 one-shot start flag

TA3OS

TA4OS

Bit name

Function

Bit symbol

Nothing is assigned.
In an attempt to write to this bit, write "0". The value, if read, turns out to be indeterminate.

TA0TGL

TA0TGH

0 0 :

Input on TA0

is selected (Note)

0 1 : TB2 overflow is selected
1 0 : TA4 overflow is selected
1 1 : TA1 overflow is selected

Timer A0 event/trigger
select bit

b7 b6

Note: Set the corresponding port direction register to "0".

1 : Timer start
When read, the value is "0"

Figure 1.14.6. Timer A-related registers (3)

Mitsubishi microcomputers

M16C / 62A Group

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

Timer A

Item

Specification

Count source

, f

C32

Count operation

· Down count

· When the timer underflows, it reloads the reload register contents before continuing counting

Divide ratio

1/(n+1)

n : Set value

Count start condition

Count start flag is set (= 1)

Count stop condition

Count start flag is reset (= 0)

Interrupt request generation timing

When the timer underflows

TAi

pin function

Programmable I/O port or gate input

TAi

OUT

pin function

Programmable I/O port or pulse output

Read from timer

Count value can be read out by reading timer Ai register

Write to timer

· When counting stopped

When a value is written to timer Ai register, it is written to both reload register and counter

· When counting in progress

When a value is written to timer Ai register, it is written to only reload register

(Transferred to counter at next reload time)

Select function

· Gate function

Counting can be started and stopped by the TAi

pin's input signal

· Pulse output function

Each time the timer underflows, the TAi

OUT

pin's polarity is reversed

(1) Timer mode

In this mode, the timer counts an internally generated count source. (See Table 1.14.1.) Figure 1.14.7

shows the timer Ai mode register in timer mode.

Table 1.14.1. Specifications of timer mode

Note 1: The settings of the corresponding port register and port direction register

are invalid.

Note 2: The bit can be "0" or "1".

Note 3: Set the corresponding port direction register to "0".

Timer Ai mode register

Symbol

Address

When reset

TAiMR(i=0 to 4)

0396

to 039A

Bit name

Function

Bit symbol

Operation mode
select bit

0 0 : Timer mode

b1 b0

TMOD1

TMOD0

MR0

Pulse output function
select bit

0 : Pulse is not output
(TA

iOUT

pin is a normal port pin)

1 : Pulse is output (Note 1)
(TA

iOUT

pin is a pulse output pin)

Gate function select bit

0 X

(Note 2)

: Gate function not available

(TAi

pin is a normal port pin)

1 0 : Timer counts only when TA

iIN

pin is

held "L" (Note 3)

1 1 : Timer counts only when TA

iIN

pin is

held "H" (Note 3)

b4 b3

MR2

MR1

MR3

0 (Must always be "0" in timer mode)

0 0 : f

0 1 : f

1 0 : f

1 1 : f

C32

b7 b6

TCK1

TCK0

Count source select bit

0 0

Figure 1.14.7. Timer Ai mode register in timer mode

Mitsubishi microcomputers

M16C / 62A Group

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

Timer A

Item

Specification

Count source

· External signals input to TAi

pin (effective edge can be selected by software)

· TB2 overflow, TAj overflow

Count operation

· Up count or down count can be selected by external signal or software

· When the timer overflows or underflows, it reloads the reload register con

tents before continuing counting (Note)

Divide ratio

1/ (FFFF

- n + 1) for up count

1/ (n + 1) for down count

n : Set value

Count start condition

Count start flag is set (= 1)

Count stop condition

Count start flag is reset (= 0)

Interrupt request generation timing The timer overflows or underflows
TAi

pin function

Programmable I/O port or count source input

TAi

OUT

pin function

Programmable I/O port, pulse output, or up/down count select input

Read from timer

Count value can be read out by reading timer Ai register

Write to timer

· When counting stopped

When a value is written to timer Ai register, it is written to both reload register and counter

· When counting in progress

When a value is written to timer Ai register, it is written to only reload register
(Transferred to counter at next reload time)

Select function

· Free-run count function

Even when the timer overflows or underflows, the reload register content is not reloaded to it

· Pulse output function

Each time the timer overflows or underflows, the TAi

OUT

pin's polarity is reversed

Note: This does not apply when the free-run function is selected.

(2) Event counter mode

In this mode, the timer counts an external signal or an internal timer's overflow. Timers A0 and A1 can
count a single-phase external signal. Timers A2, A3, and A4 can count a single-phase and a two-phase
external signal. Table 1.14.2 lists timer specifications when counting a single-phase external signal.
Figure 1.14.8 shows the timer Ai mode register in event counter mode.
Table 1.14.3 lists timer specifications when counting a two-phase external signal. Figure 1.14.9 shows

the timer Ai mode register in event counter mode.

Table 1.14.2. Timer specifications in event counter mode (when not processing two-phase pulse signal)

Figure 1.14.8. Timer Ai mode register in event counter mode

Note 1: In event counter mode, the count source is selected by the event / trigger select bit

(addresses 0382

and 0383

Note 2: The settings of the corresponding port register and port direction register are invalid.
Note 3: Valid only when counting an external signal.
Note 4: When an "L" signal is input to the TAi

OUT

pin, the downcount is activated. When "H",

the upcount is activated. Set the corresponding port direction register to "0".

Symbol

Address

When reset

TAiMR(i = 0 to 4) 0396

to 039A

Operation mode select bit

0 1 : Event counter mode

(Note 1)

b1 b0

TMOD0

MR0

Pulse output function
select bit

0 : Pulse is not output

(TA

iOUT

pin is a normal port pin)

1 : Pulse is output (Note 2)

(TA

iOUT

pin is a pulse output pin)

Count polarity
select bit (Note 3)

MR2

MR1

MR3

0 (Must always be "0" in event counter mode)

TCK0

Count operation type
select bit

0 1

0 : Counts external signal's falling edge
1 : Counts external signal's rising edge

Up/down switching
cause select bit

0 : Up/down flag's content
1 : TA

iOUT

pin's input signal (Note 4)

0 : Reload type
1 : Free-run type

Bit symbol

Bit name

Function

R W

TCK1

Invalid when not using two-phase pulse signal processing
Can be "0" or "1"

TMOD1

Timer Ai mode register
(When not using two-phase pulse signal processing)

Mitsubishi microcomputers

M16C / 62A Group

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

Timer A

Item

Specification

Count source

· Two-phase pulse signals input to TAi

or TAi

OUT

Count operation

· Up count or down count can be selected by two-phase pulse signal

· When the timer overflows or underflows, the reload register content is

reloaded and the timer starts over again (Note 1)

Divide ratio

1/ (FFFF

n + 1) for up count

1/ (n + 1) for down count

n : Set value

Count start condition

Count start flag is set (= 1)

Count stop condition

Count start flag is reset (= 0)

Interrupt request generation timing

Timer overflows or underflows

TAi

pin function

Two-phase pulse input (Set the TAi

pin correspondent port direction register to "0".)

TAi

OUT

pin function

Two-phase pulse input (Set the TAi

OUT

pin correspondent port direction register to "0".)

Read from timer

Count value can be read out by reading timer A2, A3, or A4 register

Write to timer

· When counting stopped

When a value is written to timer A2, A3, or A4 register, it is written to both

reload register and counter

· When counting in progress

When a value is written to timer A2, A3, or A4 register, it is written to only

reload register. (Transferred to counter at next reload time.)

Select function (Note 2)

· Normal processing operation (timer A2 and timer A3)

The timer counts up rising edges or counts down falling edges on the TAi

pin when input signal on the TAi

OUT

pin is "H".

· Multiply-by-4 processing operation (timer A3 and timer A4)

If the phase relationship is such that the TAi

pin goes "H" when the input

signal on the TAi

OUT

pin is "H", the timer counts up rising and falling edges

on the TAi

OUT

and TAi

pins. If the phase relationship is such that the

TAi

pin goes "L" when the input signal on the TAi

OUT

pin is "H", the timer

counts down rising and falling edges on the TAi

OUT

and TAi

pins.

Note 1: This does not apply when the free-run function is selected.

Note 2: Timer A3 alone can be selected. Timer A2 is fixed to normal processing operation, and timer A4

is fixed to multiply-by-4 processing operation.

Table 1.14.3. Timer specifications in event counter mode (when processing two-phase pulse signal with timers A2, A3, and A4)

TAi

OUT

Up
count

Down
count

TAi

(i=2,3)

TAi

OUT

TAi

(i=3,4)

Count up all edges

Count down all edges

Mitsubishi microcomputers

M16C / 62A Group

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

Timer A

Note 1: This bit is valid for timer A3 mode register. Timer A2 is fixed to normal processing

operation, and timer A4 is fixed to multiply-by-4 processing operation.

Note 2: When performing two-phase pulse signal processing, make sure the two-phase pulse

signal processing operation select bit (address 0384

) is set to "1". Also, always be

sure to set the event/trigger select bit (addresses 0382

and 0383

) to "00".

Timer Ai mode register
(When using two-phase pulse signal processing)

Symbol

Address

When reset

TAiMR(i = 2 to 4) 0398

to 039A

Operation mode select bit

0 1 : Event counter mode

b1 b0

TMOD1

TMOD0

MR0

0 (Must always be "0" when using two-phase pulse signal
processing)

MR2

MR1

MR3

0 (Must always be "0" when using two-phase pulse signal
processing)

TCK1

TCK0

0 1

1 (Must always be "1" when using two-phase pulse signal
processing)

Bit name

Function

Count operation type
select bit

Two-phase pulse
processing operation
select bit (Note 1)(Note 2)

0 : Reload type
1 : Free-run type

0 : Normal processing operation
1 : Multiply-by-4 processing operation

Figure 1.14.9. Timer Ai mode register in event counter mode

Mitsubishi microcomputers

M16C / 62A Group

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

Timer A

Item

Specification

Count source

, f

C32

Count operation

· The timer counts down

· When the count reaches 0000

, the timer stops counting after reloading a new count

· If a trigger occurs when counting, the timer reloads a new count and restarts counting

Divide ratio

1/n n : Set value

Count start condition

· An external trigger is input

· The timer overflows

· The one-shot start flag is set (= 1)

Count stop condition

· A new count is reloaded after the count has reached 0000

· The count start flag is reset (= 0)

Interrupt request generation timing

The count reaches 0000

TAi

pin function

Programmable I/O port or trigger input

TAi

OUT

pin function

Programmable I/O port or pulse output

Read from timer

When timer Ai register is read, it indicates an indeterminate value

Write to timer

· When counting stopped

When a value is written to timer Ai register, it is written to both reload

· When counting in progress

When a value is written to timer Ai register, it is written to only reload register

(Transferred to counter at next reload time)

Table 1.14.4. Timer specifications in one-shot timer mode

Figure 1.14.10. Timer Ai mode register in one-shot timer mode

(3) One-shot timer mode

In this mode, the timer operates only once. (See Table 1.14.4.) When a trigger occurs, the timer starts up
and continues operating for a given period. Figure 1.14.10 shows the timer Ai mode register in one-shot
timer mode.

Bit name

Timer Ai mode register

Symbol

Address

When reset

TAiMR(i = 0 to 4) 0396

to 039A

Function

Bit symbol

Operation mode select bit

1 0 : One-shot timer mode

b1 b0

TMOD1

TMOD0

MR0

Pulse output function
select bit

0 : Pulse is not output
(TA

iOUT

pin is a normal port pin)

1 : Pulse is output (Note 1)
(TAi

OUT

pin is a pulse output pin)

MR2

MR1

MR3

0 (Must always be "0" in one-shot timer mode)

0 0 : f

0 1 : f

1 0 : f

1 1 : f

C32

b7 b6

TCK1

TCK0

Count source select bit

1 0

0 : One-shot start flag is valid
1 : Selected by event/trigger select

bits

Trigger select bit

External trigger select
bit (Note 2)

0 : Falling edge of TAi

pin's input signal (Note 3)

1 : Rising edge of TAi

pin's input signal (Note 3)

Note 1: The settings of the corresponding port register and port direction register are invalid.
Note 2: Valid only when the TAi

pin is selected by the event/trigger select bit

(addresses 0382

and 0383

). If timer overflow is selected, this bit can be "1" or "0".

Note 3: Set the corresponding port direction register to "0".

Mitsubishi microcomputers

M16C / 62A Group

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

Timer A

(4) Pulse width modulation (PWM) mode

In this mode, the timer outputs pulses of a given width in succession. (See Table 1.14.5.) In this mode, the

counter functions as either a 16-bit pulse width modulator or an 8-bit pulse width modulator. Figure

1.14.11 shows the timer Ai mode register in pulse width modulation mode. Figure 1.14.12 shows the

example of how a 16-bit pulse width modulator operates. Figure 1.14.13 shows the example of how an 8-

bit pulse width modulator operates.

Figure 1.14.11. Timer Ai mode register in pulse width modulation mode

Table 1.14.5. Timer specifications in pulse width modulation mode

Bit name

Timer Ai mode register

Symbol

Address

When reset

TAiMR(i=0 to 4)

0396

to 039A

Function

Bit symbol

Operation mode
select bit

1 1 : PWM mode

b1 b0

TMOD1

TMOD0

MR0

MR2

MR1

MR3

0 0 : f

0 1 : f

1 0 : f

1 1 : f

C32

b7 b6

TCK1

TCK0

Count source select bit

1 (Must always be "1" in PWM mode)

16/8-bit PWM mode
select bit

0: Functions as a 16-bit pulse width modulator
1: Functions as an 8-bit pulse width modulator

Trigger select bit

External trigger select
bit (Note 1)

0: Falling edge of TAi

pin's input signal (Note 2)

1: Rising edge of TAi

pin's input signal (Note 2)

0: Count start flag is valid
1: Selected by event/trigger select bits

Note 1: Valid only when the TA

iIN

pin is selected by the event/trigger select bit

(addresses 0382

and 0383

). If timer overflow is selected, this bit can be "1" or "0".

Note 2: Set the corresponding port direction register to "0".

Item

Specification

Count source

, f

C32

Count operation

· The timer counts down (operating as an 8-bit or a 16-bit pulse width modulator)
· The timer reloads a new count at a rising edge of PWM pulse and continues counting
· The timer is not affected by a trigger that occurs when counting

16-bit PWM

· High level width

n / fi

n : Set value

· Cycle time

-1) / fi fixed

8-bit PWM

· High level width n (m+1) / fi

n : values set to timer Ai register's high-order address

· Cycle time

-1) (m+1) / fi

m : values set to timer Ai register's low-order address

Count start condition

· External trigger is input
· The timer overflows
· The count start flag is set (= 1)

Count stop condition

· The count start flag is reset (= 0)

Interrupt request generation timing

PWM pulse goes "L"

TAi

pin function

Programmable I/O port or trigger input

TAi

OUT

pin function

Pulse output

Read from timer

When timer Ai register is read, it indicates an indeterminate value

Write to timer

· When counting stopped

When a value is written to timer Ai register, it is written to both reload
register and counter

· When counting in progress

When a value is written to timer Ai register, it is written to only reload register
(Transferred to counter at next reload time)

Mitsubishi microcomputers

M16C / 62A Group

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

Timer A

1 / f

(2 1)

Count source

iIN

input signal

PWM pulse output
from TA

iOUT

Condition : Reload register = 0003

, when external trigger

(rising edge of TA

iIN

pin input signal) is selected

Trigger is not generated by this signal

"H"

"L"

Timer Ai interrupt
request bit

"1"

"0"

Cleared to "0" when interrupt request is accepted, or cleared by software

: Frequency of count source

, f

C32

)

Note: n = 0000

to FFFE

1 / f

Count source (Note1)

iIN

pin input signal

Underflow signal of
8-bit prescaler (Note2)

PWM pulse output
from TA

iOUT

"H"

"L"

"1"

"0"

Timer Ai interrupt
request bit

Cleared to "0" when interrupt request is accepted, or cleaerd by software

: Frequency of count source

, f

C32

)

Note 1: The 8-bit prescaler counts the count source.
Note 2: The 8-bit pulse width modulator counts the 8-bit prescaler's underflow signal.
Note 3: m = 00

to FF

; n = 00

to FE

Condition : Reload register high-order 8 bits = 02

Reload register low-order 8 bits = 02

External trigger (falling edge of TA

iIN

pin input signal) is selected

1 / f

X (m

+ 1) X (2 1)

1 / f

X (m + 1) X n

1 / f

X (m + 1)

Figure 1.14.12. Example of how a 16-bit pulse width modulator operates

Figure 1.14.13. Example of how an 8-bit pulse width modulator operates

Mitsubishi microcomputers

M16C / 62A Group

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

Timer B

Timer B

Figure 1.14.14 shows the block diagram of timer B. Figures 1.14.15 and 1.14.16 show the timer B-related

registers.

Use the timer Bi mode register (i = 0 to 5) bits 0 and 1 to choose the desired mode.

Timer B has three operation modes listed as follows:

· Timer mode: The timer counts an internal count source.

· Event counter mode: The timer counts pulses from an external source or a timer overflow.

· Pulse period/pulse width measuring mode: The timer measures an external signal's pulse period or

pulse width.

Figure 1.14.14. Block diagram of timer B

Timer Bi mode register

Symbol

Address

When reset

TBiMR(i = 0 to 5) 039B

to 039D

00XX0000

035B

to 035D

00XX0000

Bit name

Function

Bit symbol

0 0 : Timer mode
0 1 : Event counter mode
1 0 : Pulse period/pulse width

measurement mode

1 1 : Must not be set.

b1 b0

TCK1

MR3

MR2

MR1

TMOD1

MR0

TMOD0

TCK0

Function varies with each operation mode

Count source select bit
(Function varies with each operation mode)

Operation mode select bit

(Note 1)

(Note 2)

Note 1: Timer B0, timer B3.
Note 2: Timer B1, timer B2, timer B4, timer B5.

Clock source selection

(address 0380

)

· Event counter

· Timer
· Pulse period/pulse width measurement

Reload register (16)

Low-order 8 bits

High-order 8 bits

Data bus low-order bits

Data bus high-order bits

TBj overflow
(j = i 1. Note, however,
j = 2 when i = 0,
j = 5 when i = 3)

Can be selected in only
event counter mode

Count start flag

C32

Polarity switching
and edge pulse

TBi

(i = 0 to 5)

Counter reset circuit

Counter (16)

TBi Address

TBj

Timer B0 0391

0390

Timer B2

Timer B1 0393

0392

Timer B0

Timer B2 0395

0394

Timer B1

Timer B3 0351

0350

Timer B5

Timer B4 0353

0352

Timer B3

Timer B5 0355

0354

Timer B4

Figure 1.14.15. Timer B-related registers (1)

Mitsubishi microcomputers

M16C / 62A Group

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

Timer B

Symbol

Address

When reset

TABSR

0380

Count start flag

Bit name

Bit symbol

Timer B2 count start flag

Timer B1 count start flag

Timer B0 count start flag

Timer A4 count start flag

Timer A3 count start flag

Timer A2 count start flag

Timer A1 count start flag

Timer A0 count start flag

0 : Stops counting
1 : Starts counting

TB2S

TB1S

TB0S

TA4S

TA3S

TA2S

TA1S

TA0S

Function

Symbol

Address

When reset

CPSRF

0381

0XXXXXXX

Clock prescaler reset flag

Bit name

Function

Bit symbol

Clock prescaler reset flag

0 : No effect
1 : Prescaler is reset
(When read, the value is "0")

CPSR

Symbol

Address

When reset

TB0

0391

, 0390

Indeterminate

TB1

0393

, 0392

Indeterminate

TB2

0395

, 0394

Indeterminate

TB3

0351

, 0350

Indeterminate

TB4

0353

, 0352

Indeterminate

TB5

0355

, 0354

Indeterminate

b0 b7

(b15)

(b8)

Timer Bi register (Note)

· Pulse period / pulse width measurement mode
Measures a pulse period or width

· Timer mode

0000

to FFFF

Counts the timer's period

Function

Values that can be set

· Event counter mode

0000

to FFFF

Counts external pulses input or a timer overflow

Note: Read and write data in 16-bit units.

Symbol

Address

When reset

TBSR

0340

000XXXXX

Timer B3, 4, 5 count start flag

Bit name

Bit symbol

Timer B5 count start flag

Timer B4 count start flag

Timer B3 count start flag

0 : Stops counting
1 : Starts counting

TB5S

TB4S

TB3S

Nothing is assigned.

In an attempt to write to these bits, write "0". The value, if read, turns
out to be indeterminate.

Function

Nothing is assigned.

In an attempt to write to these bits, write "0". The value, if read, turns
out to be indeterminate.

Figure 1.14.16. Timer B-related registers (2)

Mitsubishi microcomputers

M16C / 62A Group

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

Timer B

Item

Specification

Count source

, f

C32

Count operation

· Counts down

· When the timer underflows, it reloads the reload register contents before

continuing counting

Divide ratio

1/(n+1)

n : Set value

Count start condition

Count start flag is set (= 1)

Count stop condition

Count start flag is reset (= 0)

Interrupt request generation timing

The timer underflows

TBi

pin function

Programmable I/O port

Read from timer

Count value is read out by reading timer Bi register

Write to timer

· When counting stopped

When a value is written to timer Bi register, it is written to both reload register and counter

· When counting in progress

When a value is written to timer Bi register, it is written to only reload register

(Transferred to counter at next reload time)

(1) Timer mode

In this mode, the timer counts an internally generated count source. (See Table 1.14.6.) Figure 1.14.17

shows the timer Bi mode register in timer mode.

Table 1.14.6. Timer specifications in timer mode

Note 1: Timer B0, timer B3.
Note 2: Timer B1, timer B2, timer B4, timer B5.

Timer Bi mode register

Symbol

Address

When reset

TBiMR(i=0 to 5)

039B

to 039D

00XX0000

035B

to 035D

00XX0000

Bit name

Function

Bit symbol

Operation mode select bit

0 0 : Timer mode

b1 b0

TMOD1

TMOD0

MR0

Invalid in timer mode
Can be "0" or "1"

MR2

MR1

MR3

0 0 : f

0 1 : f

1 0 : f

1 1 : f

C32

TCK1

TCK0

Count source select bit

Invalid in timer mode.
In an attempt to write to this bit, write "0". The value, if read in
timer mode, turns out to be indeterminate.

0 (Fixed to "0" in timer mode ; i = 0, 3)

Nothing is assiigned (i = 1, 2, 4, 5).
In an attempt to write to this bit, write "0". The value, if read, turns out
to be indeterminate.

(Note 1)

(Note 2)

b7 b6

Figure 1.14.17. Timer Bi mode register in timer mode

Mitsubishi microcomputers

M16C / 62A Group

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

Timer B

Item

Specification

Count source

· External signals input to TBi

· Effective edge of count source can be a rising edge, a falling edge, or falling

and rising edges as selected by software

Count operation

· Counts down

· When the timer underflows, it reloads the reload register contents before

continuing counting

Divide ratio

1/(n+1)

n : Set value

Count start condition

Count start flag is set (= 1)

Count stop condition

Count start flag is reset (= 0)

Interrupt request generation timing The timer underflows

TBi

pin function

Count source input

Read from timer

Count value can be read out by reading timer Bi register

Write to timer

· When counting stopped

When a value is written to timer Bi register, it is written to both reload register and counter

· When counting in progress

When a value is written to timer Bi register, it is written to only reload register

(Transferred to counter at next reload time)

(2) Event counter mode

In this mode, the timer counts an external signal or an internal timer's overflow. (See Table 1.14.7.)

Figure 1.14.18 shows the timer Bi mode register in event counter mode.

Table 1.14.7. Timer specifications in event counter mode

Figure 1.14.18. Timer Bi mode register in event counter mode

Timer Bi mode register

Symbol

Address

When reset

TBiMR(i=0 to 5)

039B

to 039D

00XX0000

035B

to 035D

00XX0000

Bit name

Function

Bit symbol

Operation mode select bit

0 1 : Event counter mode

b1 b0

TMOD1

TMOD0

MR0

Count polarity select
bit

(Note 1)

MR2

MR1

MR3

Invalid in event counter mode.
In an attempt to write to this bit, write "0". The value, if read in
event counter mode, turns out to be indeterminate.

TCK1

TCK0

0 1

0 0 : Counts external signal's

falling edges

0 1 : Counts external signal's

rising edges

1 0 : Counts external signal's

falling and rising edges

1 1 : Must not be set.

b3 b2

Nothing is assigned (i = 1, 2, 4, 5).
In an attempt to write to this bit, write "0". The value, if read,
turns out to be indeterminate.

Note 1: Valid only when input from the TBi

pin is selected as the event clock.

If timer's overflow is selected, this bit can be "0" or "1".

Note 2: Timer B0, timer B3.
Note 3: Timer B1, timer B2, timer B4, timer B5.
Note 4: Set the corresponding port direction register to "0".

Invalid in event counter mode.
Can be "0" or "1".

Event clock select

0 : Input from TBi

pin (Note 4)

1 : TBj overflow

(j = i 1; however, j = 2 when i = 0,

j = 5 when i = 3)

0 (Fixed to "0" in event counter mode; i = 0, 3)

(Note 2)

(Note 3)

Mitsubishi microcomputers

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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

Timer B

Item

Specification

Count source

, f

C32

Count operation

· Up count

· Counter value "0000

" is transferred to reload register at measurement

pulse's effective edge and the timer continues counting

Count start condition

Count start flag is set (= 1)

Count stop condition

Count start flag is reset (= 0)

Interrupt request generation timing · When measurement pulse's effective edge is input

(Note 1)

· When an overflow occurs. (Simultaneously, the timer Bi overflow flag

changes to "1". The timer Bi overflow flag changes to "0" when the count

start flag is "1" and a value is written to the timer Bi mode register.)

TBi

pin function

Measurement pulse input

Read from timer

When timer Bi register is read, it indicates the reload register's content

(measurement result)

(Note 2)

Write to timer

Cannot be written to

(3) Pulse period/pulse width measurement mode

In this mode, the timer measures the pulse period or pulse width of an external signal. (See Table 1.14.8.)

Figure 1.14.19 shows the timer Bi mode register in pulse period/pulse width measurement mode. Figure

1.14.20 shows the operation timing when measuring a pulse period. Figure 1.14.21 shows the operation

timing when measuring a pulse width.

Table 1.14.8. Timer specifications in pulse period/pulse width measurement mode

Figure 1.14.19. Timer Bi mode register in pulse period/pulse width measurement mode

Note 1: An interrupt request is not generated when the first effective edge is input after the timer has started counting.

Note 2: The value read out from the timer Bi register is indeterminate until the second effective edge is input

after the timer has started counting.

Timer Bi mode register

Symbol

Address

When reset

TBiMR(i=0 to 5)

039B

to 039D

00XX0000

035B

to 035D

00XX0000

Bit name

Bit symbol

Operation mode
select bit

1 0 : Pulse period / pulse width

measurement mode

b1 b0

TMOD1

TMOD0

MR0

Measurement mode
select bit

MR2

MR1

MR3

TCK1

TCK0

0 0 : Pulse period measurement (Interval between

measurement pulse's falling edge to falling edge)

0 1 : Pulse period measurement (Interval between

measurement pulse's rising edge to rising edge)

1 0 : Pulse width measurement (Interval between

measurement pulse's falling edge to rising edge,
and between rising edge to falling edge)

1 1 : Must not be set.

Function

b3 b2

Nothing is assigned (i = 1, 2, 4, 5).
In an attempt to write to this bit, write "0". The value, if read, turns out to be
indeterminate.

Count source
select bit

Timer Bi overflow
flag ( Note 1)

0 : Timer did not overflow
1 : Timer has overflowed

0 0 : f

0 1 : f

1 0 : f

1 1 : f

C32

b7 b6

Note 1: It is indeterminate when reset. The timer Bi overflow flag changes to "0" when the count start flag is "1"

and a value is written to the timer Bi mode register. This flag cannot be set to "1" by software.

Note 2: Timer B0, timer B3.
Note 3: Timer B1, timer B2, timer B4, timer B5.

0 (Fixed to "0" in pulse period/pulse width measurement mode; i = 0, 3)

(Note 2)

(Note 3)

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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

Timer B

Figure 1.14.21. Operation timing when measuring a pulse width

Measurement pulse

"H"

Count source

Count start flag

Timer Bi interrupt
request bit

Timing at which counter
reaches "0000

"1"

Transfer
(measured value)

"L"

"0"

Timer Bi overflow flag

"1"

"0"

Note 1: Counter is initialized at completion of measurement.
Note 2: Timer has overflowed.

(Note 1)

Transfer
(measured
value)

(Note 1)

Cleared to "0" when interrupt request is accepted, or cleared by software.

(Note 2)

Transfer
(indeterminate
value)

Reload register counter
transfer timing

Figure 1.14.20. Operation timing when measuring a pulse period

Count source

Measurement pulse

Count start flag

Timer Bi interrupt
request bit

Timing at which counter
reaches "0000

"H"

"1"

Transfer
(indeterminate value)

"L"

"0"

Timer Bi overflow flag

"1"

"0"

Note 1: Counter is initialized at completion of measurement.
Note 2: Timer has overflowed.

(Note 1)

When measuring measurement pulse time interval from falling edge to falling edge

(Note 2)

Cleared to "0" when interrupt request is accepted, or cleared by software.

Transfer
(measured value)

"1"

Reload register counter
transfer timing

Mitsubishi microcomputers

M16C / 62A Group

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

Timers' functions for three-phase motor control

Timers' functions for three-phase motor control

Use of more than one built-in timer A and timer B provides the means of outputting three-phase motor

driving waveforms.

Figures 1.15.1 to 1.15.3 show registers related to timers for three-phase motor control.

Three-phase PWM control register 0

Symbol

Address

When reset

INVC0

0348

b4 b3

Effective interrupt output
polarity select bit

INV00

Bit symbol

Bit name

Description

INV01

Effective interrupt output
specification bit
(Note 4)

INV02

Mode select bit
(Note 2)

INV04

Positive and negative
phases concurrent L
output disable function
enable bit

INV07

Software trigger bit

INV06

Modulation mode select
bit (Note 3)

INV05

Positive and negative
phases concurrent L
output detect flag

INV03

Output control
bit

0: A timer B2 interrupt occurs when the timer

A1 reload control signal is "1".

1: A timer B2 interrupt occurs when the timer

A1 reload control signal is "0".

Effective only in three-phase mode 1

0: Not specified.
1: Selected by the effective interrupt output

polarity selection bit.

Effective only in three-phase mode 1

0: Normal mode
1: Three-phase PWM output mode

0: Output disabled
1: Output enabled

0: Feature disabled
1: Feature enabled

0: Not detected yet
1: Already detected

0: Triangular wave modulation mode
1: Sawtooth wave modulation mode

1: Trigger generated

The value, when read, is "0".

(Note 1)

hree-phase PWM control register 1

Symbol

Address When

reset

INVC1

0349

Bit name

Description

Bit symbol

INV10

INV11

INV12

Timer Ai start trigger
signal select bit

Timer A1-1, A2-1, A4-1
control bit

Short circuit timer count
source select bit

0: Timer B2 overflow signal
1: Timer B2 overflow signal,

signal for writing to timer B2

0: Three-phase mode 0
1: Three-phase mode 1

0 : Must not be set.
1 : f

/2 (Note)

b7 b6

b1 b0

Noting is assigned.
In an attempt to write to these bits, write "0". The value, if read, turns out to be "0".

Noting is assigned.
In an attempt to write to this bit, write "0". The value, if read, turns out to be "0".

Reserved bit

Always set to "0"

Note : To use three-phase PWM output mode, write "1" to INV12.

Note 1:
Note 2:

Note 3:

Note 4:

No value other than "0" can be written.
Selecting three-phase PWM output mode causes P8

, P8

, and P7

through P7

to output U, U, V, V, W, and W, and works the

timer for setting short circuit prevention time, the U, V, W phase output control circuits, and the circuit for setting timer B2 interrupt
frequency.
In triangular wave modulation mode:
The short circuit prevention timer starts in synchronization with the falling edge of timer Ai output.
The data transfer from the three-phase buffer register to the three-phase output shift register is made only once in synchronization
with the transfer trigger signal after writing to the three-phase output buffer register.
In sawtooth wave modulation mode:
The short circuit prevention timer starts in synchronization with the falling edge of timer A output and with the transfer trigger signal.
The data transfer from the three-phase output buffer register to the three-phase output shift register is made with respect to every
transfer trigger.
To write "1" to bit 1 (INV01) of the three-phase PWM control register 0, set in advance the content of the timer B2 interrupt
occurrences frequency set counter.

Figure 1.15.1. Registers related to timers for three-phase motor control

Mitsubishi microcomputers

M16C / 62A Group

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

Timers' functions for three-phase motor control

Three-phase output buffer register 0

Symbol

Address

When reset

IDB0

034A

Bit name

Function

Bit Symbol

b6 b5

Nothing is assigned.
In an attempt to write to these bits, write "0". The value, if read, turns out to be "0".

DU0

DUB0

DV0

DW0

DVB0

DWB0

U phase output buffer 0

Setting in U phase output buffer 0

V phase output buffer 0

W phase output buffer 0

U phase output buffer 0

V phase output buffer 0

W phase output buffer 0

Setting in V phase output buffer 0

Setting in W phase output buffer 0

Setting in V phase output buffer 0

Setting in U phase output buffer 0

Three-phase output buffer register 1

Symbol

Address

When reset

IDB1

034B

Bit name

Function

Bit Symbol

b6 b5

Nothing is assigned.
In an attempt to write to these bits, write "0". The value, if read, turns out to be "0".

DU1

DUB1

DV1

DW1

DVB1

DWB1

U phase output buffer 1

Setting in U phase output buffer 1

V phase output buffer 1

W phase output buffer 1

U phase output buffer 1

V phase output buffer 1

W phase output buffer 1

Setting in V phase output buffer 1

Setting in W phase output buffer 1

Setting in V phase output buffer 1

Setting in U phase output buffer 1

Dead time timer (Note)

Symbol

Address

When reset

DTT

034C

Indeterminate

Function

Values that can be set

Set dead time timer

1 to 255

Timer B2 interrupt occurrences frequency set counter (Note 1, 2, 3)

Symbol

Address

When reset

ICTB2

034D

Indeterminate

Function

Values that can be set

Set occurrence frequency of timer B2
interrupt request

1 to 15

Note: When executing read instruction of this register, the contents of three-phase shift
register is read out.

Note 1: In setting 1 to bit 1 (INV01) - the effective interrupt output specification bit - of three-

phase PWM control register 0, do not change the B2 interrupt occurrences frequency
set counter to deal with the timer function for three-phase motor control.

Note 2: Do not write at the timing of an overflow occurrence in timer B2.
Note 3: Use MOV instruction to write to this register.

(Note)

Note: Use MOV instruction to write to this register.

Figure 1.15.2. Registers related to timers for three-phase motor control

Mitsubishi microcomputers

M16C / 62A Group

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

Timers' functions for three-phase motor control

Figure 1.15.3. Registers related to timers for three-phase motor control

Symbol

Address

When reset

TA11

0343

,0342

Indeterminate

TA21

0345

,0344

Indeterminate

TA41

0347

,0346

Indeterminate

b0 b7

(b15)

(b8)

Counts an internal count source

0000

to FFFF

Function

Values that can be set

Timer Ai-1 register (Note)

Note: Read and write data in 16-bit units.

Symbol

Address

When reset

TA1

0389

,0388

Indeterminate

TA2

038B

,038A

Indeterminate

TA4

038F

,038E

Indeterminate

TB2

0395

,0394

Indeterminate

(b15)

(b8)

· Timer mode

0000

to FFFF

Counts an internal count source

Function

Values that can be set

· One-shot timer mode

0000

to FFFF

Counts a one shot width

(Note 2, 3)

Timer Ai register (Note 1)

TA1TGL

Symbol

Address

When reset

TRGSR

0383

Timer A1 event/trigger
select bit

0 0 :

Input on TA1

is selected (Note)

0 1 : TB2 overflow is selected
1 0 : TA0 overflow is selected
1 1 : TA2 overflow is selected

Trigger select register

Bit name

Function

Bit symbol

0 0 :

Input on TA2

is selected (Note)

0 1 : TB2 overflow is selected
1 0 : TA1 overflow is selected
1 1 : TA3 overflow is selected

0 0 :

Input on TA3

is selected (Note)

0 1 : TB2 overflow is selected
1 0 : TA2 overflow is selected
1 1 : TA4 overflow is selected

0 0 :

Input on TA4

is selected (Note)

0 1 : TB2 overflow is selected
1 0 : TA3 overflow is selected
1 1 : TA0 overflow is selected

Timer A2 event/trigger
select bit

Timer A3 event/trigger
select bit

Timer A4 event/trigger
select bit

TA1TGH

TA2TGL

TA2TGH

TA3TGL

TA3TGH

TA4TGL

TA4TGH

b1 b0

b3 b2

b5 b4

b7 b6

Note: Set the corresponding port direction register to "0".

b4 b3

Symbol

Address

When reset

TABSR

0380

Count start flag

Bit name

Function

Bit symbol

b7 b6

b1 b0

Timer B2 count start flag

Timer B1 count start flag

Timer B0 count start flag

Timer A4 count start flag

Timer A3 count start flag

Timer A2 count start flag

Timer A1 count start flag

Timer A0 count start flag

0 : Stops counting
1 : Starts counting

TB2S

TB1S

TB0S

TA4S

TA3S

TA2S

TA1S

TA0S

Note 1: Read and write data in 16-bit units.
Note 2: When the timer Ai register is set to "0000

", the counter does not operate

and a timer Ai interrupt does not occur.
Note 3: Use MOV instruction to write to this register.

Mitsubishi microcomputers

M16C / 62A Group

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

Timers' functions for three-phase motor control

Bit name

Timer Ai mode register

Symbol

Address

When reset

TA1MR

0397

TA2MR

0398

TA3MR

039A

Function

Bit symbol

b2 b1

Operation mode
select bit

1 0 : One-shot timer mode

b1 b0

TMOD1

TMOD0

MR0

Pulse output function
select bit

0 (Must always be "0" in three-phase PWM
output mode)

MR2

MR1

MR3

0 (Must always be "0" in one-shot timer mode)

0 0 : f

0 1 : f

1 0 : f

1 1 : f

C32

b7 b6

TCK1

TCK0

Count source select bit

1 0

1 : Selected by event/trigger select

Trigger select bit

External trigger select
bit

Timer B2 mode register

Symbol

Address

When reset

TB2MR

039D

00XX0000

Bit name

Function

Bit symbol

b5 b4

Operation mode select bit

0 0 : Timer mode

b1 b0

TMOD1

TMOD0

MR0

Invalid in timer mode
Can be "0" or "1"

MR2

MR1

MR3

0 0 : f

0 1 : f

1 0 : f

1 1 : f

C32

TCK1

TCK0

Count source select bit

Invalid in timer mode.
In an attempt to write to this bit, write "0". When read in timer mode,
its content is indeterminate.

0 (Fixed to "0" in timer mode)

b7 b6

Invalid in three-phase PWM output mode

Figure 1.15.4. Timer mode registers in three-phase PWM output mode

Three-phase motor driving waveform output mode (three-phase PWM output mode)

Setting "1" in the mode select bit (bit 2 at 0348

) shown in Figure 1.15.1 - causes three-phase PWM

output mode that uses four timers A1, A2, A4, and B2 to be selected. As shown in Figure 1.15.4, set

timers A1, A2, and A4 in one-shot timer mode, set the trigger in timer B2, and set timer B2 in timer mode

using the respective timer mode registers.

Mitsubishi microcomputers

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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

Timers' functions for three-phase motor control

Figure 1.15.5 shows the block diagram for three-phase PWM output mode. In three-phase PWM output

___

mode, the positive-phase waveforms (U phase, V phase, and W phase) and negative waveforms (U

___

phase, V phase, and W phase), six waveforms in total, are output from P8

, P8

, P7

, and P7

___

as active on the "L" level. Of the timers used in this mode, timer A4 controls the U phase and U phase,

___

timer A1 controls the V phase and V phase, and timer A2 controls the W phase and W phase respectively;

timer B2 controls the periods of one-shot pulse output from timers A4, A1, and A2.

In outputting a waveform, dead time can be set so as to cause the "L" level of the positive waveform

___

output (U phase, V phase, and W phase) not to lap over the "L" level of the negative waveform output (U

___

phase, V phase, and W phase).

To set short circuit time, use three 8-bit timers sharing the reload register for setting dead time. A value

from 1 through 255 can be set as the count of the timer for setting dead time. The timer for setting dead

time works as a one-shot timer. If a value is written to the dead time timer (034C

), the value is written to

the reload register shared by the three timers for setting dead time.

Any of the timers for setting dead time takes the value of the reload register into its counter, if a start

trigger comes from its corresponding timer, and performs a down count in line with the clock source

selected by the dead time timer count source select bit (bit 2 at 0349

). The timer can receive another

trigger again before the workings due to the previous trigger are completed. In this instance, the timer

performs a down count from the reload register's content after its transfer, provoked by the trigger, to the

timer for setting dead time.

Since the timer for setting dead time works as a one-shot timer, it starts outputting pulses if a trigger

comes; it stops outputting pulses as soon as its content becomes 00

, and waits for the next trigger to

come.

___

The positive waveforms (U phase, V phase, and W phase) and the negative waveforms (U phase, V

___

phase, and W phase) in three-phase PWM output mode are output from respective ports by means of

setting "1" in the output control bit (bit 3 at 0348

). Setting "0" in this bit causes the ports to be the state

of set by port direction register. This bit can be set to "0" not only by use of the applicable instruction, but

_______

by entering a falling edge in the NMI terminal or by resetting. Also, if "1" is set in the positive and negative

phases concurrent L output disable function enable bit (bit 4 at 0348

) causes one of the pairs of U

___

phase and U phase, V phase and V phase, and W phase and W phase concurrently go to "L", as a result,

the port becomes the state of set by port direction register.

Mitsubishi microcomputers

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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

Timers' functions for three-phase motor control

100

Timer B2

(Timer mode)

Overflow

Interrupt occurrence

frequency set counter

Interrupt request bit

U(P8

)

U(P8

)

V(P7

)

V(P7

)

W(P7

)

W(P7

)

NMI

RESET

For short circuit

prevention

INV03

INV05

Diagram for switching to P8

, P8

, and to P7

- P7

is not shown.

INV04

Timer A4 counter

(One-shot timer mode)

Trigger

Timer A4

Reload

Timer A4-1

Timer A1 counter

Trigger

Timer A1

Reload

Timer A1-1

Timer A2 counter

Trigger

Timer A2

Reload

Timer A2-1

INV0

INV11

Dead time timer setting (8)

INV00

INV01

INV11

DU0

DU1

DUB0

DUB1

U phase output control circuit

U phase output signal

V phase output

control circuit

To be set to "0" when timer A4 stops

INV11

To be set to "0" when timer A1 stops

INV11

To be set to "0" when timer A2 stops

W phase output

control circuit

V phase output signal

W phase output signal

V phase output signal

W phase output signal

Signal to be

written to B2

Trigger signal for

timer Ai start

Trigger signal

for transfer

INV10

Circuit for interrupt occurrence

frequency set counter

Bit 0 at 034B

Bit 0 at 034A

Three-phase output

shift register

(U phase)

Control signal for timer A4 reload

INV12

1/2

n = 1 to 15

Reload register

n = 1 to 255

Dead time timer setting (8)

n = 1 to 255

Dead time timer setting (8)

n = 1 to 255

Trigger

INV06

Trigger

INV06

(Note)

Note: To use three-phase output mode, write "1" to INV

Figure 1.15.5. Block diagram for three-phase PWM output mode

Mitsubishi microcomputers

M16C / 62A Group

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

Timers' functions for three-phase motor control

101

Triangular wave modulation

To generate a PWM waveform of triangular wave modulation, set "0" in the modulation mode select bit

(bit 6 at 0348

). Also, set "1" in the timers A4-1, A1-1, A2-1 control bit (bit 1 at 0349

). In this mode, each

of timers A4, A1, and A2 has two timer registers, and alternately reloads the timer register's content to the

counter every time timer B2 counter's content becomes 0000

. If "0" is set to the effective interrupt

output specification bit (bit 1 at 0348

), the frequency of interrupt requests that occur every time the timer

B2 counter's value becomes 0000

can be set by use of the timer B2 counter (034D

) for setting the

frequency of interrupt occurrences. The frequency of occurrences is given by (setting; setting

0).

Setting "1" in the effective interrupt output specification bit (bit 1 at 0348

) provides the means to choose

which value of the timer A1 reload control signal to use, "0" or "1", to cause timer B2's interrupt request to

occur. To make this selection, use the effective interrupt output polarity selection bit (bit 0 at 0348

An example of U phase waveform is shown in Figure 1.15.6, and the description of waveform output

workings is given below. Set "1" in DU0 (bit 0 at 034A

). And set "0" in DUB0 (bit 1 at 034A

). In

addition, set "0" in DU1 (bit 0 at 034B

) and set "1" in DUB1 (bit 1 at 034B

). Also, set "0" in the effective

interrupt output specification bit (bit 1 at 0348

) to set a value in the timer B2 interrupt occurrence

frequency set counter. By this setting, a timer B2 interrupt occurs when the timer B2 counter's content

becomes 0000

as many as (setting) times. Furthermore, set "1" in the effective interrupt output specifi-

cation bit (bit 1 at 0348

), set "0" in the effective interrupt output polarity select bit (bit 0 at 0348

) and set

"1" in the interrupt occurrence frequency set counter (034D

). These settings cause a timer B2 interrupt

to occur every other interval when the U phase output goes to "H".

When the timer B2 counter's content becomes 0000

, timer A4 starts outputting one-shot pulses. In this

instance, the content of DU1 (bit 0 at 034B

) and that of DU0 (bit 0 at 034A

) are set in the three-phase

output shift register (U phase), the content of DUB1 (bit 1 at 034B

) and that of DUB0 (bit 1 at 034A

)

___

are set in the three-phase output shift register (U phase). After triangular wave modulation mode is se-

lected, however, no setting is made in the shift register even though the timer B2 counter's content

becomes 0000

___

The value of DU0 and that of DUB0 are output to the U terminal (P8

) and to the U terminal (P8

)

respectively. When the timer A4 counter counts the value written to timer A4 (038F

, 038E

) and when

timer A4 finishes outputting one-shot pulses, the three-phase shift register's content is shifted one posi-

___

tion, and the value of DU1 and that of DUB1 are output to the U phase output signal and to U phase output

signal respectively. At this time, one-shot pulses are output from the timer for setting dead time used for

___

setting the time over which the "L" level of the U phase waveform does not lap over the "L" level of the U

phase waveform, which has the opposite phase of the former. The U phase waveform output that started

from the "H" level keeps its level until the timer for setting dead time finishes outputting one-shot pulses

even though the three-phase output shift register's content changes from "1" to "0" by the effect of the

one-shot pulses. When the timer for setting dead time finishes outputting one-shot pulses, "0" already

shifted in the three-phase shift register goes effective, and the U phase waveform changes to the "L"

level. When the timer B2 counter's content becomes 0000

, the timer A4 counter starts counting the

value written to timer A4-1 (0347

, 0346

), and starts outputting one-shot pulses. When timer A4 fin-

ishes outputting one-shot pulses, the three-phase shift register's content is shifted one position, but if the

three-phase output shift register's content changes from "0" to "1" as a result of the shift, the output level

changes from "L" to "H" without waiting for the timer for setting dead time to finish outputting one-shot

pulses. A U phase waveform is generated by these workings repeatedly. With the exception that the

three-phase output shift register on the U phase side is used, the workings in generating a U phase

waveform, which has the opposite phase of the U phase waveform, are the same as in generating a U

Mitsubishi microcomputers

M16C / 62A Group

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

Timers' functions for three-phase motor control

102

Timer A4 output

Trigger signal for
timer Ai start
(timer B2 overflow
signal)

Timer B2

U phase

Dead time

A carrier wave of triangular waveform

Carrier wave

Signal wave

Timer B2 interrupt occurs
Rewriting timer A4 and timer A4-1.
Possible to set the number of overflows to generate an
interrupt by use of the interrupt occurrences frequency
set circuit

U phase
output signal

Note: Set to triangular wave modulation mode and to three-phase mode 1.

The three-phase
shift register
shifts in
synchronization
with the falling
edge of the timer
A4 output.

U phase

U phase
output signal

Control signal for
timer A4 reload

Figure 1.15.6. Timing chart of operation (1)

phase waveform. In this way, a waveform can be picked up from the applicable terminal in a manner in

which the "L" level of the U phase waveform doesn't lap over that of the U phase waveform, which has the

opposite phase of the U phase waveform. The width of the "L" level too can be adjusted by varying the

___

values of timer B2, timer A4, and timer A4-1. In dealing with the V and W phases, and V and W phases,

the latter are of opposite phase of the former, have the corresponding timers work similarly to dealing with

___

the U and U phases to generate an intended waveform.

Mitsubishi microcomputers

M16C / 62A Group

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

Timers' functions for three-phase motor control

104

Sawtooth modulation

To generate a PWM waveform of sawtooth wave modulation, set "1" in the modulation mode select bit (bit

6 at 0348

). Also, set "0" in the timers A4-1, A1-1, and A2-1 control bit (bit 1 at 0349

). In this mode, the

timer registers of timers A4, A1, and A2 comprise conventional timers A4, A1, and A2 alone, and reload

the corresponding timer register's content to the counter every time the timer B2 counter's content be-

comes 0000

. The effective interrupt output specification bit (bit 1 at 0348

) and the effective interrupt

output polarity select bit (bit 0 at 0348

) go nullified.

An example of U phase waveform is shown in Figure 1.15.8, and the description of waveform output

workings is given below. Set "1" in DU0 (bit 0 at 034A

), and set "0" in DUB0 (bit 1 at 034A

). In addition,

set "0" in DU1 (bit 0 at 034A

) and set "1" in DUB1 (bit 1 at 034A

When the timber B2 counter's content becomes 0000

, timer B2 generates an interrupt, and timer A4

starts outputting one-shot pulses at the same time. In this instance, the contents of the three-phase buffer

registers DU1 and DU0 are set in the three-phase output shift register (U phase), and the contents of

___

DUB1 and DUB0 are set in the three-phase output shift register (U phase). After this, the three-phase

buffer register's content is set in the three-phase shift register every time the timer B2 counter's content

becomes 0000

___

The value of DU0 and that of DUB0 are output to the U terminal (P8

) and to the U terminal (P8

)

respectively. When the timer A4 counter counts the value written to timer A4 (038F

, 038E

) and when

timer A4 finishes outputting one-shot pulses, the three-phase output shift register's content is shifted one

___

position, and the value of DU1 and that of DUB1 are output to the U phase output signal and to the U

output signal respectively. At this time, one-shot pulses are output from the timer for setting dead time

used for setting the time over which the "L" level of the U phase waveform doesn't lap over the "L" level of

___

the U phase waveform, which has the opposite phase of the former. The U phase waveform output that

started from the "H" level keeps its level until the timer for setting dead time finishes outputting one-shot

pulses even though the three-phase output shift register's content changes from "1" to "0 "by the effect of

the one-shot pulses. When the timer for setting dead time finishes outputting one-shot pulses, 0 already

shifted in the three-phase shift register goes effective, and the U phase waveform changes to the "L"

level. When the timer B2 counter's content becomes 0000

, the contents of the three-phase buffer

registers DU1 and DU0 are set in the three-phase output shift register (U phase), and the contents of

___

DUB1 and DUB0 are set in the three-phase output shift register (U phase) again.

A U phase waveform is generated by these workings repeatedly. With the exception that the three-phase

___

output shift register on the U phase side is used, the workings in generating a U phase waveform, which

has the opposite phase of the U phase waveform, are the same as in generating a U phase waveform. In

this way, a waveform can be picked up from the applicable terminal in a manner in which the "L" level of

___

the U phase waveform doesn't lap over that of the U phase waveform, which has the opposite phase of

the U phase waveform. The width of the "L" level too can be adjusted by varying the values of timer B2

___

and timer A4. In dealing with the V and W phases, and V and W phases, the latter are of opposite phase

___

of the former, have the corresponding timers work similarly to dealing with the U and U phases to gener-

ate an intended waveform.

___

Setting "1" both in DUB0 and in DUB1 provides a means to output the U phase alone and to fix the U

phase output to "H" as shown in Figure 1.15.9.

Mitsubishi microcomputers

M16C / 62A Group

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

Serial I/O

107

Serial I/O

Serial I/O is configured as five channels: UART0, UART1, UART2, S I/O3 and S I/O4.

UART0 to 2

UART0, UART1 and UART2 each have an exclusive timer to generate a transfer clock, so they operate

independently of each other.

Figure 1.16.1 shows the block diagram of UART0, UART1 and UART2. Figures 1.16.2 and 1.16.3 show

the block diagram of the transmit/receive unit.

UARTi (i = 0 to 2) has two operation modes: a clock synchronous serial I/O mode and a clock asynchronous

serial I/O mode (UART mode). The contents of the serial I/O mode select bits (bits 0 to 2 at addresses

03A0

, 03A8

and 0378

) determine whether UARTi is used as a clock synchronous serial I/O or as a

UART. Although a few functions are different, UART0, UART1 and UART2 have almost the same functions.

UART2, in particular, is used for the SIM interface with some extra settings added in clock-asynchronous

serial I/O mode (Note). It also has the bus collision detection function that generates an interrupt request if

the TxD pin and the RxD pin are different in level.

Table 1.16.1 shows the comparison of functions of UART0 through UART2, and Figures 1.16.4 to 1.16.9

show the registers related to UARTi.

Note: SIM : Subscriber Identity Module

Note 1: Only when clock synchronous serial I/O mode.
Note 2: Only when clock synchronous serial I/O mode and 8-bit UART mode.
Note 3: Only when UART mode.
Note 4: Using for SIM interface.

UART0

UART1

UART2

Function

CLK polarity selection

Continuous receive mode selection

LSB first / MSB first selection

Impossible

Transfer clock output from multiple
pins selection

Impossible

Serial data logic switch

Impossible

Sleep mode selection

Impossible

TxD, RxD I/O polarity switch

Impossible

Possible

CMOS output

TxD, RxD port output format

CMOS output

N-channel open-drain
output

Impossible

Parity error signal output

Impossible

Bus collision detection

Impossible

Possible

(Note 1)

Possible

(Note 1)

Possible

(Note 1)

Possible

(Note 3)

Possible

(Note 1)

Possible

(Note 1)

Possible

(Note 1)

Possible

(Note 1)

Possible

(Note 3)

Possible

(Note 1)

Possible

(Note 2)

Possible

(Note 1)

Possible

(Note 4)

Possible

(Note 4)

Table 1.16.1. Comparison of functions of UART0 through UART2

Mitsubishi microcomputers

M16C / 62A Group

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

Serial I/O

108

Figure 1.16.1. Block diagram of UARTi (i = 0 to 2)

n0 : Values set to UART0 bit rate generator (U0BRG)
n1 : Values set to UART1 bit rate generator (U1BRG)
n2 : Values set to UART2 bit rate generator (U2BRG)

RxD

Reception

control circuit

Transmission
control circuit

1 / (n

+1)

1/16

1/2

Bit rate generator

(address 0379

)

Clock synchronous type
(when internal clock is selected)

UART reception

Clock synchronous type

UART transmission

Clock synchronous type

(when internal clock is selected)

Clock synchronous type
(when external clock is
selected)

Receive
clock

Transmit
clock

CLK

CTS

/ RTS

Vcc

RTS

CTS

TxD

(UART2)

RxD polarity

reversing circuit

TxD

polarity

reversing

circuit

RxD

1 / (n

+1)

1/2

Bit rate generator

(address 03A1

)

Clock synchronous type
(when internal clock is selected)

UART reception

Clock synchronous type

UART transmission

Clock synchronous type

Clock synchronous type
(when internal clock is selected)

Clock synchronous type
(when external clock is
selected)

Receive
clock

Transmit
clock

CLK

Clock source selection

CTS

/ RTS

Reception

control circuit

Transmission
control circuit

Internal

External

Vcc

RTS

CTS

TxD

Transmit/

receive

unit

RxD

1 / (n

+1)

1/16

1/2

Bit rate generator

(address 03A9

)

Clock synchronous type
(when internal clock is selected)

UART reception

Clock synchronous type

UART transmission

Clock synchronous type

(when internal clock is selected)

Clock synchronous type
(when external clock is
selected)

Receive
clock

Transmit
clock

CLK

Clock source selection

Reception

control circuit

Transmission
control circuit

Internal

External

RTS

CTS

TxD

(UART1)

(UART0)

CLK

polarity

reversing

circuit

CLK

polarity

reversing

circuit

CTS/RTS disabled

Clock output pin
select switch

CTS

/ RTS

CLKS

CTS/RTS disabled

CTS/RTS selected

CTS/RTS disabled

CTS/RTS selected

CTS/RTS disabled

CTS/RTS
selected

CLK

polarity

reversing

circuit

Internal

External

Clock source selection

Transmit/

receive

unit

Transmit/

receive

unit

1/16

Mitsubishi microcomputers

M16C / 62A Group

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

Serial I/O

110

PAR

2SP

1SP

UART

UART
(7 bits)
UART
(8 bits)

UART(7 bits)

UART
(9 bits)

Clock
synchronous
type

Clock
synchronous type

Data bus low-order bits

TxD2

UART2 transmit register

PAR
disabled

PAR
enabled

UART2 transmit
buffer register

UART
(8 bits)
UART
(9 bits)

Clock
synchronous type

UART2 receive
buffer register

UART2 receive register

2SP

1SP

UART
(7 bits)
UART
(8 bits)

UART(7 bits)

UART
(9 bits)

Clock
synchronous type

RxD2

UART
(8 bits)
UART
(9 bits)

Address 037E

Address 037F

Address 037A

Address 037B

Data bus high-order bits

PAR

"0"

Reverse

No reverse

Error signal

output circuit

RxD data

reverse circuit

Error signal output
enable

Error signal output
disable

Reverse

No reverse

Logic reverse circuit + MSB/LSB conversion circuit

PAR
enabled

PAR
disabled

UART

Clock
synchronous
type

TxD data

reverse circuit

SP: Stop bit
PAR: Parity bit

Figure 1.16.3. Block diagram of UART2 transmit/receive unit

Mitsubishi microcomputers

M16C / 62A Group

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

Serial I/O

111

Figure 1.16.4. Serial I/O-related registers (1)

UARTi bit rate generator (Note 1, 2)

Symbol

Address

When reset

U0BRG

03A1

Indeterminate

U1BRG

03A9

Indeterminate

U2BRG

0379

Indeterminate

Function

Assuming that set value = n, BRGi divides the count source by
n + 1

to FF

Values that can be set

(b15)

(b8)

UARTi transmit buffer register (Note)

Function

Transmit data

Nothing is assigned.
In an attempt to write to these bits, write "0". The value, if read, turns out to be indeterminate.

Symbol

Address

When reset

U0TB

03A3

, 03A2

Indeterminate

U1TB

03AB

, 03AA

Indeterminate

U2TB

037B

, 037A

Indeterminate

(b15)

Symbol

Address

When reset

U0RB

03A7

, 03A6

Indeterminate

U1RB

03AF

, 03AE

Indeterminate

U2RB

037F

, 037E

Indeterminate

(b8)

UARTi receive buffer register

Function

(During UART mode)

Function

(During clock synchronous

serial I/O mode)

Bit name

Bit

symbol

0 : No framing error
1 : Framing error found

0 : No parity error
1 : Parity error found

0 : No error
1 : Error found

Note 1: Bits 15 through 12 are set to "0" when the serial I/O mode select bit (bits 2 to 0 at addresses 03A0

03A8

and 0378

) are set to "000

" or the receive enable bit is set to "0".

(Bit 15 is set to "0" when bits 14 to 12 all are set to "0".) Bits 14 and 13 are also set to "0" when the
lower byte of the UARTi receive buffer register (addresses 03A6

, 03AE

and 037E

) is read out.

Note 2: Arbitration lost detecting flag is allocated to U2RB and noting but "0" may be written. Nothing is

assigned in bit 11 of U0RB and U1RB. When write, set "0". The value, if read, turns out to be "0".

Invalid

OER

FER

PER

SUM

Overrun error flag (Note 1)

Framing error flag (Note 1)

Parity error flag (Note 1)

Error sum flag (Note 1)

0 : No overrun error
1 : Overrun error found

Nothing is assigned.
In an attempt to write to these bits, write "0". The value, if read, turns out to be "0".

Receive data

ABT

Arbitration lost detecting
flag (Note 2)

Invalid

0 : Not detected
1 : Detected

Note 1: Write a value to this register while transmit/receive halts.
Note 2: Use MOV instruction to write to this register.

Note: Use MOV instruction to write to this register.

Mitsubishi microcomputers

M16C / 62A Group

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

Serial I/O

112

UARTi transmit/receive mode register

Symbol

Address

When reset

UiMR(i=0,1)

03A0

, 03A8

Bit name

Bit

symbol

Must be fixed to 001

0 0 0 : Serial I/O invalid
0 1 0 : Must not be set.
0 1 1 : Must not be set.
1 1 1 : Must not be set.

b2 b1 b0

CKDIR

SMD1

SMD0

Serial I/O mode select bit

SMD2

Internal/external clock
select bit

STPS

PRY

PRYE

SLEP

Parity enable bit

0 : Internal clock
1 : External clock (Note)

Stop bit length select bit

Odd/even parity select bit

Sleep select bit

0 : One stop bit
1 : Two stop bits

0 : Parity disabled
1 : Parity enabled

0 : Sleep mode deselected
1 : Sleep mode selected

1 0 0 : Transfer data 7 bits long
1 0 1 : Transfer data 8 bits long
1 1 0 : Transfer data 9 bits long
0 0 0 : Serial I/O invalid
0 1 0 : Must not be set.
0 1 1 : Must not be set.
1 1 1 : Must not be set.

b2 b1 b0

0 : Internal clock
1 : External clock (Note)

Invalid

Valid when bit 6 = "1"
0 : Odd parity
1 : Even parity

Invalid

Must always be "0"

Function

(During UART mode)

Function

(During clock synchronous

serial I/O mode)

UART2 transmit/receive mode register

Symbol

Address

When reset

U2MR

0378

Bit name

Bit

symbol

Must be fixed to 001

0 0 0 : Serial I/O invalid
0 1 0 : (Note 1)
0 1 1 : Must not be set.
1 1 1 : Must not be set.

b2 b1 b0

CKDIR

SMD1

SMD0

Serial I/O mode select bit

SMD2

Internal/external clock
select bit

STPS

PRY

PRYE

IOPOL

Parity enable bit

0 : Internal clock
1 : External clock (Note 2)

Stop bit length select bit

Odd/even parity select bit

TxD, RxD I/O polarity
reverse bit

0 : One stop bit
1 : Two stop bits

0 : Parity disabled
1 : Parity enabled

0 : No reverse
1 : Reverse

Usually set to "0"

b2 b1 b0

Invalid

Valid when bit 6 = "1"
0 : Odd parity
1 : Even parity

Invalid

0 : No reverse
1 : Reverse

Usually set to "0"

Function

(During UART mode)

Function

(During clock synchronous

serial I/O mode)

Note 1: Bit 2 to bit 0 are set to "010

" when I

C mode is used.

Note 2: Set the corresponding port direction register to "0".

Must always be fixed to "0"

Note : Set the corresponding port direction register to "0".

Figure 1.16.5. Serial I/O-related registers (2)

Mitsubishi microcomputers

M16C / 62A Group

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

Serial I/O

113

UARTi transmit/receive control register 0

Symbol

Address

When reset

UiC0(i=0,1)

03A4

, 03AC

Function

(During UART mode)

Function

(During clock synchronous

serial I/O mode)

TXEPT

CLK1

CLK0

CRS

CRD

NCH

CKPOL

BRG count source
select bit

Transmit register empty
flag

0 : Transmit data is output at

falling edge of transfer clock
and receive data is input at
rising edge

1 : Transmit data is output at

rising edge of transfer clock
and receive data is input at
falling edge

CLK polarity select bit

CTS/RTS function
select bit

CTS/RTS disable bit

Data output select bit

0 0 : f

is selected

0 1 : f

is selected

1 0 : f

is selected

1 1 : Must not be set.

b1 b0

0 : LSB first
1 : MSB first

0 : Data present in transmit

1 : No data present in transmit

0 : CTS/RTS function enabled
1 : CTS/RTS function disabled

(P6

and P6

function as

programmable I/O port)

0 : T

Di pin is CMOS output

1 : T

Di pin is N-channel

open-drain output

UFORM Transfer format select bit

0 0 : f

is selected

0 1 : f

is selected

1 0 : f

is selected

1 1 : Must not be set.

b1 b0

Valid when bit 4 = "0"

0 : CTS function is selected (Note 1)
1 : RTS function is selected (Note 2)

Valid when bit 4 = "0"
0 : CTS function is selected (Note 1)
1 : RTS function is selected (Note 2)

0 : Data present in transmit register

(during transmission)

1 : No data present in transmit

0: T

Di pin is CMOS output

1: T

Di pin is N-channel

open-drain output

Must always be "0"

Bit name

Bit

symbol

Must always be "0"

Note 1: Set the corresponding port direction register to "0".
Note 2: The settings of the corresponding port register and port direction register are invalid.

0 : CTS/RTS function enabled
1 : CTS/RTS function disabled

(P6

and P6

function as

programmable I/O port)

UART2 transmit/receive control register 0

Symbol

Address

When reset

U2C0

037C

Function

(During UART mode)

Function

(During clock synchronous

serial I/O mode)

TXEPT

CLK1

CLK0

CRS

CRD

CKPOL

BRG count source
select bit

Transmit register empty
flag

0 : Transmit data is output at

falling edge of transfer clock
and receive data is input at
rising edge

1 : Transmit data is output at

rising edge of transfer clock
and receive data is input at
falling edge

CLK polarity select bit

CTS/RTS function
select bit

CTS/RTS disable bit

0 0 : f

is selected

0 1 : f

is selected

1 0 : f

is selected

1 1 : Must not be set.

b1 b0

0 : LSB first
1 : MSB first

0 : Data present in transmit

1 : No data present in transmit

0 : CTS/RTS function enabled
1 : CTS/RTS function disabled

(P7

functions

programmable I/O port)

0 : TXDi pin is CMOS output
1 : TXDi pin is N-channel

open-drain output

UFORM Transfer format select bit

(Note 3)

0 0 : f

is selected

0 1 : f

is selected

1 0 : f

is selected

1 1 : Must not be set.

b1 b0

Valid when bit 4 = "0"

0 : CTS function is selected (Note 1)
1 : RTS function is selected (Note 2)

Valid when bit 4 = "0"
0 : CTS function is selected (Note 1)
1 : RTS function is selected (Note 2)

0 : Data present in transmit register

(during transmission)

1 : No data present in transmit

0: TXDi pin is CMOS output
1: TXDi pin is N-channel

open-drain output

Must always be "0"

Bit name

Bit

symbol

Note 1: Set the corresponding port direction register to "0".
Note 2: The settings of the corresponding port register and port direction register are invalid.
Note 3: Only clock synchronous serial I/O mode and 8-bit UART mode are valid.

0 : CTS/RTS function enabled
1 : CTS/RTS function disabled

(P7

functions programmable

I/O port)

Nothing is assigned.

In an attempt to write to this bit, write "0". The value, if read, turns out to be "0".

0 : LSB first
1 : MSB first

Figure 1.16.6. Serial I/O-related registers (3)

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Figure 1.16.7. Serial I/O-related registers (4)

UARTi transmit/receive control register 1

Symbol

Address

When reset

UiC1(i=0,1)

03A5

03AD

Bit name

Bit

symbol

Function

(During UART mode)

Function

(During clock synchronous

serial I/O mode)

Transmit enable bit

Receive enable bit

Receive complete flag

Transmit buffer
empty flag

0 : Transmission disabled
1 : Transmission enabled

0 : Data present in

transmit buffer register

1 : No data present in

transmit buffer register

0 : Reception disabled
1 : Reception enabled

0 : Transmission disabled
1 : Transmission enabled

0 : Data present in

transmit buffer register

1 : No data present in

transmit buffer register

0 : Reception disabled
1 : Reception enabled

0 : No data present in

receive buffer register

1 : Data present in

receive buffer register

0 : No data present in

receive buffer register

1 : Data present in

receive buffer register

Nothing is assigned.
In an attempt to write to these bits, write "0". The value, if read, turns out to be "0".

UART2 transmit/receive control register 1

Symbol

Address

When reset

U2C1

037D

Bit name

Bit

symbol

Function

(During UART mode)

Function

(During clock synchronous

serial I/O mode)

Transmit enable bit

Receive enable bit

Receive complete flag

Transmit buffer
empty flag

0 : Transmission disabled
1 : Transmission enabled

0 : Data present in

transmit buffer register

1 : No data present in

transmit buffer register

0 : Reception disabled
1 : Reception enabled

0 : Transmission disabled
1 : Transmission enabled

0 : Data present in

transmit buffer register

1 : No data present in

transmit buffer register

0 : Reception disabled
1 : Reception enabled

0 : No data present in

receive buffer register

1 : Data present in

receive buffer register

0 : No data present in

receive buffer register

1 : Data present in

receive buffer register

U2IRS

UART2 transmit interrupt
cause select bit

0 : Transmit buffer empty

(TI = 1)

1 : Transmit is completed

(TXEPT = 1)

0 : Transmit buffer empty

(TI = 1)

1 : Transmit is completed

(TXEPT = 1)

U2RRM UART2 continuous

receive mode enable bit

0 : Continuous receive

mode disabled

1 : Continuous receive

mode enabled

Must always be "0"

Data logic select bit

0 : No reverse
1 : Reverse

U2LCH

U2ERE Error signal output

enable bit

Must be fixed to "0"

0 : Output disabled
1 : Output enabled

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Note: When using multiple pins to output the transfer clock, the following requirements must be met:

· UART1 internal/external clock select bit (bit 3 at address 03A8

) = "0".

UART transmit/receive control register 2

Symbol

Address

When reset

UCON

03B0

X0000000

Bit

name

Bit

symbol

Function

(During UART mode)

Function

(During clock synchronous

serial I/O mode)

CLKMD0

CLKMD1

Reserved bit

UART0 transmit
interrupt cause select bit

UART0 continuous
receive mode enable bit

0 : Continuous receive

mode disabled

1 : Continuous receive

mode enable

UART1 continuous
receive mode enable bit

CLK/CLKS select bit 0

UART1 transmit
interrupt cause select bit

0 :

Transmit buffer empty (Tl = 1)

1 : Transmission completed

(TXEPT = 1)

0 :

Transmit buffer empty (Tl = 1)

1 : Transmission completed

(TXEPT = 1)

0 : Normal mode

(CLK output is CLK1 only)

1 : Transfer clock output

from multiple pins
function selected

0 : Continuous receive

mode disabled

1 : Continuous receive

mode enabled

Nothing is assigned.
In an attempt to write to this bit, write "0". The value, if read, turns out to be indeterminate.

0 : Transmit buffer empty (Tl = 1)
1 : Transmission completed

(TXEPT = 1)

0 : Transmit buffer empty (Tl = 1)
1 : Transmission completed

(TXEPT = 1)

Must always be "0"

U0IRS

U1IRS

U0RRM

U1RRM

Invalid

CLK/CLKS select
bit 1 (Note)

Valid when bit 5 = "1"
0 : Clock output to CLK1
1 : Clock output to CLKS1

UART2 special mode register

Symbol

Address

When reset

U2SMR

0377

b7 b6

b1 b0

Bit

name

Bit

symbol

Function

(During UART mode)

Function

(During clock synchronous

serial I/O mode)

ABSCS

ACSE

SSS

C mode select bit

Bus busy flag

0 : STOP condition detected
1 : START condition detected

SCLL sync output
enable bit

Bus collision detect
sampling
clock select bit

Arbitration lost detecting
flag control bit

0 : Normal mode
1 : I

C mode

0 : Update per bit
1 : Update per byte

IICM

ABC

BBS

LSYN

0 : Ordinary
1 : Falling edge of R

0 : Disabled
1 : Enabled

Transmit start condition
select bit

Must always be "0"

0 : Rising edge of transfer

clock

1 : Underflow signal of timer A0

Auto clear function
select bit of transmit
enable bit

0 : No auto clear function
1 : Auto clear at occurrence of

bus collision

Must always be "0"

Note 1: Nothing but "0" may be written.
Note 2: When not in I

C mode, do not set this bit by writing a "1". During normal mode, fix it to "0". When this

bit = "0", UART2 special mode register 3 (U2SMR3 at address 0375

) bits 7 to 5 (DL2 to DL0 = SDA

digital delay setup bits) are initialized to "000", with the analog delay circuit selected. Also, when SDDS
= "0", the U2SMR3 register cannot be read or written to.

Note 3: When analog delay is selected, only the analog delay value is effective; when digital delay is selected,

only the digital delay value is effective.

(Note1)

SDDS

SDA digital delay select
bit (Note 2, Note 3)

Must always be "0"

0 : Analog delay output
is selected
1 : Digital delay output
is selected
(must always be "0" when
not using I C mode)

Must always be set to

"0"

Must always be "0"

Figure 1.16.8. Serial I/O-related registers (5)

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Figure 1.16.9. Serial I/O-related registers (6)

UART2 special mode register 2 (I C bus exclusive use register)

Symbol

Address

When reset

U2SMR2

0376

b6 b5

Bit name

Bit

symbol

Function

(I2C bus exclusive use)

STAC

SWC2

SDHI

I C mode select bit 2

SCL wait output bit

0 : Disabled
1 : Enabled

SDA output stop bit

UART2 initialization bit

Clock-synchronous bit

Refer to Table 1.16.11

0 : Disabled
1 : Enabled

IICM2

CSC

SWC

ALS

0 : Disabled
1 : Enabled

SDA output disable bit

SCL wait output bit 2

0: Enabled
1: Disabled (high impedance)

0 : Disabled
1 : Enabled

0: UART2 clock
1: 0 output

SHTC

Start/stop condition
control bit

Set this bit to "1" in I

C mode

(refer to Table 1.16.12)

UART2 special mode register 3 (I C bus exclusive use register)

Symbol

Address

When reset

U2SMR3

0375

Indeterminate

(However, when SDDS = "1", the initial value is "00

b6 b5

Bit name

Bit

symbol

Function

(I C bus exclusive use register)

DL2

SDA digital delay setup
bit
(Note 1, Note 2, Note 3,
Note 4)

DL0

DL1

0 0 0 : Analog delay is selected
0 0 1 : 1 to 2 cycle(s) of 1/f(X

)

0 1 0 : 2 to 3 cycles of 1/f(X

)

0 1 1 : 3 to 4 cycles of 1/f(X

)

1 0 0 : 4 to 5 cycles of 1/f(X

)

1 0 1 : 5 to 6 cycles of 1/f(X

)

1 1 0 : 6 to 7 cycles of 1/f(X

)

1 1 1 : 7 to 8 cycles of 1/f(X

)

Nothing is assigned.
In an attempt to write to these bits, write "0". The value, if read, turns out to be
indeterminate. However, when SDDS = "1", the value "0" is read out (Note 1)

b7 b6 b5

Note 1: This bit can be read or written to when UART2 special mode register (U2SMR at address 0377

) bit

7 (SDDS: SDA digital delay select bit) = "1". When the initial value of UART2 special mode register 3
(U2SMR3) is read after setting SDDS = "1", the value is "00

". When writing to UART2 special mode

register 3 (U2SMR3) after setting SDDS = "1", be sure to write 0's to bits 04. When SDDS = "0",
this register cannot be written to; when read, the value is indeterminate.

Note 2: These bits are initialized to "000" when SDDS = "0", with the analog delay circuit selected. After a reset,

these bits are set to "000", with the analog delay circuit selected. However, because these bits can be
read only when SDDS = "1", the value read from these bits when SDDS = "0" is indeterminate.

Note 3: When analog delay is selected, only the analog delay value is effective; when digital delay is selected,

only the digital delay value is effective.

Note 4: The amount of delay varies with the load on SCL and SDA pins. Also, when using an external clock, the

amount of delay increases by about 100 ns, so be sure to take this into account when using the device.

Digital delay
is selected

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(1) Clock synchronous serial I/O mode

The clock synchronous serial I/O mode uses a transfer clock to transmit and receive data. Tables 1.16.2
and 1.16.3 list the specifications of the clock synchronous serial I/O mode. Figure 1.16.10 shows the

UARTi transmit/receive mode register.

Table 1.16.2. Specifications of clock synchronous serial I/O mode (1)

Item

Specification

Transfer data format

· Transfer data length: 8 bits

Transfer clock

· When internal clock is selected (bit 3 at addresses 03A0

, 03A8

, 0378

= "0") : fi/ 2(n+1)

(Note 1) fi = f

, f

· When external clock is selected (bit 3 at addresses 03A0

, 03A8

, 0378

= "1") : Input from CLKi pin

Transmission/reception control

_______

CTS

function,

RTS

function,

CTS

and

RTS

function invalid: selectable

Transmission start condition

· To start transmission, the following requirements must be met:

Transmit enable bit (bit 0 at addresses 03A5

, 03AD

, 037D

) = "1"

Transmit buffer empty flag (bit 1 at addresses 03A5

, 03AD

, 037D

) = "0"

_______

When CTS function selected, CTS input level = "L"

· Furthermore, if external clock is selected, the following requirements must also be met:

CLKi polarity select bit (bit 6 at addresses 03A4

, 03AC

, 037C

) = "0":

CLKi input level = "H"

CLKi polarity select bit (bit 6 at addresses 03A4

, 03AC

, 037C

) = "1":

CLKi input level = "L"

Reception start condition

· To start reception, the following requirements must be met:

Receive enable bit (bit 2 at addresses 03A5

, 03AD

, 037D

) = "1"

Transmit enable bit (bit 0 at addresses 03A5

, 03AD

, 037D

) = "1"

Transmit buffer empty flag (bit 1 at addresses 03A5

, 03AD

, 037D

) = "0"

· Furthermore, if external clock is selected, the following requirements must

also be met:

CLKi polarity select bit (bit 6 at addresses 03A4

, 03AC

, 037C

) = "0":

CLKi input level = "H"

CLKi polarity select bit (bit 6 at addresses 03A4

, 03AC

, 037C

) = "1":

CLKi input level = "L"

· When transmitting

Transmit interrupt cause select bit (bits 0, 1 at address 03B0

, bit 4 at

address 037D

) = "0": Interrupts requested when data transfer from UARTi

transfer buffer register to UARTi transmit register is completed

Transmit interrupt cause select bit (bits 0, 1 at address 03B0

, bit 4 at

address 037D

) = "1": Interrupts requested when data transmission from

UARTi transfer register is completed

· When receiving

Interrupts requested when data transfer from UARTi receive register to

UARTi receive buffer register is completed

Error detection

· Overrun error (Note 2)

This error occurs when the next data is ready before contents of UARTi

receive buffer register are read out

Interrupt request
generation timing

Note 1: "n" denotes the value 00

to FF

that is set to the UART bit rate generator.

Note 2: If an overrun error occurs, the UARTi receive buffer will have the next data written in. Note also that

the UARTi receive interrupt request bit does not change.

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Figure 1.16.10. UARTi transmit/receive mode register in clock synchronous serial I/O mode

Symbol

Address

When reset

UiMR(i=0,1)

03A0

, 03A8

CKDIR

UARTi transmit/receive mode registers

Internal/external clock
select bit

STPS

PRY

PRYE

SLEP

0 : Internal clock
1 : External clock (Note)

Bit name

Function

Bit symbol

0 (Must always be "0" in clock synchronous serial I/O mode)

0 1

SMD0

SMD1

SMD2

Serial I/O mode select bit

0 0 1 : Clock synchronous serial

I/O mode

b2 b1 b0

Invalid in clock synchronous serial I/O mode

Symbol

Address

When reset

U2MR

0378

CKDIR

UART2 transmit/receive mode register

Internal/external clock
select bit

STPS

PRY

PRYE

IOPOL

0 : Internal clock
1 : External clock (Note 2)

Bit name

Function

Bit symbol

0 1

SMD0

SMD1

SMD2

Serial I/O mode select bit

0 0 1 : Clock synchronous serial

I/O mode

b2 b1 b0

Invalid in clock synchronous serial I/O mode

TxD, RxD I/O polarity
reverse bit (Note 1)

0 : No reverse
1 : Reverse

Note 1: Usually set to "0".
Note 2: Set the corresponding port direction register to "0".

Note : Set the corresponding port direction register to "0".

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Table 1.16.4 lists the functions of the input/output pins during clock synchronous serial I/O mode. This

table shows the pin functions when the transfer clock output from multiple pins function is not selected.

Note that for a period from when the UARTi operation mode is selected to when transfer starts, the TxDi

pin outputs an "H". (If the N-channel open-drain is selected, this pin is in floating state.)

Table 1.16.4. Input/output pin functions in clock synchronous serial I/O mode

Pin name

Function

Method of selection

TxDi
(P6

, P6

, P7

)

Serial data output

Serial data input

Transfer clock output

Transfer clock input

Programmable I/O port

(Outputs dummy data when performing reception only)

RxDi
(P6

, P6

, P7

)

CLKi
(P6

, P6

, P7

)

Internal/external clock select bit (bit 3 at address 03A0

, 03A8

, 0378

) = "0"

Internal/external clock select bit (bit 3 at address 03A0

, 03A8

, 0378

) = "1"

Port P6

, P6

and P7

direction register (bits 1 and 5 at address 03EE

bit 2 at address 03EF

) = "0"

Port P6

, P6

and P7

direction register (bits 2 and 6 at address 03EE

bit 1 at address 03EF

)= "0"

(Can be used as an input port when performing transmission only)

CTS/RTS disable bit (bit 4 at address 03A4

, 03AC

, 037C

) ="0"

CTS/RTS function select bit (bit 2 at address 03A4

, 03AC

, 037C

) = "0"

Port P6

, P6

and P7

direction register (bits 0 and 4 at address 03EE

bit 3 at address 03EF

) = "0"

CTS/RTS disable bit (bit 4 at address 03A4

, 03AC

, 037C

16)

= "0"

CTS/RTS function select bit (bit 2 at address 03A4

, 03AC

, 037C

) = "1"

CTS/RTS disable bit (bit 4 at address 03A4

, 03AC

, 037C

) = "1"

CTS input

RTS output

CTSi/RTSi
(P6

, P6

, P7

)

(when transfer clock output from multiple pins is not selected)

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Figure 1.16.11. Typical transmit/receive timings in clock synchronous serial I/O mode

· Example of transmit timing (when internal clock is selected)

CLK

Stopped pulsing because transfer enable bit = "0"

Data is set in UARTi transmit buffer register

Tc = TCLK = 2(n + 1) / fi

fi: frequency of BRGi count source (f

, f

)

n: value set to BRGi

Transfer clock

Transmit enable
bit (TE)

Transmit buffer
empty flag (Tl)

CLKi

TxDi

Transmit
register empty
flag (TXEPT)

"H"

"L"

"0"

"1"

"0"

"1"

"0"

"1"

CTSi

The above timing applies to the following settings:
· Internal clock is selected.
· CTS function is selected.
· CLK polarity select bit = "0".
· Transmit interrupt cause select bit = "0".

Transmit interrupt
request bit (IR)

"0"

"1"

Stopped pulsing because CTS = "H"

Transferred from UARTi transmit buffer register to UARTi transmit register

Shown in ( ) are bit symbols.

Cleared to "0" when interrupt request is accepted, or cleared by software

1 / f

EXT

Dummy data is set in UARTi transmit buffer register

Transmit enable
bit (TE)

Transmit buffer
empty flag (Tl)

CLKi

RxDi

Receive complete
flag (Rl)

RTSi

"H"

"L"

"0"

"1"

"0"

"1"

"0"

"1"

Receive enable
bit (RE)

"0"

"1"

Receive data is taken in

Transferred from UARTi transmit buffer register to UARTi transmit register

Read out from UARTi receive buffer register

The above timing applies to the following settings:
· External clock is selected.
· RTS function is selected.
· CLK polarity select bit = "0".

EXT

: frequency of external clock

Transferred from UARTi receive register

to UARTi receive buffer register

Receive interrupt
request bit (IR)

"0"

"1"

Shown in ( ) are bit symbols.

Meet the following conditions are met when the CLK
input before data reception = "H"
· Transmit enable bit "1"
· Receive enable bit "1"
· Dummy data write to UARTi transmit buffer register

Cleared to "0" when interrupt request is accepted, or cleared by software

· Example of receive timing (when external clock is selected)

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(a) Polarity select function

As shown in Figure 1.16.12, the CLK polarity select bit (bit 6 at addresses 03A4

, 03AC

, 037C

)

allows selection of the polarity of the transfer clock.

· When CLK polarity select bit = "1"

Note 2: The CLKi pin level when not

transferring data is "L".

CLK

· When CLK polarity select bit = "0"

Note 1: The CLKi pin level when not

transferring data is "H".

CLK

Figure 1.16.12. Polarity of transfer clock

(b) LSB first/MSB first select function

As shown in Figure 1.16.13, when the transfer format select bit (bit 7 at addresses 03A4

, 03AC

037C

) = "0", the transfer format is "LSB first"; when the bit = "1", the transfer format is "MSB first".

Figure 1.16.13. Transfer format

LSB first

· When transfer format select bit = "0"

CLK

· When transfer format select bit = "1"

CLK

MSB first

Note: This applies when the CLK polarity select bit = "0".

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(c) Transfer clock output from multiple pins function (UART1)

This function allows the setting two transfer clock output pins and choosing one of the two to output a

clock by using the CLK and CLKS select bit (bits 4 and 5 at address 03B0

). (See Figure 1.16.14.)

The multiple pins function is valid only when the internal clock is selected for UART1.

Figure 1.16.14. The transfer clock output from the multiple pins function usage

Microcomputer

(P6

)

CLKS

(P6

)

CLK

(P6

)

CLK

Note: This applies when the internal clock is selected and transmission

is performed only in clock synchronous serial I/O mode.

(d) Continuous receive mode

If the continuous receive mode enable bit (bits 2 and 3 at address 03B0

, bit 5 at address 037D

) is

set to "1", the unit is placed in continuous receive mode. In this mode, when the receive buffer register

is read out, the unit simultaneously goes to a receive enable state without having to set dummy data to

the transmit buffer register back again.

(e) Serial data logic switch function (UART2)

When the data logic select bit (bit6 at address 037D

) = "1", and writing to transmit buffer register or

reading from receive buffer register, data is reversed. Figure 1.16.15 shows the example of serial data

logic switch timing.

Figure 1.16.15. Serial data logic switch timing

Transfer clock

TxD

(no reverse)

TxD

(reverse)

"H"

"L"

"H"

"L"

"H"

"L"

·When LSB first

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Item

Specification

Transfer data format

· Character bit (transfer data): 7 bits, 8 bits, or 9 bits as selected

· Start bit: 1 bit

· Parity bit: Odd, even, or nothing as selected

· Stop bit: 1 bit or 2 bits as selected

Transfer clock

· When internal clock is selected (bit 3 at addresses 03A0

, 03A8

, 0378

= "0") :

fi/16(n+1) (Note 1)

fi = f

, f

· When external clock is selected (bit 3 at addresses 03A0

, 03A8

="1") :

EXT

/16(n+1) (Note 1) (Note 2) (Do not set external clock for UART2)

Transmission/reception control

_______

CTS

function,

RTS

function,

CTS

and

RTS

function invalid: selectable

Transmission start condition

· To start transmission, the following requirements must be met:

- Transmit enable bit (bit 0 at addresses 03A5

, 03AD

, 037D

) = "1"

- Transmit buffer empty flag (bit 1 at addresses 03A5

, 03AD

, 037D

) = "0"

_______

- When CTS function selected, CTS input level = "L"

Reception start condition

· To start reception, the following requirements must be met:

- Receive enable bit (bit 2 at addresses 03A5

, 03AD

, 037D

) = "1"

- Start bit detection

Interrupt request

· When transmitting

generation timing

ransmit interrupt cause select bits (bits 0,1 at address 03B0

, bit4 at

address 037D

) = "0": Interrupts requested when data transfer from UARTi

transfer buffer register to UARTi transmit register is completed

- Transmit interrupt cause select bits (bits 0, 1 at address 03B0

, bit4 at

address 037D

) = "1": Interrupts requested when data transmission from

UARTi transfer register is completed

When receiving

- Interrupts requested when data transfer from UARTi receive register to

UARTi receive buffer register is completed

Error detection

· Overrun error (Note 3)

This error occurs when the next data is ready before contents of UARTi

receive buffer register are read out

· Framing error

This error occurs when the number of stop bits set is not detected

· Parity error

This error occurs when if parity is enabled, the number of 1's in parity and

character bits does not match the number of 1's set

· Error sum flag

This flag is set (= 1) when any of the overrun, framing, and parity errors is

encountered

(2) Clock asynchronous serial I/O (UART) mode

The UART mode allows transmitting and receiving data after setting the desired transfer rate and transfer
data format. Tables 1.16.5 and 1.16.6 list the specifications of the UART mode. Figure 1.16.16 shows
the UARTi transmit/receive mode register.

Table 1.16.5. Specifications of UART Mode (1)

Note 1: `n' denotes the value 00

to FF

that is set to the UARTi bit rate generator.

Note 2: f

EXT

is input from the CLKi pin.

Note 3: If an overrun error occurs, the UARTi receive buffer will have the next data written in. Note also that

the UARTi receive interrupt request bit is not set to "1".

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Figure 1.16.16. UARTi transmit/receive mode register in UART mode

Symbol

Address

When reset

UiMR(i=0,1)

03A0

, 03A8

CKDIR

UARTi transmit / receive mode registers

Internal / external clock
select bit

STPS

PRY

PRYE

SLEP

0 : Internal clock
1 : External clock (Note)

Bit name

Function

Bit symbol

SMD0

SMD1

SMD2

Serial I/O mode select bit

b2 b1 b0

0 : One stop bit
1 : Two stop bits

0 : Parity disabled
1 : Parity enabled

0 : Sleep mode deselected
1 : Sleep mode selected

1 0 0 : Transfer data 7 bits long
1 0 1 : Transfer data 8 bits long
1 1 0 : Transfer data 9 bits long

Valid when bit 6 = "1"
0 : Odd parity
1 : Even parity

Stop bit length select bit

Odd / even parity
select bit

Parity enable bit

Sleep select bit

Symbol

Address

When reset

U2MR

0378

CKDIR

UART2 transmit / receive mode register

Internal / external clock
select bit

STPS

PRY

PRYE

IOPOL

Must always be fixed to "0"

Bit name

Function

Bit symbol

SMD0

SMD1

SMD2

Serial I/O mode select bit

b2 b1 b0

0 : One stop bit
1 : Two stop bits

0 : Parity disabled
1 : Parity enabled

0 : No reverse
1 : Reverse

1 0 0 : Transfer data 7 bits long
1 0 1 : Transfer data 8 bits long
1 1 0 : Transfer data 9 bits long

Valid when bit 6 = "1"
0 : Odd parity
1 : Even parity

Stop bit length select bit

Odd / even parity
select bit

Parity enable bit

TxD, RxD I/O polarity
reverse bit (Note)

Note: Usually set to "0".

Note : Set the corresponding port direction register to "0".

Clock asynchronous serial I/O (UART) mode

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Table 1.16.7 lists the functions of the input/output pins during UART mode. Note that for a period from

when the UARTi operation mode is selected to when transfer starts, the TxDi pin outputs an "H". (If the N-

channel open-drain is selected, this pin is in floating state.)

Table 1.16.7. Input/output pin functions in UART mode

Pin name

Function

Method of selection

TxDi
(P6

, P6

, P7

)

Serial data output

Serial data input

Programmable I/O port

Transfer clock input

Programmable I/O port

RxDi
(P6

, P6

, P7

)

CLKi
(P6

, P6

, P7

)

Internal/external clock select bit (bit 3 at address 03A0

, 03A8

, 0378

) = "0"

Internal/external clock select bit (bit 3 at address 03A0

, 03A8

) = "1"

Port P6

, P6

direction register (bits 1 and 5 at address 03EE

) = "0"

(Do not set external clock for UART2)

Port P6

, P6

and P7

direction register (bits 2 and 6 at address 03EE

bit 1 at address 03EF

)= "0"

(Can be used as an input port when performing transmission only)

CTS/RTS disable bit (bit 4 at address 03A4

, 03AC

, 037C

) ="0"

CTS/RTS function select bit (bit 2 at address 03A4

, 03AC

, 037C

) = "0"

Port P6

, P6

and P7

direction register (bits 0 and 4 at address 03EE

bit 3 at address 03EF

) = "0"

CTS/RTS disable bit (bit 4 at address 03A4

, 03AC

, 037C

16)

= "0"

CTS/RTS function select bit (bit 2 at address 03A4

, 03AC

, 037C

) = "1"

CTS/RTS disable bit (bit 4 at address 03A4

, 03AC

, 037C

) = "1"

CTS input

RTS output

CTSi/RTSi
(P6

, P6

, P7

)

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Clock asynchronous serial I/O (UART) mode

128

Transmit enable
bit(TE)

Transmit buffer
empty flag(TI)

Transmit register
empty flag (TXEPT)

Start

bit

Parity

bit

TxDi

CTSi

The above timing applies to the following settings :
· Parity is enabled.
· One stop bit.
· CTS function is selected.
· Transmit interrupt cause select bit = "1".

"1"

"0"

"1"

"L"

"H"

"0"

"1"

Tc = 16 (n + 1) / fi or 16 (n + 1) / f

EXT

fi : frequency of BRGi count source (f

, f

)

EXT

: frequency of BRGi count source (external clock)

n : value set to BRGi

Transmit interrupt
request bit (IR)

"0"

"1"

Cleared to "0" when interrupt request is accepted, or cleared by software

Transmit enable
bit(TE)

Transmit buffer
empty flag(TI)

TxDi

Transmit register
empty flag (TXEPT)

"0"

"1"

"0"

"1"

"0"

"1"

The above timing applies to the following settings :
· Parity is disabled.
· Two stop bits.
· CTS function is disabled.
· Transmit interrupt cause select bit = "0".

Transfer clock

Tc = 16 (n + 1) / fi or 16 (n + 1) / f

EXT

fi : frequency of BRGi count source (f

, f

)

EXT

: frequency of BRGi count source (external clock)

n : value set to BRGi

Transmit interrupt
request bit (IR)

"0"

"1"

Shown in ( ) are bit symbols.

Transfer clock

Stopped pulsing because transmit enable bit = "0"

Stop

bit

Transferred from UARTi transmit buffer register to UARTi transmit register

Start

bit

The transfer clock stops momentarily as CTS is "H" when the stop bit is checked.
The transfer clock starts as the transfer starts immediately CTS changes to "L".

Data is set in UARTi transmit buffer register

SPSP

Transferred from UARTi transmit buffer register to UARTi transmit register

Stop

bit

Stop

bit

Data is set in UARTi transmit buffer register.

"0"

Cleared to "0" when interrupt request is accepted, or cleared by software

· Example of transmit timing when transfer data is 8 bits long (parity enabled, one stop bit)

· Example of transmit timing when transfer data is 9 bits long (parity disabled, two stop bits)

Figure 1.16.17. Typical transmit timings in UART mode(UART0,UART1)

Clock asynchronous serial I/O (UART) mode

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Figure 1.16.18. Typical transmit timings in UART mode(UART2)

Start

bit

Parity

bit

Cleared to "0" when interrupt request is accepted, or cleared by software

Stop

bit

Data is set in UART2 transmit buffer register

Transferred from UART2 transmit buffer register to UARTi transmit register

Transmit enable
bit(TE)

Transmit buffer
empty flag(TI)

Transmit register
empty flag (TXEPT)

"0"

"1"

"0"

"1"

"0"

"1"

Transmit interrupt
request bit (IR)

"0"

"1"

Transfer clock

TxD

The above timing applies to the following settings :
· Parity is enabled.
· One stop bit.
· Transmit interrupt cause select bit = "1".

Tc = 16 (n + 1) / fi

fi : frequency of BRG2 count source (f

, f

)

n : value set to BRG2

Shown in ( ) are bit symbols.

Note

Note: The transmit is started with overflow timing of BRG after having written in a value at the transmit buffer in the above timing.

· Example of transmit timing when transfer data is 8 bits long (parity enabled, one stop bit)

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Clock asynchronous serial I/O (UART) mode

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(b) Function for switching serial data logic (UART2)

When the data logic select bit (bit 6 of address 037D

) is assigned 1, data is inverted in writing to the

transmission buffer register or reading the reception buffer register. Figure 1.16.20 shows the ex-

ample of timing for switching serial data logic.

Figure 1.16.20. Timing for switching serial data logic

ST : Start bit
P : Even parity
SP : Stop bit

Transfer clock

TxD

(no reverse)

TxD

(reverse)

"H"

"L"

"H"

"L"

"H"

"L"

· When LSB first, parity enabled, one stop bit

· Example of receive timing when transfer data is 8 bits long (parity disabled, one stop bit)

Figure 1.16.19. Typical receive timing in UART mode

(a) Sleep mode (UART0, UART1)

This mode is used to transfer data between specific microcomputers among multiple microcomputers

connected using UARTi. The sleep mode is selected when the sleep select bit (bit 7 at addresses

03A0

, 03A8

) is set to "1" during reception. In this mode, the unit performs receive operation when

the MSB of the received data = "1" and does not perform receive operation when the MSB = "0".

Start bit

Sampled "L"

Receive data taken in

BRGi count
source

Receive enable bit

RxDi

Transfer clock

Receive
complete flag

RTSi

Stop bit

"1"

"0"

"1"

"H"

"L"

The above timing applies to the following settings :
·Parity is disabled.
·One stop bit.
·RTS function is selected.

Receive interrupt
request bit

"0"

"1"

Transferred from UARTi receive register to
UARTi receive buffer register

Reception triggered when transfer clock
is generated by falling edge of start bit

Cleared to "0" when interrupt request is accepted, or cleared by software

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Clock asynchronous serial I/O (UART) mode

132

Item

Specification

Transfer data format

· Transfer data 8-bit UART mode (bit 2 through bit 0 of address 0378

= "101

· One stop bit (bit 4 of address 0378

= "0")

· With the direct format chosen

Set parity to "even" (bit 5 and bit 6 of address 0378

= "1" and "1" respectively)

Set data logic to "direct" (bit 6 of address 037D

= "0").

Set transfer format to LSB (bit 7 of address 037C

= "0").

· With the inverse format chosen

Set parity to "odd" (bit 5 and bit 6 of address 0378

= "0" and "1" respectively)

Set data logic to "inverse" (bit 6 of address 037D

= "1")

Set transfer format to MSB (bit 7 of address 037C

= "1")

Transfer clock

· With the internal clock chosen (bit 3 of address 0378

= "0") : fi / 16 (n + 1) (Note 1) : fi=f

, f

(Do not set external clock)

Transmission / reception control

_______

· Disable the CTS and RTS function (bit 4 of address 037C

= "1")

Other settings

· The sleep mode select function is not available for UART2

· Set transmission interrupt factor to "transmission completed" (bit 4 of address 037D

= "1")

Transmission start condition · To start transmission, the following requirements must be met:

- Transmit enable bit (bit 0 of address 037D

) = "1"

- Transmit buffer empty flag (bit 1 of address 037D

) = "0"

Reception start condition

· To start reception, the following requirements must be met:

- Reception enable bit (bit 2 of address 037D

) = "1"

- Detection of a start bit

· When transmitting

When data transmission from the UART2 transmit register is completed

(bit 4 of address 037D

= "1")

· When receiving

When data transfer from the UART2 receive register to the UART2 receive

buffer register is completed

Error detection

· Overrun error (see the specifications of clock-asynchronous serial I/O) (Note 2)

· Framing error (see the specifications of clock-asynchronous serial I/O)

· Parity error (see the specifications of clock-asynchronous serial I/O)

- On the reception side, an "L" level is output from the T

pin by use of the parity error

signal output function (bit 7 of address 037D

= "1") when a parity error is detected

- On the transmission side, a parity error is detected by the level of input to

the R

pin when a transmission interrupt occurs

· The error sum flag (see the specifications of clock-asynchronous serial I/O)

(3) Clock-asynchronous serial I/O mode (used for the SIM interface)

The SIM interface is used for connecting the microcomputer with a memory card or the like; adding some

extra settings in UART2 clock-asynchronous serial I/O mode allows the user to effect this function. Table

1.16.8 shows the specifications of clock-asynchronous serial I/O mode (used for the SIM interface).

Interrupt request

generation timing

Note 1: `n' denotes the value 00

to FF

that is set to the UART2 bit rate generator.

Note 2: If an overrun error occurs, the UART2 receive buffer will have the next data written in. Note also

that the UART2 receive interrupt request bit is not set to "1".

Table 1.16.8. Specifications of clock-asynchronous serial I/O mode (used for the SIM interface)

Clock asynchronous serial I/O (UART) mode

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Figure 1.16.22. Typical transmit/receive timing in UART mode (used for the SIM interface)

Transmit enable
bit(TE)

Transmit buffer
empty flag(TI)

Transmit register
empty flag (TXEPT)

Start

bit

Parity

bit

The above timing applies to the following settings :
· Parity is enabled.
· One stop bit.
· Transmit interrupt cause select bit = "1".

"0"

"1"

"0"

"1"

"0"

"1"

Tc = 16 (n + 1) / fi

fi : frequency of BRG2 count source (f

, f

)

n : value set to BRG2

Transmit interrupt
request bit (IR)

"0"

"1"

Shown in ( ) are bit symbols.

Transfer clock

Stop

bit

Data is set in UART2 transmit buffer register

An "L" level returns from TxD

due to

the occurrence of a parity error.

The level is detected by the
interrupt routine.

The level is
detected by the
interrupt routine.

Receive enable
bit (RE)

Receive complete
flag (RI)

Start

bit

Parity

bit

RxD

The above timing applies to the following settings :
· Parity is enabled.
· One stop bit.
· Transmit interrupt cause select bit = "0".

"0"

"1"

"0"

"1"

Tc = 16 (n + 1) / fi

fi : frequency of BRG2 count source (f

, f

)

n : value set to BRG2

Receive interrupt
request bit (IR)

"0"

"1"

Shown in ( ) are bit symbols.

Transfer clock

Stop

bit

An "L" level returns from TxD

due to

the occurrence of a parity error.

TxD

Read to receive buffer

Signal conductor level
(Note 2)

TxD

RxD

Signal conductor level
(Note 2)

Note 2: Equal in waveform because TxD

and RxD

are connected.

Transferred from UART2 transmit buffer register to UART2 transmit register

Cleared to "0" when interrupt request is accepted, or cleared by software

Note 1: The transmit is started with overflow timing of BRG after having written in a value at the transmit buffer in the above timing.

Note 1

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Clock asynchronous serial I/O (UART) mode

134

(a) Function for outputting a parity error signal

During reception, with the error signal output enable bit (bit 7 of address 037D

) assigned "1", you

can output an "L" level from the T

pin when a parity error is detected. And during transmission,

comparing with the case in which the error signal output enable bit (bit 7 of address 037D

) is as-

signed "0", the transmission completion interrupt occurs in the half cycle later of the transfer clock.

Therefore parity error signals can be detected by a transmission completion interrupt program. Figure

1.16.23 shows the output timing of the parity error signal.

Figure 1.16.23. Output timing of the parity error signal

ST : Start bit
P : Even Parity
SP : Stop bit

Hi-Z

Transfer

clock

RxD

TxD

Receive

complete flag

"H"

"L"

"H"

"L"

"H"

"L"

"1"

· LSB first

"0"

(b) Direct format/inverse format

Connecting the SIM card allows you to switch between direct format and inverse format. If you choose

the direct format, D

data is output from TxD

. If you choose the inverse format, D

data is inverted

and output from TxD

Figure 1.16.24 shows the SIM interface format.

Figure 1.16.24. SIM interface format

P : Even parity

Transfer

clcck

TxD

(direct)

TxD

(inverse)

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UART2 Special Mode Register

136

UART2 Special Mode Register

The UART2 special mode register (address 0377

) is used to control UART2 in various ways.

Figure 1.16.26 shows the UART2 special mode register.

Bit 0 of the UART2 special mode register (0377

) is used as the I

C mode select bit.

Setting "1" in the I

C mode select bit (bit 0) goes the circuit to achieve the I

C bus (simplified I

C bus)

interface effective.

Table 1.16.9 shows the relation between the I

C mode select bit and respective control workings.

Since this function uses clock-synchronous serial I/O mode, set this bit to "0" in UART mode.

Figure 1.16.26. UART2 special mode register

UART2 special mode register

Symbol

Address

When reset

U2SMR

0377

b4 b3

Bit

name

Bit

symbol

Function

(During UART mode)

Function

(During clock synchronous

serial I/O mode)

ABSCS

ACSE

SSS

C mode select bit

Bus busy flag

0 : STOP condition detected
1 : START condition detected

SCL L sync output
enable bit

Bus collision detect
sampling clock select bit

Arbitration lost detecting
flag control bit

0 : Normal mode
1 : I

C mode

0 : Update per bit
1 : Update per byte

IICM

ABC

BBS

LSYN

0 : Ordinary
1 : Falling edge of RxD

0 : Disabled
1 : Enabled

Transmit start condition
select bit

Must always be "0"

0 : Rising edge of transfer

clock

1 : Underflow signal of timer A0

Auto clear function
select bit of transmit
enable bit

0 : No auto clear function
1 : Auto clear at occurrence of

bus collision

Must always be "0"

Note 1: Nothing but "0" may be written.
Note 2: When not in I

C mode, do not set this bit by writing a "1". During normal mode, fix it to "0". When this

bit = "0", UART2 special mode register 3 (U2SMR3 at address 0375

) bits 7 to 5 (DL2 to DL0 = SDA

digital delay setup bits) are initialized to "000", with the analog delay circuit selected. Also, when SDDS
= "0", the U2SMR3 register cannot be read or written to.

Note 3: When analog delay is selected, only the analog delay value is effective; when digital delay is selected,

only the digital delay value is effective.

(Note1)

SDDS

SDA digital delay select
bit (Note 2, Note 3)

Must always be "0"

0 : Analog delay output
is selected
1 : Digital delay output
is selected
(must always be "0" when
not using I C mode)

UART2 special mode register 3 (I C bus exclusive use register)

Symbol

Address

When reset

U2SMR3

0375

Indeterminate

(However, when SDDS = "1", the initial value is "00

b6 b5

Bit name

Bit

symbol

Function

(I C bus exclusive use register)

DL2

SDA digital delay setup
bit
(Note 1, Note 2, Note 3,
Note 4)

DL0

DL1

0 0 0 : Analog delay is selected
0 0 1 : 1 to 2 cycle(s) of 1/f(X

)

0 1 0 : 2 to 3 cycles of 1/f(X

)

0 1 1 : 3 to 4 cycles of 1/f(X

)

1 0 0 : 4 to 5 cycles of 1/f(X

)

1 0 1 : 5 to 6 cycles of 1/f(X

)

1 1 0 : 6 to 7 cycles of 1/f(X

)

1 1 1 : 7 to 8 cycles of 1/f(X

)

Nothing is assigned.
In an attempt to write to these bits, write "0". The value, if read, turns out to be
indeterminate. However, when SDDS = "1", the value "0" is read out (Note 1)

b7 b6 b5

Note 1: This bit can be read or written to when UART2 special mode register (U2SMR at address 0377

) bit

7 (SDDS: SDA digital delay select bit) = "1". When the initial value of UART2 special mode register 3
(U2SMR3) is read after setting SDDS = "1", the value is "00

". When writing to UART2 special mode

register 3 (U2SMR3) after setting SDDS = "1", be sure to write 0's to bits 04. When SDDS = "0",
this register cannot be written to; when read, the value is indeterminate.

Note 2: These bits are initialized to "000" when SDDS = "0", with the analog delay circuit selected. After a reset,

these bits are set to "000", with the analog delay circuit selected. However, because these bits can be
read only when SDDS = "1", the value read from these bits when SDDS = "0" is indeterminate.

Note 3: When analog delay is selected, only the analog delay value is effective; when digital delay is selected,

only the digital delay value is effective.

Note 4: The amount of delay varies with the load on SCL and SDA pins. Also, when using an external clock, the

amount of delay increases by about 100 ns, so be sure to take this into account when using the device.

Digital delay
is selected

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UART2 Special Mode Register

137

Function

Normal mode

C mode (Note 1)

Factor of interrupt number 15 (Note 2)

UART2 transmission

No acknowledgment detection (NACK)

Factor of interrupt number 16 (Note 2)

UART2 reception

Start condition detection or stop
condition detection

UART2 transmission output delay

Not delayed

Delayed

at the time when UART2 is in use

TxD

(output)

SDA (input/output) (Note 3)

at the time when UART2 is in use

RxD

(input)

SCL (input/output)

at the time when UART2 is in use

CLK

DMA1 factor at the time when 1 1 0 1 is assigned
to the DMA request factor selection bits

UART2 reception

Acknowledgment detection (ACK)

Noise filter width

15ns

50ns

Reading P7

Reading the terminal when 0 is
assigned to the direction register

Reading the terminal regardless of the
value of the direction register

Note 1: Make the settings given below when I

C mode is in use.

Set 0 1 0 in bits 2, 1, 0 of the UART2 transmission/reception mode register.
Disable the RTS/CTS function. Choose the MSB First function.

Note 2: Follow the steps given below to switch from a factor to another.

1. Disable the interrupt of the corresponding number.
2. Switch from a factor to another.
3. Reset the interrupt request flag of the corresponding number.
4. Set an interrupt level of the corresponding number.

Note 3: Set an initial value of SDA transmission output when serial I/O is invalid.

Factor of interrupt number 10 (Note 2)

Bus collision detection

Acknowledgment detection (ACK)

Initial value of UART2 output

H level (when 0 is assigned to
the CLK polarity select bit)

The value set in latch P7

when the port is

selected

Table 1.16.9. Features in I

C mode

/TxD

/SDA

/RxD

/SCL

CLK
control

/CLK

Falling edge
detection

UART2 reception/ACK interrupt
request, DMA1 request

To DMA0, DMA1

To DMA0

through P7

conforming to the simplified I C bus

I/O

Timer

UART2

Timer

UART2

IICM=1 (SDDS=0) or
DL=000 (SDDS=1)

IICM=0
or IICM2=1

IICM=1
and IICM2=0

SDHI

Noize
Filter

Timer

UART2

I/O

NACK

ACK

UART2

IICM=1

IICM=0

IICM=1

IICM=0

IICM=1

IICM=0

I/O

ALS

IICM=0 or
DL

000 (SDDS=1)

SDDS=0
or DL=000

SDDS=1 and
DL

000

SWC2

Falling edge of 9 bit

SWC

IICM=1
and IICM2=0

IICM=0
or IICM2=1

Selector

Noize
Filter

With IICM set to 1, the port terminal is to be readable

even if 1 is assigned to P7

of the direction register.

Port reading

External clock

Internal clock

9th pulse

Bus collision
detection

Bus collision/start, stop condition
detection interrupt request

UART2 transmission/
NACK interrupt request

Start condition
detection

Stop condition
detection

L-synchronous
output enabling
bit

(Port P7

output data latch)

Data bus

Reception register

Bus busy

Transmission
register

Arbitration

Analog

delay

Digital delay

(Divider)

Figure 1.16.27. Functional block diagram for I

C mode

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UART2 Special Mode Register

138

An attempt to read Port P7

(SCL) results in getting the terminal's level regardless of the content of the

port direction register. The initial value of SDA transmission output in this mode goes to the value set in

port P7

. The interrupt factors of the bus collision detection interrupt, UART2 transmission interrupt, and

of UART2 reception interrupt turn to the start/stop condition detection interrupt, acknowledgment non-

detection interrupt, and acknowledgment detection interrupt respectively.

The start condition detection interrupt refers to the interrupt that occurs when the falling edge of the SDA

terminal (P7

) is detected with the SCL terminal (P7

) staying "H". The stop condition detection interrupt

refers to the interrupt that occurs when the rising edge of the SDA terminal (P7

) is detected with the SCL

terminal (P7

) staying "H". The bus busy flag (bit 2 of the UART2 special mode register) is set to "1" by the

start condition detection, and set to "0" by the stop condition detection.

The acknowledgment non-detection interrupt refers to the interrupt that occurs when the SDA terminal

level is detected still staying "H" at the rising edge of the 9th transmission clock. The acknowledgment

detection interrupt refers to the interrupt that occurs when SDA terminal's level is detected already went

to "L" at the 9th transmission clock. Also, assigning 1 1 0 1 (UART2 reception) to the DMA1 request factor

select bits provides the means to start up the DMA transfer by the effect of acknowledgment detection.

Bit 1 of the UART2 special mode register (0377

) is used as the arbitration lost detecting flag control bit.

Arbitration means the act of detecting the nonconformity between transmission data and SDA terminal

data at the timing of the SCL rising edge. This detecting flag is located at bit 11 of the UART2 reception

buffer register (037F

, 037E

), and "1" is set in this flag when nonconformity is detected. Use the

arbitration lost detecting flag control bit to choose which way to use to update the flag, bit by bit or byte by

byte. When setting this bit to "1" and updated the flag byte by byte if nonconformity is detected, the

arbitration lost detecting flag is set to "1" at the falling edge of the 9th transmission clock.

If update the flag byte by byte, must judge and clear ("0") the arbitration lost detecting flag after complet-

ing the first byte acknowledge detect and before starting the next one byte transmission.

Bit 3 of the UART2 special mode register is used as SCL- and L-synchronous output enable bit. Setting

this bit to "1" goes the P7

data register to "0" in synchronization with the SCL terminal level going to "L".

Figure 1.16.27 shows the functional block diagram for I

C mode. Setting "1" in the I

C mode select bit

(IICM) causes ports P7

, P7

, and P7

to work as data transmission-reception terminal SDA, clock input-

output terminal SCL, and port P7

respectively. A delay circuit is added to the SDA transmission output,

so the SDA output changes after SCL fully goes to "L". The SDA digital delay select bit (bit 7 at address

0377

) can be used to select between analog delay and digital delay. When digital delay is selected, the

amount of delay can be selected in the range of 2 cycles to 8 cycles of f1 using UART2 special mode

). Delay circuit select conditions are shown in Table 1.16.10.

Table 1.16.10. Delay circuit select conditions

Digital delay is
selected

001

111

000

(000)

Analog delay is
selected

No delay

(000)

IICM

SDDS

Contents

When digital delay is selected, no analog delay is added. Only
digital delay is effective.

When DL is set to "000", analog delay is selected no matter what
value is set in SDDS.

When SDDS is set to "0", DL is initialized, so that DL ="000".

When IICM = "0", no delay circuit is selected. When IICM = "0",
however, always make sure SDDS = "0".

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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

UART2 Special Mode Register

139

1. Bus collision detect sampling clock select bit (Bit 4 of the UART2 special mode register)

0: Rising edges of the transfer clock

CLK

Timer A0

1: Timer A0 overflow

2. Auto clear function select bit of transmt enable bit (Bit 5 of the UART2 special mode register)

CLK

TxD/RxD

Bus collision
detect interrupt
request bit

Transmit
enable bit

3. Transmit start condition select bit (Bit 6 of the UART2 special mode register)

CLK

TxD

Enabling transmission

CLK

TxD

RxD

With "1: falling edge of RxD

" selected

0: In normal state

TxD/RxD

Figure 1.16.28. Some other functions added

Some other functions added are explained here. Figure 1.16.28 shows their workings.

Bit 4 of the UART2 special mode register is used as the bus collision detect sampling clock select bit. The

bus collision detect interrupt occurs when the R

level and T

level do not match, but the nonconfor-

mity is detected in synchronization with the rising edge of the transfer clock signal if the bit is set to "0". If

this bit is set to "1", the nonconformity is detected at the timing of the overflow of timer A0 rather than at

the rising edge of the transfer clock.

Bit 5 of the UART2 special mode register is used as the auto clear function select bit of transmit enable

bit. Setting this bit to "1" automatically resets the transmit enable bit to "0" when "1" is set in the bus

collision detect interrupt request bit (nonconformity).

Bit 6 of the UART2 special mode register is used as the transmit start condition select bit. Setting this bit

to "1" starts the TxD transmission in synchronization with the falling edge of the RxD terminal.

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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

UART2 Special Mode Register 2

141

Bit 0 of the UART2 special mode register 2 (address 0376

) is used as the I

C mode select bit 2. Table

1.16.11 shows the types of control to be changed by I

C mode select bit 2 when the I

C mode select bit

is set to "1". Table 1.16.12 shows the timing characteristics of detecting the start condition and the stop

condition. Set the start/stop condition control bit (bit 7 of UART2 special mode register 2) to "1" in I

mode.

Function

IICM2 = 1

IICM2 = 0

Factor of interrupt number 15

No acknowledgment detection (NACK)

UART2 transmission (the rising edge
of the final bit of the clock)

Factor of interrupt number 16

Acknowledgment detection (ACK)

UART2 reception (the falling edge
of the final bit of the clock)

DMA1 factor at the time when 1 1 0 1
is assigned to the DMA request
factor selection bits

Acknowledgment detection (ACK)

UART2 reception (the falling edge of
the final bit of the clock)

Timing for transferring data from the
UART2 reception shift register to the
reception buffer.

The rising edge of the final bit of the
reception clock

The falling edge of the final bit of the
reception clock

Timing for generating a UART2
reception/ACK interrupt request

The rising edge of the final bit of the
reception clock

The falling edge of the final bit of the
reception clock

3 to 6 cycles < duration for setting-up (Note2)

3 to 6 cycles < duration for holding (Note2)

Note 1 : When the start/stop condition control bit SHTC is "1" .
Note 2 : "Cycles" is in terms of the input oscillation frequency f(X

) of the main clock.

Duration for

setting up

Duration for

holding

SCL

SDA

(Start condition)

SDA

(Stop condition)

Table 1.16.11. Functions changed by I

C mode select bit 2

Table 1.16.12. Timing characteristics of detecting the start condition and the stop condition (Note1)

Mitsubishi microcomputers

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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

UART2 Special Mode Register 2

142

/TxD

/SDA

/RxD

/SCL

CLK
control

/CLK

Falling edge
detection

UART2 reception/ACK interrupt
request, DMA1 request

To DMA0, DMA1

To DMA0

through P7

conforming to the simplified I C bus

I/O

Timer

UART2

Timer

UART2

IICM=1 (SDDS=0) or
DL=000 (SDDS=1)

IICM=0
or IICM2=1

IICM=1
and IICM2=0

SDHI

Noize
Filter

Timer

UART2

I/O

NACK

ACK

UART2

IICM=1

IICM=0

IICM=1

IICM=0

IICM=1

IICM=0

I/O

ALS

IICM=0 or
DL

000 (SDDS=1)

SDDS=0
or DL=000

SDDS=1 and
DL

000

SWC2

Falling edge of 9 bit

SWC

IICM=1
and IICM2=0

IICM=0
or IICM2=1

Selector

Noize
Filter

With IICM set to 1, the port terminal is to be readable

even if 1 is assigned to P7

of the direction register.

Port reading

External clock

Internal clock

9th pulse

Bus collision
detection

Bus collision/start, stop condition
detection interrupt request

UART2 transmission/
NACK interrupt request

Start condition
detection

Stop condition
detection

L-synchronous
output enabling
bit

(Port P7

output data latch)

Data bus

Reception register

Bus busy

Transmission
register

Arbitration

Analog

delay

Digital delay

(Divider)

Functions available in I

C mode are shown in Figure 1.16.30 -- a functional block diagram.

Bit 3 of the UART2 special mode register 2 (address 0376

) is used as the SDA output stop bit. Setting

this bit to "1" causes an arbitration loss to occur, and the SDA pin turns to high-impedance state at the

instant when the arbitration lost detecting flag is set to "1".

Bit 1 of the UART2 special mode register 2 (address 0376

) is used as the clock synchronization bit.

With this bit set to "1" at the time when the internal SCL is set to "H", the internal SCL turns to "L" if the

falling edge is found in the SCL pin; and the baud rate generator reloads the set value, and start counting

within the "L" interval. When the internal SCL changes from "L" to "H" with the SCL pin set to "L", stops

counting the baud rate generator, and starts counting it again when the SCL pin turns to "H". Due to this

function, the UART2 transmission-reception clock becomes the logical product of the signal flowing

through the internal SCL and that flowing through the SCL pin. This function operates over the period

from the moment earlier by a half cycle than falling edge of the UART2 first clock to the rising edge of the

ninth bit. To use this function, choose the internal clock for the transfer clock.

Bit 2 of the UART2 special mode register 2 (0376

) is used as the SCL wait output bit. Setting this bit to

"1" causes the SCL pin to be fixed to "L" at the falling edge of the ninth bit of the clock. Setting this bit to

"0" frees the output fixed to "L".

Figure 1.16.30. Functional block diagram for I

C mode

Mitsubishi microcomputers

M16C / 62A Group

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

UART2 Special Mode Register 2

143

Bit 4 of the UART2 special mode register 2 (address 0376

) is used as the UART2 initialization bit.

Setting this bit to "1", and when the start condition is detected, the microcomputer operates as follows.

(1) The transmission shift register is initialized, and the content of the transmission register is transferred

to the transmission shift register. This starts transmission by dealing with the clock entered next as the

first bit. The UART2 output value, however, doesn't change until the first bit data is output after the

entrance of the clock, and remains unchanged from the value at the moment when the microcomputer

detected the start condition.

(2) The reception shift register is initialized, and the microcomputer starts reception by dealing with the

clock entered next as the first bit.

(3) The SCL wait output bit turns to "1". This turns the SCL pin to "L" at the falling edge of the ninth bit of

the clock.

Starting to transmit/receive signals to/from UART2 using this function doesn't change the value of the

transmission buffer empty flag. To use this function, choose the external clock for the transfer clock.

Bit 5 of the UART2 special mode register 2 (0376

) is used as the SCL pin wait output bit 2. Setting this

bit to "1" with the serial I/O specified allows the user to forcibly output an "1" from the SCL pin even if

UART2 is in operation. Setting this bit to "0" frees the "L" output from the SCL pin, and the UART2 clock

is input/output.

Bit 6 of the UART2 special mode register 2 (0376

) is used as the SDA output disable bit. Setting this bit

to "1" forces the SDA pin to turn to the high-impedance state. Refrain from changing the value of this bit

at the rising edge of the UART2 transfer clock. There can be instances in which arbitration lost detecting

flag is turned on.

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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

S I/O3, 4

145

SI/Oi bit rate generator (Note 1, 2)

Symbol

Address

When reset

S3BRG

0363

Indeterminate

S4BRG

0367

Indeterminate

Assuming that set value = n, BRGi divides the count
source by n + 1

to FF

Values that can be set

SI/Oi transmit/receive register (Note)

Symbol

Address

When reset

S3TRR

0360

Indeterminate

S4TRR

0364

Indeterminate

Transmission/reception starts by writing data to this register.
After transmission/reception finishes, reception data is input.

S I/Oi control register (i = 3, 4) (Note 1)

Symbol

Address

When reset

SiC

0362

, 0366

b4 b3

Description

SMi5

SMi1

SMi0

SMi3

SMi6

SMi7

Internal synchronous
clock select bit

Transfer direction select
bit

S I/Oi port select bit
(Note 2)

OUT

i initial value

set bit

0 0 : Selecting f

0 1 : Selecting f

1 0 : Selecting f

1 1 : Must not be set.

b1 b0

0 : External clock
1 : Internal clock

Effective when SMi3 = 0
0 : L output
1 : H output

0 : Input-output port
1 : S

OUT

i output, CLK function

Bit name

Bit

symbol

Synchronous clock
select bit (Note 2)

0 : LSB first
1 : MSB first

SMi2

OUT

i output disable bit

0 : S

OUT

i output

1 : S

OUT

i output disable

(high impedance)

Note 1: Set "1" in bit 2 of the protection register (000A

) in advance to write to the

S I/Oi control register (i = 3, 4).

Note 2:

When using the port as an input/output port by setting the SI/Oi port

select bit (i = 3, 4) to

"0"

, be sure to set the sync clock select bit to

"1"

Nothing is assigned.
In an attempt to write to this bit, write "0". The value, if read, turns out to be "0".

Note 1: Write a value to this register while transmit/receive halts.
Note 2: Use MOV instruction to write to this register.

Note: Write a value to this register while transmit/receive halts.

Figure 1.16.32. S I/O3, 4 related register

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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

S I/O3, 4

146

Table 1.16.13. Specifications of S I/O3, 4

Note 1: n is a value from 00

through FF

set in the S I/Oi bit rate generator (i = 3, 4).

Note 2: With the external clock selected:

· Before data can be written to the SI/Oi transmit/receive register (addresses 0360

, 0364

), the

CLKi pin input must be in the high state. Also, before rewriting the SI/Oi Control Register (addresses

0362

, 0366

)'s bit 7 (S

OUT

i initial value set bit), make sure the CLKi pin input is held high.

· The S I/Oi circuit keeps on with the shift operation as long as the synchronous clock is entered in it,

so stop the synchronous clock at the instant when it counts to eight. The internal clock, if selected,

automatically stops.

Note 3: If the internal clock is used for the synchronous clock, the transfer clock signal stops at the "H" state.

Item

Transfer data format

Transfer clock

Conditions for

transmission/

reception start

Interrupt request

generation timing

Select function

Precaution

Specifications

· Transfer data length: 8 bits

· With the internal clock selected (bit 6 of 0362

, 0366

= "1"): f

/2(ni+1),

/2(ni+1), f

/2(ni+1) (Note 1)

· With the external clock selected (bit 6 of 0362

, 0366

= 0):Input from the CLKi terminal (Note 2)

· To start transmit/reception, the following requirements must be met:

- Select the synchronous clock (use bit 6 of 0362

, 0366

Select a frequency dividing ratio if the internal clock has been selected (use bits

0 and 1 of 0362

, 0366

- S

OUT

i initial value set bit (use bit 7 of 0362

, 0366

)= 1.

- S I/Oi port select bit (bit 3 of 0362

, 0366

) = 1.

- Select the transfer direction (use bit 5 of 0362

, 0366

)

-Write transfer data to SI/Oi transmit/receive register (0360

, 0364

)

· To use S I/Oi interrupts, the following requirements must be met:

- Clear the SI/Oi interrupt request bit before writing transfer data to the SI/Oi

transmit/receive register (bit 3 of 0049

, 0048

) = 0.

· Rising edge of the last transfer clock. (Note 3)

· LSB first or MSB first selection

Whether transmission/reception begins with bit 0 (LSB) or bit 7 (MSB) can be

selected.

· Function for setting an S

OUT

i initial value selection

When using an external clock for the transfer clock, the user can choose the

OUT

i pin output level during a non-transfer time. For details on how to set, see

Figure 1.16.33.

· Unlike UART02, SI/Oi (i = 3, 4) is not divided for transfer register and buffer.

Therefore, do not write the next transfer data to the SI/Oi transmit/receive register

(addresses 0360

, 0364

) during a transfer.

· When the internal clock is selected for the transfer clock, S

OUT

i holds the last data

for a 1/2 transfer clock period after it finished transferring and then goes to a high-

impedance state. However, if the transfer data is written to the SI/Oi transmit/

receive register (addresses 0360

, 0364

) during this time, S

OUT

i is placed in

the high-impedance state immediately upon writing and the data hold time is

thereby reduced.

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M16C / 62A Group

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

S I/O3, 4

147

Functions for setting an S

OUT

i initial value

When using an external clock for the transfer clock, the S

OUTi

pin output level during a non-transfer

time can be set to the high or the low state. Figure 1.16.33 shows the timing chart for setting an S

OUTi

initial value and how to set it.

Figure 1.16.33. Timing chart for setting S

OUT

i's initial value and how to set it

S I/Oi operation timing

Figure 1.16.34 shows the S I/Oi operation timing

(i= 3, 4)

Hiz

(i= 3, 4)

1.5 cycle (max)

SI/Oi internal clock

Transfer clock

(Note 1)

Signal written to the S I/Oi
transmit/receive register

S I/Oi output S

OUT

S I/Oi input S

SI/Oi interrupt request
bit

Note2

Note 1: With the internal clock selected for the transfer clock, the frequency dividing ratio can be selected using bits 0 and 1 of the S I/Oi control

Note 2: With the internal clock selected for the transfer clock, the S

OUT

i (i = 3, 4) pin becomes to the high-impedance state after the transfer finishes.

Note 3: Shown above is the case where the S

OUT

i (i = 3, 4) port select bit ="1".

"H"
"L"

"H"

"L"

"H"

"L"

"H"

"L"

"1"
"0"

Figure 1.16.34. S I/Oi operation timing chart

S I/Oi port select bit SMi3 = 0

SOUTi initial value select bit

SMi7 = 1

OUT

i: Internal "H" level)

S I/Oi port select bit

SMi3 = 0 1

(Port select: Normal port S

OUT

i terminal = "H" output

Signal written to the S I/Oi register

="L" "H" "L"

(Falling edge)

OUT

i terminal = Outputting

stored data in the S I/Oi transmission/

reception register

Signal written to the S I/Oi

transmit/receive register

OUT

i (internal)

OUT

i's initial value

set bit (SMi7)

OUT

i terminal output

S I/Oi port select bit

(SMi3)

Setting the S

OUT

initial value to H

Port selection
(normal port S

OUT

(i = 3, 4)

Initial value = "H" (Note)

Port output

(Example) With "H" selected for S

OUT

Note: The set value is output only when the external clock has been selected. When

initializing S

OUT

i, make sure the CLKi pin input is held "H" level.

If the internal clock has been selected or if S

OUT

output disable has been set,

this output goes to the high-impedance state.

Mitsubishi microcomputers

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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

A-D Converter

148

Item

Performance

Method of A-D conversion Successive approximation (capacitive coupling amplifier)

Analog input voltage (Note 1) 0V to AV

)

Operating clock

(Note 2) V

= 5V

/divide-by-2 of f

/divide-by-4 of f

, f

=f(X

)

= 3V

divide-by-2 of f

/divide-by-4 of f

, f

=f(X

)

Resolution

8-bit or 10-bit (selectable)

Absolute precision

= 5V

· Without sample and hold function

3LSB

· With sample and hold function (8-bit resolution)

2LSB

· With sample and hold function (10-bit resolution)

to AN

input :

3LSB

ANEX0 and ANEX1 input (including mode in which external

operation amp is connected) :

7LSB

= 3V

· Without sample and hold function (8-bit resolution)

2LSB

Operating modes

One-shot mode, repeat mode, single sweep mode, repeat sweep mode 0,

and repeat sweep mode 1

Analog input pins

8pins (AN

to AN

) + 2pins (ANEX0 and ANEX1)

A-D conversion start condition · Software trigger

A-D conversion starts when the A-D conversion start flag changes to "1"

· External trigger (can be retriggered)

A-D conversion starts when the A-D conversion start flag is "1" and the

___________

TRG

/P9

input changes from "H" to "L"

Conversion speed per pin · Without sample and hold function

8-bit resolution: 49

cycles, 10-bit resolution: 59

cycles

· With sample and hold function

8-bit resolution: 28

cycles, 10-bit resolution: 33

cycles

A-D Converter

The A-D converter consists of one 10-bit successive approximation A-D converter circuit with a capacitive coupling

amplifier. Pins P10

to P10

, P9

, and P9

also function as the analog signal input pins. The direction registers of

these pins for A-D conversion must therefore be set to input. The Vref connect bit (bit 5 at address 03D7

) can be

used to isolate the resistance ladder of the A-D converter from the reference voltage input pin (V

REF

) when the A-D

converter is not used. Doing so stops any current flowing into the resistance ladder from V

REF

, reducing the power

dissipation. When using the A-D converter, start A-D conversion only after setting bit 5 of 03D7

to connect V

REF

The result of A-D conversion is stored in the A-D registers of the selected pins. When set to 10-bit precision, the low

8 bits are stored in the even addresses and the high 2 bits in the odd addresses. When set to 8-bit precision, the low

8 bits are stored in the even addresses.

Table 1.17.1 shows the performance of the A-D converter. Figure 1.17.1 shows the block diagram of the

A-D converter, and Figures 1.17.2 and 1.17.3 show the A-D converter-related registers.

Note 1: Does not depend on use of sample and hold function.

Note 2: Divide the frequency if f(X

) exceeds 10MH

, and make

frequency equal to or less than 10MHz.

Without sample and hold function, set the

frequency to 250kH

min.

With the sample and hold function, set the

frequency to 1MH

min.

Table 1.17.1. Performance of A-D converter

Mitsubishi microcomputers

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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

A-D Converter

149

Figure 1.17.1. Block diagram of A-D converter

1/2

A-D conversion rate
selection

(03C1

, 03C0

)

(03C3

, 03C2

)

(03C5

, 03C4

)

(03C7

, 03C6

)

(03C9

, 03C8

)

(03CB

, 03CA

)

(03CD

, 03CC

)

(03CF

, 03CE

)

CKS1=1

CKS0=0

0 0 : Normal operation
0 1 : ANEX0
1 0 : ANEX1
1 1 : External op-amp mode

A-D register 0(16)

A-D register 1(16)
A-D register 2(16)

A-D register 3(16)

A-D register 4(16)

A-D register 5(16)

A-D register 6(16)

A-D register 7(16)

Resistor ladder

ANEX1

ANEX0

Successive conversion register

OPA1,OPA0=0,1

OPA0=1

OPA1=1

OPA1,OPA0=1,1

A-D control register 0 (address 03D6

)

A-D control register 1 (address 03D7

)

ref

Data bus high-order

Data bus low-order

REF

OPA1,OPA0=0,0

VCUT=0

VCUT=1

CKS0=1

CKS1=0

CH2,CH1,CH0=000

CH2,CH1,CH0=001

CH2,CH1,CH0=010

CH2,CH1,CH0=011

CH2,CH1,CH0=100

CH2,CH1,CH0=101

CH2,CH1,CH0=110

CH2,CH1,CH0=111

Decoder

Comparator

OPA1, OPA0

Addresses

Mitsubishi microcomputers

M16C / 62A Group

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

A-D Converter

150

Figure 1.17.2. A-D converter-related registers (1)

A-D control register 0 (Note 1)

Symbol

Address

When reset

ADCON0

03D6

00000XXX

Analog input pin select bit

0 0 0 : AN

is selected

0 0 1 : AN

is selected

0 1 0 : AN

is selected

0 1 1 : AN

is selected

1 0 0 : AN

is selected

1 0 1 : AN

is selected

1 1 0 : AN

is selected

1 1 1 : AN

is selected

(Note 2)

CH0

Bit symbol

Bit name

Function

CH1

CH2

A-D operation mode
select bit 0

0 0 : One-shot mode
0 1 : Repeat mode
1 0 : Single sweep mode
1 1 : Repeat sweep mode 0

Repeat sweep mode 1

(Note 2)

MD0

MD1

Trigger select bit

0 : Software trigger
1 : AD

TRG

trigger

TRG

ADST

A-D conversion start flag

0 : A-D conversion disabled
1 : A-D conversion started

Frequency select bit 0

0 : f

/4 is selected

1 : f

/2 is selected

CKS0

A-D control register 1 (Note)

Symbol Address

When

reset

ADCON1

03D7

Bit name

Function

Bit symbol

A-D sweep pin select bit

SCAN0

SCAN1

MD2

BITS

8/10-bit mode select bit

0 : 8-bit mode
1 : 10-bit mode

VCUT

OPA0

Vref connect bit

OPA1

A-D operation mode
select bit 1

0 : Any mode other than repeat sweep

mode 1

1 : Repeat sweep mode 1

0 : Vref not connected
1 : Vref connected

External op-amp
connection mode bit

b2 b1 b0

b4 b3

When single sweep and repeat sweep
mode 0 are selected

0 0 : AN

, AN

(2 pins)

0 1 : AN

to AN

(4 pins)

1 0 : AN

to AN

(6 pins)

1 1 : AN

to AN

(8 pins)

b1 b0

When repeat sweep mode 1 is selected

0 0 : AN

(1 pin)

0 1 : AN

, AN

(2 pins)

1 0 : AN

to AN

(3 pins)

1 1 : AN

to AN

(4 pins)

b1 b0

0 0 : ANEX0 and ANEX1 are not used
0 1 : ANEX0 input is A-D converted
1 0 : ANEX1 input is A-D converted
1 1 : External op-amp connection mode

b7 b6

Note 1: If the A-D control register is rewritten during A-D conversion, the conversion result is

indeterminate.

Note 2: When changing A-D operation mode, set analog input pin again.

Frequency select bit 1

0 : f

/2 or f

/4 is selected

1 : f

is selected

CKS1

Note: If the A-D control register is rewritten during A-D conversion, the conversion result is

indeterminate.

Mitsubishi microcomputers

M16C / 62A Group

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

A-D Converter

152

(1) One-shot mode

In one-shot mode, the pin selected using the analog input pin select bit is used for one-shot A-D conver-

sion. Table 1.17.2 shows the specifications of one-shot mode. Figure 1.17.4 shows the A-D control regis-

ter in one-shot mode.

Table 1.17.2. One-shot mode specifications

Figure 1.17.4. A-D conversion register in one-shot mode

A-D control register 0 (Note 1)

Symbol

Address

When reset

ADCON0

03D6

00000XXX

Analog input pin select
bit

Bit symbol

Bit name

Function

CH1

CH2

A-D operation mode
select bit 0

MD0

MD1

Trigger select bit

0 : Software trigger
1 : AD

TRG

trigger

TRG

ADST

A-D conversion start flag

0 : A-D conversion disabled
1 : A-D conversion started

Frequency select bit 0

0: f

/4 is selected

1: f

/2 is selected

CKS0

A-D control register 1 (Note)

Symbol

Address

When reset

ADCON1

03D7

Bit name

Function

Bit symbol

A-D sweep pin
select bit

SCAN0

SCAN1

MD2

BITS

8/10-bit mode select bit

0 : 8-bit mode
1 : 10-bit mode

VCUT

OPA0

Vref connect bit

OPA1

A-D operation mode
select bit 1

Set to "0" when this mode is selected

1 : Vref connected

External op-amp
connection mode bit

0 0 : ANEX0 and ANEX1 are not used
0 1 : ANEX0 input is A-D converted
1 0 : ANEX1 input is A-D converted
1 1 : External op-amp connection mode

Invalid in one-shot mode

0 0 0 : AN

is selected

0 0 1 : AN

is selected

0 1 0 : AN

is selected

0 1 1 : AN

is selected

1 0 0 : AN

is selected

1 0 1 : AN

is selected

1 1 0 : AN

is selected

1 1 1 : AN

is selected

(Note 2)

b2 b1 b0

0 0 : One-shot mode

(Note 2)

b4 b3

CH0

b7 b6

Note 1: If the A-D control register is rewritten during A-D conversion, the conversion

result is indeterminate.

Note 2: When changing A-D operation mode, set analog input pin again.

Frequency select bit1

0 : f

/2 or f

/4 is selected

1 : f

is selected

CKS1

Note: If the A-D control register is rewritten during A-D conversion, the conversion

result is indeterminate.

Item

Specification

Function

The pin selected by the analog input pin select bit is used for one A-D conversion

Start condition

Writing "1" to A-D conversion start flag

Stop condition

· End of A-D conversion (A-D conversion start flag changes to "0", except

when external trigger is selected)

· Writing "0" to A-D conversion start flag

Interrupt request generation timing

End of A-D conversion

Input pin

One of AN

to AN

, as selected

Reading of result of A-D converter

Read A-D register corresponding to selected pin

Mitsubishi microcomputers

M16C / 62A Group

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

A-D Converter

153

(2) Repeat mode

In repeat mode, the pin selected using the analog input pin select bit is used for repeated A-D conversion.

Table 1.17.3 shows the specifications of repeat mode. Figure 1.17.5 shows the A-D control register in

repeat mode.

A-D control register 0 (Note 1)

Symbol

Address When

reset

ADCON0

03D6

00000XXX

Analog input pin
select bit

CH0

Bit symbol

Bit name

Function

CH1

CH2

A-D operation mode
select bit 0

MD0

MD1

Trigger select bit

0 : Software trigger
1 : AD

TRG

trigger

TRG

ADST

A-D conversion start flag

0 : A-D conversion disabled
1 : A-D conversion started

Frequency select bit 0

0 : f

/4 is selected

1 : f

/2 is selected

CKS0

A-D control register 1 (Note)

Symbol

Address

When reset

ADCON1

03D7

Bit name

Function

Bit symbol

A-D sweep pin
select bit

SCAN0

SCAN1

MD2

BITS

8/10-bit mode select bit

0 : 8-bit mode
1 : 10-bit mode

VCUT

OPA0

Vref connect bit

OPA1

A-D operation mode
select bit 1

1 : Vref connected

External op-amp
connection mode bit

Invalid in repeat mode

0 0 0 : AN

is selected

0 0 1 : AN

is selected

0 1 0 : AN

is selected

0 1 1 : AN

is selected

1 0 0 : AN

is selected

1 0 1 : AN

is selected

1 1 0 : AN

is selected

1 1 1 : AN

is selected

(Note 2)

b2 b1 b0

0 1 : Repeat mode

(Note 2)

b4 b3

0 0 : ANEX0 and ANEX1 are not used
0 1 : ANEX0 input is A-D converted
1 0 : ANEX1 input is A-D converted
1 1 : External op-amp connection mode

b7 b6

Note 1: If the A-D control register is rewritten during A-D conversion, the conversion

result is indeterminate.

Note 2: When changing A-D operation mode, set analog input pin again.

Frequency select bit 1

0 : f

/2 or f

/4 is selected

1 : f

is selected

CKS1

Note: If the A-D control register is rewritten during A-D conversion, the conversion

result is indeterminate.

Set to "0" when this mode is selected

Figure 1.17.5. A-D conversion register in repeat mode

Item

Specification

Function

The pin selected by the analog input pin select bit is used for repeated A-D conversion

Star condition

Writing "1" to A-D conversion start flag

Stop condition

Writing "0" to A-D conversion start flag

Interrupt request generation timing

None generated

Input pin

One of AN

to AN

, as selected

Reading of result of A-D converter

Read A-D register corresponding to selected pin (at any time)

Table 1.17.3. Repeat mode specifications

Mitsubishi microcomputers

M16C / 62A Group

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

A-D Converter

154

(3) Single sweep mode

In single sweep mode, the pins selected using the A-D sweep pin select bit are used for one-by-one A-D

conversion. Table 1.17.4 shows the specifications of single sweep mode. Figure 1.17.6 shows the A-D

control register in single sweep mode.

Table 1.17.4. Single sweep mode specifications

Figure 1.17.6. A-D conversion register in single sweep mode

A-D control register 0 (Note)

Symbol

Address

When reset

ADCON0

03D6

00000XXX

Analog input pin
select bit

CH0

Bit symbol

Bit name

Function

CH1

CH2

A-D operation mode
select bit 0

1 0 : Single sweep mode

MD0

MD1

Trigger select bit

0 : Software trigger
1 : AD

TRG

trigger

TRG

ADST

A-D conversion start flag

0 : A-D conversion disabled
1 : A-D conversion started

Frequency select bit 0

0 : f

/4 is selected

1 : f

/2 is selected

CKS0

A-D control register 1 (Note 1)

Symbol

Address

When reset

ADCON1

03D7

Bit name

Function

Bit symbol

A-D sweep pin select bit

SCAN0

SCAN1

MD2

BITS

8/10-bit mode select bit

0 : 8-bit mode
1 : 10-bit mode

VCUT

OPA0

Vref connect bit

OPA1

A-D operation mode
select bit 1

1 : Vref connected

External op-amp
connection mode
bit (Note 2)

1 0

Invalid in single sweep mode

Note 1: If the A-D control register is rewritten during A-D conversion, the conversion result

is indeterminate.

Note 2: Neither `01' nor `10' can be selected with the external op-amp connection mode bit.

b4 b3

When single sweep and repeat sweep mode 0
are selected

0 0 : AN

, AN

(2 pins)

0 1 : AN

to AN

(4 pins)

1 0 : AN

to AN

(6 pins)

1 1 : AN

to AN

(8 pins)

b1 b0

0 0 : ANEX0 and ANEX1 are not used
0 1 : ANEX0 input is A-D converted
1 0 : ANEX1 input is A-D converted
1 1 : External op-amp connection mode

b7 b6

Note: If the A-D control register is rewritten during A-D conversion, the conversion result

is indeterminate.

Frequency select bit 1

0 : f

/2 or f

/4 is selected

1 : f

is selected

CKS1

Set to "0" when this mode is selected

Item

Specification

Function

The pins selected by the A-D sweep pin select bit are used for one-by-one A-D conversion

Start condition

Writing "1" to A-D converter start flag

Stop condition

· End of A-D conversion (A-D conversion start flag changes to "0", except

when external trigger is selected)

· Writing "0" to A-D conversion start flag

Interrupt request generation timing

End of A-D conversion

Input pin

and AN

(2 pins), AN

to AN

(4 pins), AN

to AN

(6 pins), or AN

to AN

(8 pins)

Reading of result of A-D converter

Read A-D register corresponding to selected pin

Mitsubishi microcomputers

M16C / 62A Group

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

A-D Converter

155

(4) Repeat sweep mode 0

In repeat sweep mode 0, the pins selected using the A-D sweep pin select bit are used for repeat sweep

A-D conversion. Table 1.17.5 shows the specifications of repeat sweep mode 0. Figure 1.17.7 shows the

A-D control register in repeat sweep mode 0.

Figure 1.17.7. A-D conversion register in repeat sweep mode 0

A-D control register 0 (Note)

Symbol

Address

When reset

ADCON0

03D6

00000XXX

Analog input pin
select bit

CH0

Bit symbol

Bit name

Function

CH1

CH2

A-D operation mode
select bit 0

1 1 : Repeat sweep mode 0

MD0

MD1

Trigger select bit

0 : Software trigger
1 : AD

TRG

trigger

TRG

ADST

A-D conversion start flag

0 : A-D conversion disabled
1 : A-D conversion started

Frequency select bit 0

0 : f

/4 is selected

1 : f

/2 is selected

CKS0

A-D control register 1 (Note 1)

Symbol

Address

When reset

ADCON1

03D7

Bit name

Function

Bit symbol

A-D sweep pin select bit

SCAN0

SCAN1

MD2

BITS

8/10-bit mode select bit

0 : 8-bit mode
1 : 10-bit mode

VCUT

OPA0

Vref connect bit

OPA1

A-D operation mode
select bit 1

1 : Vref connected

External op-amp
connection mode
bit (Note 2)

1 1

Invalid in repeat sweep mode 0

Note 1: If the A-D control register is rewritten during A-D conversion, the conversion result

is indeterminate.

Note 2: Neither "01" nor "10" can be selected with the external op-amp connection mode bit.

b4 b3

When single sweep and repeat sweep mode 0
are selected

0 0 : AN

, AN

(2 pins)

0 1 : AN

to AN

(4 pins)

1 0 : AN

to AN

(6 pins)

1 1 : AN

to AN

(8 pins)

b1 b0

0 0 : ANEX0 and ANEX1 are not used
0 1 : ANEX0 input is A-D converted
1 0 : ANEX1 input is A-D converted
1 1 : External op-amp connection mode

b7 b6

Note: If the A-D control register is rewritten during A-D conversion, the conversion result

is indeterminate.

Frequency select bit 1

0 : f

/2 or f

/4 is selected

1 : f

is selected

CKS1

Set to "0" when this mode is selected

Item

Specification

Function

The pins selected by the A-D sweep pin select bit are used for repeat A-D conversion

Start condition

Writing "1" to A-D conversion start flag

Stop condition

Writing "0" to A-D conversion start flag

Interrupt request generation timing

None generated

Input pin

and AN

(2 pins), AN

to AN

(4 pins), AN

to AN

(6 pins), or AN

to AN

(8 pins)

Reading of result of A-D converter

Read A-D register corresponding to selected pin (at any time)

Table 1.17.5. Repeat sweep mode 0 specifications

Mitsubishi microcomputers

M16C / 62A Group

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

A-D Converter

156

Item

Specification

Function

All pins perform repeat A-D conversion, with emphasis on the pin or pins

selected by the A-D sweep pin select bit

Example : AN

selected AN

, etc

Start condition

Writing "1" to A-D conversion start flag

Stop condition

Writing "0" to A-D conversion start flag

Interrupt request generation timing

None generated

Input pin

With emphasis on these pins ; AN

(1 pin), AN

and AN

(2 pins),

to AN

(3 pins), AN

to AN

(4 pins)

Reading of result of A-D converter

Read A-D register corresponding to selected pin (at any time)

(5) Repeat sweep mode 1

In repeat sweep mode 1, all pins are used for A-D conversion with emphasis on the pin or pins selected

using the A-D sweep pin select bit. Table 1.17.6 shows the specifications of repeat sweep mode 1. Figure

1.17.8 shows the A-D control register in repeat sweep mode 1.

A-D control register 0 (Note)

Symbol

Address

When reset

ADCON0

03D6

00000XXX

Analog input pin
select bit

CH0

Bit symbol

Bit name

Function

CH1

CH2

A-D operation mode
select bit 0

1 1 : Repeat sweep mode 1

MD0

MD1

Trigger select bit

0 : Software trigger
1 : AD

TRG

trigger

TRG

ADST

A-D conversion start flag

0 : A-D conversion disabled
1 : A-D conversion started

Frequency select bit 0

0 : f

/4 is selected

1 : f

/2 is selected

CKS0

A-D control register 1 (Note 1)

Symbol

Address

When reset

ADCON1

03D7

Bit name

Function

Bit symbol

A-D sweep pin select bit

SCAN0

SCAN1

MD2

BITS

8/10-bit mode select bit

0 : 8-bit mode
1 : 10-bit mode

VCUT

OPA0

Vref connect bit

OPA1

A-D operation mode
select bit 1

1 : Vref connected

External op-amp
connection mode
bit (Note 2)

1 1

Invalid in repeat sweep mode 1

Note 1: If the A-D control register is rewritten during A-D conversion, the conversion result

is indeterminate.

Note 2: Neither `01' nor `10' can be selected with the external op-amp connection mode bit.

b4 b3

When repeat sweep mode 1 is selected

0 0 : AN

(1 pin)

0 1 : AN

, AN

(2 pins)

1 0 : AN

to AN

(3 pins)

1 1 : AN

to AN

(4 pins)

b1 b0

0 0 : ANEX0 and ANEX1 are not used
0 1 : ANEX0 input is A-D converted
1 0 : ANEX1 input is A-D converted
1 1 : External op-amp connection mode

b7 b6

Note: If the A-D control register is rewritten during A-D conversion, the conversion result

is indeterminate.

Frequency select bit 1

0 : f

/2 or f

/4 is selected

1 : f

is selected

CKS1

Set to "1" when this mode is selected

Figure 1.17.8. A-D conversion register in repeat sweep mode 1

Table 1.17.6. Repeat sweep mode 1 specifications

Mitsubishi microcomputers

M16C / 62A Group

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

A-D Converter

157

(a) Sample and hold

Sample and hold is selected by setting bit 0 of the A-D control register 2 (address 03D4

) to "1". When

sample and hold is selected, the rate of conversion of each pin increases. As a result, a 28

cycle is

achieved with 8-bit resolution and 33

with 10-bit resolution. Sample and hold can be selected in all

modes. However, in all modes, be sure to specify before starting A-D conversion whether sample and

hold is to be used.

(b) Extended analog input pins

In one-shot mode and repeat mode, the input via the extended analog input pins ANEX0 and ANEX1 can

also be converted from analog to digital.

When bit 6 of the A-D control register 1 (address 03D7

) is "1" and bit 7 is "0", input via ANEX0 is

converted from analog to digital. The result of conversion is stored in A-D register 0.

When bit 6 of the A-D control register 1 (address 03D7

) is "0" and bit 7 is "1", input via ANEX1 is

converted from analog to digital. The result of conversion is stored in A-D register 1.

(c) External operation amp connection mode

In this mode, multiple external analog inputs via the extended analog input pins, ANEX0 and ANEX1, can

be amplified together by just one operation amp and used as the input for A-D conversion.

When bit 6 of the A-D control register 1 (address 03D7

) is "1" and bit 7 is "1", input via AN

to AN

output from ANEX0. The input from ANEX1 is converted from analog to digital and the result stored in the

corresponding A-D register. The speed of A-D conversion depends on the response of the external op-

eration amp. Do not connect the ANEX0 and ANEX1 pins directly. Figure 1.17.9 is an example of how to

connect the pins in external operation amp mode.

Analog
input

External op-amp

ANEX1

ANEX0

Resistor ladder

Successive conversion register

Comparator

Figure 1.17.9. Example of external op-amp connection mode

Mitsubishi microcomputers

M16C / 62A Group

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

D-A Converter

158

D-A Converter

This is an 8-bit, R-2R type D-A converter. The microcomputer contains two independent D-A converters of

this type.

D-A conversion is performed when a value is written to the corresponding D-A register. Bits 0 and 1 (D-A

output enable bits) of the D-A control register decide if the result of conversion is to be output. Do not set the

target port to output mode if D-A conversion is to be performed. When the D-A output is enabled, the pull-

up function of the corresponding port is automatically disabled.

Output analog voltage (V) is determined by a set value (n : decimal) in the D-A register.

V = V

REF

X n/ 256 (n = 0 to 255)

REF

: reference voltage

Table 1.18.1 lists the performance of the D-A converter. Figure 1.18.1 shows the block diagram of the D-A

converter. Figure 1.18.2 shows the D-A control register. Figure 1.18.3 shows the D-A converter equivalent

circuit.

Item

Performance

Conversion method

R-2R method

Resolution

8 bits

Analog output pin

2 channels

Table 1.18.1. Performance of D-A converter

/DA

Data bus low-order bits

D-A register 0 (8)

R-2R resistor ladder

D-A0 output enable bit

D-A register 1 (8)

R-2R resistor ladder

D-A1 output enable bit

(Address 03D8

)

(Address 03DA

)

Figure 1.18.1. Block diagram of D-A converter

Mitsubishi microcomputers

M16C / 62A Group

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

D-A Converter

159

Figure 1.18.2. D-A control register

D-A control register

Symbol

Address

When reset

DACON

03DC

D-A0 output enable bit

DA0E

Bit symbol

Bit name

Function

R W

0 : Output disabled
1 : Output enabled

D-A1 output enable bit

0 : Output disabled
1 : Output enabled

DA1E

Nothing is assigned.
In an attempt to write to these bits, write "0". The value, if read, turns out to be "0"

D-A register

Symbol

Address

When reset

DAi (i = 0,1)

03D8

03DA

Indeterminate

Function

R W

Output value of D-A conversion

REF

DA0

MSB

LSB

D-A0 output enable bit

"0"

"1"

D-A register 0

Note 1: The above diagram shows an instance in which the D-A register is assigned 2A

Note 2: The same circuit as this is also used for D-A1.
Note 3: To reduce the current consumption when the D-A converter is not used, set the D-A output enable bit to 0 and set the D-A register to 00

so that no current flows in the resistors Rs and 2Rs.

"0"

"1"

Figure 1.18.3. D-A converter equivalent circuit

Mitsubishi microcomputers

M16C / 62A Group

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

CRC

160

CRC Calculation Circuit

The Cyclic Redundancy Check (CRC) calculation circuit detects an error in data blocks. The microcom-

puter uses a generator polynomial of CRC_CCITT (X

+ X

+ 1) to generate CRC code.

The CRC code is a 16-bit code generated for a block of a given data length in multiples of 8 bits. The CRC

code is set in a CRC data register each time one byte of data is transferred to a CRC input register after

writing an initial value into the CRC data register. Generation of CRC code for one byte of data is com-

pleted in two machine cycles.

Figure 1.19.1 shows the block diagram of the CRC circuit. Figure 1.19.2 shows the CRC-related registers.

Figure 1.19.3 shows the calculation example using the CRC calculation circuit.

Figure 1.19.2. CRC-related registers

Symbol

Address

When reset

CRCD

03BD

, 03BC

Indeterminate

b0 b7

(b15)

(b8)

CRC data register

CRC calculation result output register

Function

Values that

can be set

0000

to FFFF

Symbo

Address

When reset

CRCIN

03BE

Indeterminate

CRC input register

Data input register

Function

Values that

can be set

to FF

Eight low-order bits

Eight high-order bits

Data bus high-order bits

Data bus low-order bits

CRC data register (16)

CRC input register (8)

CRC code generating circuit

+ x

+ 1

(Addresses 03BD

, 03BC

)

(Address 03BE

)

Figure 1.19.1. Block diagram of CRC circuit

Mitsubishi microcomputers

M16C / 62A Group

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

CRC

161

b15

(1) Setting 0000

CRC data register

CRCD

[03BD

, 03BC

]

b15

(2) Setting 01

CRC input register

CRCIN
[03BE

]

2 cycles
After CRC calculation is complete

CRC data register

CRCD
[03BD

, 03BC

]

1189

Stores CRC code

b15

(3) Setting 23

CRC input register

CRCIN
[03BE

]

After CRC calculation is complete

CRC data register

CRCD
[03BD

, 03BC

]

0A41

Stores CRC code

The code resulting from sending 01

in LSB first mode is (1000 0000). Thus the CRC code in the generating polynomial,

+ X

+ 1), becomes the remainder resulting from dividing (1000 0000) X

by (1 0001 0000 0010 0001) in

conformity with the modulo-2 operation.

Thus the CRC code becomes (1001 0001 1000 1000). Since the operation is in LSB first mode, the (1001 0001 1000 1000)
corresponds to 1189

in hexadecimal notation. If the CRC operation in MSB first mode is necessary in the CRC operation

circuit built in the M16C, switch between the LSB side and the MSB side of the input-holding bits, and carry out the CRC
operation. Also switch between the MSB and LSB of the result as stored in CRC data.

1 0001 0000 0010 0001

1000 0000 0000 0000 0000 0000
1000 1000 0001 0000 1
1000 0001 0000 1000 0
1000 1000 0001 0000 1
1001 0001 1000 1000

1000 1000

LSB

MSB

LSB

MSB

Modulo-2 operation is
operation that complies
with the law given below.

0 + 0 = 0
0 + 1 = 1
1 + 0 = 1
1 + 1 = 0
-1 = 1

Figure 1.19.3. Calculation example using the CRC calculation circuit

Mitsubishi microcomputers

M16C / 62A Group

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

Programmable I/O Port

162

Programmable I/O Ports

There are 87 programmable I/O ports: P0 to P10 (excluding P8

). Each port can be set independently for

input or output using the direction register. A pull-up resistance for each block of 4 ports can be set. P8

an input-only port and has no built-in pull-up resistance.

Figures 1.20.1 to 1.20.4 show the programmable I/O ports. Figure 1.20.5 shows the I/O pins.

Each pin functions as a programmable I/O port and as the I/O for the built-in peripheral devices.

To use the pins as the inputs for the built-in peripheral devices, set the direction register of each pin to input

mode. When the pins are used as the outputs for the built-in peripheral devices (other than the D-A con-

verter), they function as outputs regardless of the contents of the direction registers. When pins are to be

used as the outputs for the D-A converter, do not set the direction registers to output mode. See the

descriptions of the respective functions for how to set up the built-in peripheral devices.

(1) Direction registers

Figure 1.20.6 shows the direction registers.

These registers are used to choose the direction of the programmable I/O ports. Each bit in these regis-

ters corresponds one for one to each I/O pin.

In memory expansion and microprocessor mode, the contents of corresponding direction register of pins

_______

_____

________ ______

________ _______

_______

__________

_________

to A

, D

to D

, CS0 to CS3, RD, WRL/WR, WRH/BHE, ALE, RDY, HOLD, HLDA and BCLK cannot

be modified.

Note: There is no direction register bit for P8

(2) Port registers

Figure 1.20.7 shows the port registers.

These registers are used to write and read data for input and output to and from an external device. A

port register consists of a port latch to hold output data and a circuit to read the status of a pin. Each bit

in port registers corresponds one for one to each I/O pin.

In memory expansion and microprocessor mode, the contents of corresponding port register of pins A

_______

________ _____

________ ______

________ ________

_______

__________

_________

, D

to D

, CS0 to CS3, RD, WRL/WR, WRH/BHE, ALE, RDY, HOLD, HLDA and BCLK cannot be

modified.

(3) Pull-up control registers

Figure 1.20.8 shows the pull-up control registers.

The pull-up control register can be set to apply a pull-up resistance to each block of 4 ports. When ports

are set to have a pull-up resistance, the pull-up resistance is connected only when the direction register is

set for input.

However, in memory expansion mode and microprocessor mode, the pull-up control register of P0 to P3,

to P4

, and P5 is invalid. The contents of register can be changed, but the pull-up resistance is not

connected.

(4) Port control register

Figure 1.20.9 shows the port control register.

The bit 0 of port control register is used to read port P1 as follows:

0 : When port P1 is input port, port input level is read.

When port P1 is output port , the contents of port P1 register is read.

1 : The contents of port P1 register is read always.

This register is valid in the following:

· External bus width is 8 bits in microprocessor mode or memory expansion mode.

· Port P1 can be used as a port in multiplexed bus for the entire space.

Mitsubishi microcomputers

M16C / 62A Group

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

Programmable I/O Port

167

Figure 1.20.6. Direction register

Port Pi direction register (Note 1, 2)

Symbol

Address

When reset

PDi (i = 0 to 10, except 8)

03E2

, 03E3

, 03E6

, 03E7

, 03EA

03EB

, 03EE

, 03EF

, 03F3

, 03F6

Bit name

Function

Bit symbol

PDi_0

Port Pi

direction register

PDi_1

Port Pi

direction register

PDi_2

Port Pi

direction register

PDi_3

Port Pi

direction register

PDi_4

Port Pi

direction register

PDi_5

Port Pi

direction register

PDi_6

Port Pi

direction register

PDi_7

Port Pi

direction register

0 : Input mode

(Functions as an input port)

1 : Output mode

(Functions as an output port)

(i = 0 to 10 except 8)

Port P8 direction register

Symbol

Address

When reset

PD8

03F2

00X00000

Bit name

Function

Bit symbol

PD8_0

Port P8

direction register

PD8_1

Port P8

direction register

PD8_2

Port P8

direction register

PD8_3

Port P8

direction register

PD8_4

Port P8

direction register

Nothing is assigned.
In an attempt to write to this bit, write "0". The value, if read, turns out to be
indeterminate.

PD8_6

Port P8

direction register

PD8_7

Port P8

direction register

0 : Input mode

(Functions as an input port)

1 : Output mode

(Functions as an output port)

0 : Input mode

(Functions as an input port)

1 : Output mode

(Functions as an output port)

Note 2: In memory expansion and microprocessor mode, the contents of

corresponding port Pi direction register of pins A

to A

, D

to D

to CS

, RD, WRL/WR, WRH/BHE, ALE, RDY, HOLD, HLDA and

BCLK cannot be modified.

Note 1: Set bit 2 of protect register (address 000A

) to "1" before rewriting to

the port P9 direction register.

Mitsubishi microcomputers

M16C / 62A Group

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

Programmable I/O Port

168

Port Pi register (Note 2)

Symbol

Address

When reset

Pi (i = 0 to 10, except 8)

03E0

, 03E1

, 03E4

, 03E5

, 03E8

Indeterminate

03E9

, 03EC

, 03ED

, 03F1

, 03F4

Indeterminate

Bit name

Function

Bit symbol

Pi_0

Port Pi

Pi_1

Port Pi

Pi_2

Port Pi

Pi_3

Port Pi

Pi_4

Port Pi

Pi_5

Port Pi

Pi_6

Port Pi

Pi_7

Port Pi

Data is input and output to and from
each pin by reading and writing to
and from each corresponding bit
0 : "L" level data
1 : "H" level data (Note 1)

(i = 0 to 10 except 8)

Port P8 register

Symbol

Address

When reset

03F0

Indeterminate

Bit name

Function

Bit symbol

P8_0

Port P8

P8_1

Port P8

P8_2

Port P8

P8_3

Port P8

P8_4

Port P8

P8_5

Port P8

P8_6

Port P8

P8_7

Port P8

Data is input and output to and from
each pin by reading and writing to
and from each corresponding bit
(except for P8

)

0 : "L" level data
1 : "H" level data

Note 1:

Since P7

and P7

are N-channel open drain ports, the data is high-impedance.

Note 2: In memory expansion and microprocessor mode, the contents of

corresponding port Pi register of pins A

to A

, D

to D

, CS

to CS

RD, WRL/WR, WRH/BHE, ALE, RDY, HOLD, HLDA and BCLK cannot
be modified.

Figure 1.20.7. Port register

Mitsubishi microcomputers

M16C / 62A Group

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

Programmable I/O Port

169

Figure 1.20.8. Pull-up control register

Pull-up control register 0 (Note)

Symbol

Address

When reset

PUR0

03FC

Bit name

Function

Bit symbol

PU00

to P0

pull-up

PU01

to P0

pull-up

PU02

to P1

pull-up

PU03

to P1

pull-up

PU04

to P2

pull-up

PU05

to P2

pull-up

PU06

to P3

pull-up

PU07

to P3

pull-up

The corresponding port is pulled
high with a pull-up resistor
0 : Not pulled high
1 : Pulled high

Pull-up control register 1

Symbol

Address

When reset

PUR1

03FD

(Note 2)

Bit name

Function

Bit symbol

PU10

to P4

pull-up (Note 3)

PU11

to P4

pull-up

PU12

to P5

pull-up (Note 3)

PU13

to P5

pull-up

PU14

to P6

pull-up

PU15

to P6

pull-up

PU16

to P7

pull-up (Note 1)

PU17

to P7

pull-up

The corresponding port is pulled
high with a pull-up resistor
0 : Not pulled high
1 : Pulled high

Note 1: Since P7

and P7

are N-channel open drain ports, pull-up is not available for them.

Note 2: When the V

level is being impressed to the CNV

terminal, this register becomes

to 02

when reset (PU11 becomes to "1").

Pull-up control register 2

Symbol

Address

When reset

PUR2

03FE

Bit name

Function

Bit symbol

PU20

to P8

pull-up

PU21

to P8

pull-up

(Except P8

)

PU22

to P9

pull-up

PU23

to P9

pull-up

PU24

P10

to P10

pull-up

PU25

P10

to P10

pull-up

Nothing is assigned.
In an attempt to write to these bits, write "0". The value, if read, turns out to be "0".

The corresponding port is pulled
high with a pull-up resistor
0 : Not pulled high
1 : Pulled high

Note 3: In memory expansion and microprocessor mode, the content of these bits can be

changed, but the pull-up resistance is not connected.

Note : In memory expansion and microprocessor mode, the content of this register

can be changed, but the pull-up resistance is not connected.

Mitsubishi microcomputers

M16C / 62A Group

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

Programmable I/O Port

171

Pin name

Connection

Ports P0 to P10
(excluding P8

)

OUT

(Note)

, V

REF

, BYTE

After setting for input mode, connect every pin to V

via a resistor

(pull-down); or after setting for output mode, leave these pins open.

Open

Connect to V

Note: With external clock input to X

pin.

NMI

Connect via resistor to V

(pull-up)

Table 1.20.1. Example connection of unused pins in single-chip mode

Pin name

Connection

Ports P6 to P10
(excluding P8

)

, V

REF

After setting for input mode, connect every pin to V

via a resistor

(pull-down); or after setting for output mode, leave these pins open.

Open

Connect to V

Note 1: With external clock input to X

pin.

Note 2: When the BCLK output disable bit (bit 7 at address 0004

) is set to "1", connect to V

via a resistor (pull-up).

HOLD, RDY, NMI

Connect via resistor to V

(pull-up)

BHE, ALE, HLDA,
X

OUT

(Note 1), BCLK (Note 2)

/ CS1 to P4

/ CS3

Set ports to input mode, set output enable bits of CS1 through CS3 to
0, and connect to Vcc via resistors (pull-up).

Figure 1.20.10. Example connection of unused pins

Port P0 to P10 (except for P8

)

(Input mode)

(Output mode)

NMI

OUT

BYTE

REF

Microcomputer

In single-chip mode

Port P6 to P10 (except for P8

)

(Input mode)

(Output mode)

NMI

OUT

REF

Open

Microcomputer

In memory expansion mode or
in microprocessor mode

HOLD

RDY

ALE

BCLK (Note)

BHE

HLDA

Open

Port P4

/ CS1

to P4

/ CS3

Note : When the BCLK output disable bit (bit 7 at address 0004

) is set to "1", connect to V

via a resistor (pull-up).

Table 1.20.2. Example connection of unused pins in memory expansion mode and microprocessor mode

Mitsubishi microcomputers

M16C / 62A Group

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

Electrical characteristics

173

Table 1.23.1. Absolute maximum ratings

Note : Specify a product of -40

C to 85

C to use it.

REF

, X

OUT

-0.3 to Vcc+0.3

Topr=25

-0.3 to 6.5

AVcc

Vcc

stg

opr

-65 to 150

300

-20 to 85 / -40 to 85 (Note)

to P3

, P4

to P4

, P5

to P5

to P6

, P7

to P7

, P8

to P8

to P0

, P1

to P1

, P2

to P2

to P3

,P4

to P4

, P5

to P5

to P6

,P7

to P7

, P8

to P8

to P0

, P1

to P1

, P2

to P2

RESET,

to P9

, P10

to P10

, P8

, P9

to P9

, P10

to P10

, P7

-0.3 to 6.5

CNV

, BYTE,

=AV

C
C

Symbol

Parameter

Condition

Rated value

Unit

Supply voltage

Analog supply voltage

Input
voltage

Output
voltage

Power dissipation

Operating ambient temperature

Storage temperature

Mitsubishi microcomputers

M16C / 62A Group

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

Electrical characteristics

174

Note 1: The mean output current is the mean value within 100ms.

Note 2: The total I

(peak) for ports P0, P1, P2, P8

, P8

, P9, and P10 must be 80mA max. The total I

(peak) for ports P0, P1,

P2, P8

, P8

, P9, and P10 must be 80mA max. The total I

(peak) for ports P3, P4, P5, P6, P7, and P8

to P8

must be

80mA max. The total I

(peak) for ports P3, P4, P5, P6, P7

to P7

, and P8

to P8

must be 80mA max.

Note 3: Specify a product of -40

C to 85

C to use it.

Note 4: Relationship between main clock oscillation frequency and supply voltage.

Table 1.23.2. Recommended operating conditions (referenced to V

= 2.7V to 5.5V at Topr = 20

to 85

C / 40

C to 85

C(Note 3) unless otherwise specified)

Main clock input oscillation frequency

(Mask ROM, Flash memory 5V version, No wait)

16.0

5.0

0.0

2.7

4.2

5.5

Operating maximum

frequency

[MH

]

Supply voltage

[V]

(BCLK: no division)

7.33 X V

- 14.791MH

Main clock input oscillation frequency

(Mask ROM, Flash memory 5V version, With wait)

16.0

10.0

0.0

2.7

4.2

5.5

Operating maximum

frequency

[MH

]

Supply voltage

[V]

(BCLK: no division)

4 X V

- 0.8MH

2.7

5.5

Vcc

5.0

Vcc

AVcc

0
0

OH (avg)

Vss

AVss

0.8Vcc

0.5Vcc

Vcc

0.2Vcc

(data input function during memory expansion and microprocessor modes)

0.16Vcc

OH (peak)

to P7

, P8

to P8

, P9

to P9

, P10

to P10

-5.0

-10.0

to P0

, P1

to P1

, P2

to P2

, P3

(during single-chip mode)

to P0

, P1

to P1

, P2

to P2

, P3

to P0

, P1

to P1

to P2

, P3

to P3

to P4

, P5

to P5

to P6

, P7

to P7

to P8

, P8

, P9

to P9

, P10

to P10

to P3

, P4

to P4

, P5

to P5

to P6

10.0

5.0

)

OL (peak)

OL (avg)

(Xc

)

kHz

32.768

, RESET, CNV

, BYTE

to P7

, P8

to P8

, P9

to P9

, P10

to P10

to P3

, P4

to P4

, P5

to P5

to P6

, RESET, CNV

, BYTE

(data input function during memory expansion and microprocessor modes)

to P0

, P1

to P1

, P2

to P2

, P3

(during single-chip mode)

to P0

, P1

to P1

, P2

to P2

, P3

to P0

, P1

to P1

to P2

, P3

to P3

to P4

, P5

to P5

to P6

, P7

to P7

to P8

, P8

, P9

to P9

, P10

to P10

to P0

, P1

to P1

to P2

, P3

to P3

to P4

, P5

to P5

to P6

, P7

to P7

to P8

, P8

, P9

to P9

, P10

to P10

to P0

, P1

to P1

to P2

, P3

to P3

to P4

, P5

to P5

to P6

, P7

to P7

to P8

, P8

, P9

to P9

, P10

to P10

0.8Vcc

6.5

Mask ROM version,
Flash memory 5V
version (Note 5)

7.33 X Vcc

-14.791

4 X Vcc

-0.8

Vcc=4.2V to 5.5V

Vcc=2.7V to 4.2V

Vcc=4.2V to 5.5V

Vcc=2.7V to 4.2V

MHz

Symbol

Parameter

Unit

Standard

Min

Typ.

Max.

Supply voltage

Analog supply voltage
Supply voltage
Analog supply voltage

HIGH input
voltage

LOW input
voltage

HIGH peak output
current

HIGH average output
current

LOW peak output
current

LOW average
output current

Main clock input
oscillation frequency

Subclock oscillation frequency

With wait

No wait

Mask ROM version,
Flash memory 5V
version (Note 5)

Note 5: Execute case without wait, program / erase of flash memory by V

=4.2V to 5.5V and f(BCLK)

6.25 MHz. Execute case

with wait, program / erase of flash memory by V

=4.2V to 5.5V and f(BCLK)

12.5 MHz.

Mitsubishi microcomputers

M16C / 62A Group

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

Electrical characteristics (Vcc = 5V)

175

= 5V

Table 1.23.3. A-D conversion characteristics (referenced to V

= AV

= V

REF

= 2.7V to 5.5V, Vss = AV

0V at Topr = 20

C to 85

C / 40

C to 85

C (Note 4) unless otherwise specified)

µs

Standard

Min.

Typ. Max.

Resolution

Absolute
accuracy

Bits

LSB

REF

±3

Symbol

Parameter

Measuring condition

Unit

REF

= V

= 5V

LADDER

CONV

Ladder resistance

Conversion time(10bit), Sample & hold function available

Reference voltage

Analog input voltage

REF

2.7

REF

3.3

2.8

CONV

SAMP

Sampling time

0.3

REF

Sample & hold function not available

Sample & hold function available(10bit)

to AN

input

ANEX0, ANEX1 input,

External op-amp connection mode

REF

= 5V

LSB

±7

Sample & hold function available(8bit)

REF

= V

= 5V

±2

LSB

Min.

Typ.

Max.

Resolution
Absolute accuracy
Setup time
Output resistance
Reference power supply input current

Bits

VREF

1.0

1.5

Symbol

Parameter

Measuring condition

Unit

µs

(Note 1)

Standard

µs

±3

Note 1: Do f(X

) in range of main clock input oscillation frequency prescribed with recommended operating

conditions of table 1.23.2. Divide the f

if f(X

) exceeds 10MHz, and make AD operation clock frequency

(ØAD) equal to or lower than 10MHz. And divide the f

if V

is less than 4.2V, and make AD operation

clock frequency (ØAD) equal to or lower than f

/2.

Note 2: A case without sample & hold function turn AD operation clock frequency (ØAD) into 250 kHz or more in

addition to a limit of Note 1.

A case with sample & hold function turn AD operation clock frequency (ØAD) into 1MHz or more in addition

to a limit of Note 1.

Note 3: Connect AV

pin to V

pin and apply the same electric potential.

Note 4: Specify a product of -40°C to 85°C to use it.

Sample & hold function not available(8bit)

REF

= V

= 3V, Ø

= f

±2

LSB

Conversion time(8bit), Sample & hold function available

REF

= V

= 5V, Ø

=10MHz

REF

= V

= 5V, Ø

=10MHz

9.8

CONV

µs

Conversion time(8bit), Sample & hold function not available

REF

= V

= 3V, Ø

= f

/2 = 5MHz

Page program time

Block erase time

Erase all unlocked blocks time

Lock bit program time

50 X n (Note)

120

600

600 X n (Note)

120

Parameter

Standard

Min.

Typ.

Max

Unit

Note 1: This applies when using one D-A converter, with the D-A register for the unused D-A converter set to
"00

The A-D converter's ladder resistance is not included.

Also, when D-A register contents are not "00

", the current I

VREF

always flows even though Vref may

have been set to be unconnected by the A-D control register.

Note 2: Specify a product of -40°C to 85°C to use it.

Note : n denotes the number of block erases.

Table 1.23.4. D-A conversion characteristics (referenced to V

= V

REF

= 2.7V to 5.5V, V

= AV

0V, at Topr = 20

C to 85

C / 40

C to 85

C (Note 2) unless otherwise specified)

Table 1.23.5. Flash memory version electrical characteristics

(referenced to V

= 4.2V to 5.5V, at Topr =0 to 60

C unless otherwise specified)

Mitsubishi microcomputers

M16C / 62A Group

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

Electrical characteristics (Vcc = 5V)

176

= 5V

Table 1.23.6. Electrical characteristics (referenced to V

= 4.2V to 5.5V, V

= 0V at Topr = 20

to 85

C / 40

C to 85

C (Note 2), f(X

) = 16MH

unless otherwise specified)

OUT

2.0

= -5mA

= -1mA

= -200µA

= -0.5mA

= 5mA

= 1mA

= 200µA

= 0.5mA

to P3

, P4

to P4

, P5

to P5

HIGHPOWER

LOWPOWER

COUT

3.0

to P6

, P7

to P7

, P8

to P8

, P8

, P9

to P9

, P10

to P10

T+-

T-

COUT

HIGHPOWER

LOWPOWER

Typ.

Hysteresis

With no load applied

to P0

, P1

to P1

, P2

to P2

to P3

, P4

to P4

, P5

to P5

to P6

, P7

to P7

, P8

to P8

to P9

, P10

to P10

, RESET, CNVss, BYTE

= 5V

= 0V

-5.0

f(X

) = 16MHz

(

)

90.0

µA

1.0

PULLUP

50.0

to P0

, P1

to P1

, P2

to P2

to P3

, P4

to P4

, P5

to P5

to P6

, P7

to P7

, P8

to P8

, P8

, P9

to P9

, P10

to P10

= 0V

30.0

167.0

Hysteresis

HIGH input
current

LOW input
current

Pull-up
resistance

Feedback resistance

RAM retention voltage

Square wave, no division

Square wave

Mask ROM version

f(X

) = 16MHz

Square wave, no division

f(X

CIN

) = 32kHz

Square wave, in RAM

TB0

to TB5

, INT

to INT

, NMI,

to KI

, RxD

to RxD

, S

IN3

, S

IN4

1.0

µA

4.0

µA

f(X

CIN

) = 32kHz

Topr = 25

when clock is stopped

When a WAIT instruction
is executed (Note 1)

f(X

CIN

) = 32kHz

2.2

Square wave, in flash memory

Flash memory 5V
version

µA

f(X

) = 16MHz

Square wave, Division by 4

f(X

) = 16MHz

Square wave, Division by 4

(

)

Mitsubishi microcomputers

M16C / 62A Group

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

Timing (Vcc = 5V)

177

Timing requirements (referenced to V

= 5V, V

= 0V at Topr = 20

C to 85

C / 40

C to 85

C (*)

unless otherwise specified)

* : Specify a product of -40

C to 85

C to use it.

f(BCLK) X 2

(Note)

Note: Calculated according to the BCLK frequency as follows:

Max.

External clock rise time

Min.

External clock input cycle time
External clock input HIGH pulse width

External clock input LOW pulse width

External clock fall time

w(H

)

w(L)

Parameter

Symbol

Unit

Standard

62.5

Min.

Data input setup time

su(DB-RD)

su(RDY-BCLK )

Parameter

Symbol

Unit

Max.

Standard

RDY input setup time

Data input hold time

h(RD-DB)

h(BCLK -RDY)

RDY input hold time

HOLD input setup time

su(HOLD-BCLK )

HOLD input hold time

h(BCLK-HOLD )

Data input access time (no wait)

ac1(RD-DB)

ac2(RD-DB)

ac3(RD-DB)

Data input access time (with wait)
Data input access time (when accessing multiplex bus area)

d(BCLK-HLDA )

HLDA output delay time

ac1(RD DB) =

f(BCLK) X 2

[ns]

ac2(RD DB) =

f(BCLK) X 2

3 X 10

[ns]

ac3(RD DB) =

3 X 10

[ns]

= 5V

Table 1.23.8. Memory expansion and microprocessor modes

Table 1.23.7. External clock input

Mitsubishi microcomputers

M16C / 62A Group

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

Timing (Vcc = 5V)

178

Standard

Max.

TAi

input LOW pulse width

w(TAL)

Min.

Unit

Standard

Max.

Min.

Unit

Standard

Max.

Min.

Unit

Standard

Max.

Min.

Unit

Standard

Max.

Min.

Unit

TAi

input HIGH pulse width

w(TAH)

Parameter

Symbol

TAi

input cycle time

TAi

input HIGH pulse width

TAi

input LOW pulse width

c(TA)

w(TAH)

w(TAL)

Symbol

Parameter

TAi

input cycle time

TAi

input HIGH pulse width

TAi

input LOW pulse width

c(TA)

w(TAH)

w(TAL)

Symbol

Parameter

w(TAH)

w(TAL)

Symbol

Parameter

TAi

input HIGH pulse width

TAi

input LOW pulse width

Symbol

Parameter

c(TA)

TAi

input cycle time

TAi

OUT

input cycle time

TAi

OUT

input HIGH pulse width

TAi

OUT

input LOW pulse width

TAi

OUT

input setup time

TAi

OUT

input hold time

c(UP)

w(UPH)

w(UPL)

su(UP-T

)

h(T

IN-

UP)

100

400

200

100

2000

1000

400

Timing requirements (referenced to V

= 5V, V

= 0V at Topr = 20

C to 85

C / 40

C to 85

C (*)

unless otherwise specified)

* : Specify a product of -40

C to 85

C to use it.

Table 1.23.10. Timer A input (gating input in timer mode)

Table 1.23.11. Timer A input (external trigger input in one-shot timer mode)

Table 1.23.12. Timer A input (external trigger input in pulse width modulation mode)

Table 1.23.13. Timer A input (up/down input in event counter mode)

= 5V

Table 1.23.9. Timer A input (counter input in event counter mode)

Mitsubishi microcomputers

M16C / 62A Group

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

Timing (Vcc = 5V)

179

Timing requirements (referenced to V

= 5V, V

= 0V at Topr = 20

C to 85

C / 40

C to 85

C (*)

unless otherwise specified)

* : Specify a product of -40

C to 85

C to use it.

Standard

Max.

Min.

TBi

input cycle time (counted on one edge)

TBi

input HIGH pulse width (counted on one edge)

TBi

input LOW pulse width (counted on one edge)

c(TB)

w(TBH)

w(TBL)

Parameter

Symbol

Unit

c(TB)

w(TBL)

w(TBH)

TBi

input HIGH pulse width (counted on both edges)

TBi

input LOW pulse width (counted on both edges)

TBi

input cycle time (counted on both edges)

Standard

Max.

Min.

c(TB)

w(TBH)

Symbol

Parameter

Unit

w(TBL)

TBi

input HIGH pulse width

TBi

input cycle time

TBi

input LOW pulse width

Standard

Max.

Min.

c(TB)

Symbol

Parameter

Unit

w(TBL)

w(TBH)

TBi

input cycle time

TBi

input HIGH pulse width

TBi

input LOW pulse width

Standard

Max.

Min.

c(AD)

w(ADL)

Symbol

Parameter

Unit

TRG

input cycle time (trigger able minimum)

TRG

input LOW pulse width

Standard

Max.

Min.

w(INH)

w(INL)

Symbol

Parameter

Unit

INTi input LOW pulse width

INTi input HIGH pulse width

Standard

Max.

Min.

CLKi input cycle time

CLKi input HIGH pulse width

CLKi input LOW pulse width

c(CK)

w(CKH)

w(CKL)

Parameter

Symbol

Unit

d(C-Q)

su(D-C)

h(C-Q)

TxDi hold time

RxDi input setup time

TxDi output delay time

h(C-D)

RxDi input hold time

100

200

400

200

400

200

1000

125

250

200

100

= 5V

Table 1.23.17. A-D trigger input

_______

Table 1.23.19. External interrupt INTi inputs

Table 1.23.15. Timer B input (pulse period measurement mode)

Table 1.23.16. Timer B input (pulse width measurement mode)

Table 1.23.18. Serial I/O

Table 1.23.14. Timer B input (counter input in event counter mode)

Mitsubishi microcomputers

M16C / 62A Group

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

Timing (Vcc = 5V)

180

Symbol

Standard

Measuring condition

Max.

Min.

Parameter

Unit

d(BCLK-AD)

Address output delay time

h(BCLK-AD)

Address output hold time (BCLK standard)

h(BCLK-CS)

Chip select output hold time (BCLK standard)

d(BCLK-ALE)

ALE signal output delay time

h(BCLK-ALE)

ALE signal output hold time

d(BCLK-RD)

RD signal output delay time

h(BCLK-RD)

RD signal output hold time

d(BCLK-WR)

WR signal output delay time

h(BCLK-WR)

WR signal output hold time

d(BCLK-DB)

Data output delay time (BCLK standard)

h(BCLK-DB)

Data output hold time (BCLK standard)

h(WR-DB)

Data output hold time (WR standard)(Note2)

d(DB-WR)

Data output delay time (WR standard)

(Note1)

Note 1: Calculated according to the BCLK frequency as follows:

td(DB WR) =

f(BCLK) X 2

[ns]

d(BCLK-CS)

Chip select output delay time

h(RD-AD)

Address output hold time (RD standard)

h(WR-AD)

Address output hold time (WR standard)

Note 2: This is standard value shows the timing when the output is off,

and doesn't show hold time of data bus.
Hold time of data bus is different by capacitor volume and pull-up
(pull-down) resistance value.
Hold time of data bus is expressed in

t = CR X ln (1 V

/ V

)

by a circuit of the right figure.

For example, when V

= 0.2V

, C = 30pF, R = 1k

, hold time

of output "L" level is

t = 30pF X 1k

X ln (1 0.2V

/ V

)

= 6.7ns.

DBi

Note 3: Specify a product of -40°C to 85°C to use it.

Switching characteristics (referenced to V

= 5V, V

= 0V at Topr = 20

C to 85

C / 40

C to

C (Note 3), CM15 = "1" unless otherwise specified)

= 5V

Figure 1.23.1

Table 1.23.20. Memory expansion mode and microprocessor mode (no wait)

Figure 1.23.1. Port P0 to P10 measurement circuit

P10

30pF

Mitsubishi microcomputers

M16C / 62A Group

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

Timing (Vcc = 5V)

181

Switching characteristics (referenced to V

= 5V, V

= 0V at Topr = 20

C to 85

C / 40

C to

C (Note 3), CM15 = "1" unless otherwise specified)

= 5V

Figure 1.23.1

Table 1.23.21. Memory expansion mode and microprocessor mode

(with wait, accessing external memory)

Symbol

Standard

Measuring condition

Max.

Min.

Parameter

Unit

d(BCLK-AD)

Address output delay time

h(BCLK-AD)

Address output hold time (BCLK standard)

h(BCLK-CS)

Chip select output hold time (BCLK standard)

d(BCLK-ALE)

ALE signal output delay time

h(BCLK-ALE)

ALE signal output hold time

d(BCLK-RD)

RD signal output delay time

h(BCLK-RD)

RD signal output hold time

d(BCLK-WR)

WR signal output delay time

h(BCLK-WR)

WR signal output hold time

d(BCLK-DB)

Data output delay time (BCLK standard)

h(BCLK-DB)

Data output hold time (BCLK standard)

h(WR-DB)

Data output hold time (WR standard)(Note2)

d(DB-WR)

Data output delay time (WR standard)

(Note1)

Note 1: Calculated according to the BCLK frequency as follows:

td(DB WR) =

f(BCLK)

[ns]

d(BCLK-CS)

Chip select output delay time

h(RD-AD)

Address output hold time (RD standard)

h(WR-AD)

Address output hold time (WR standard)

Note 2: This is standard value shows the timing when the output is off,

and doesn't show hold time of data bus.
Hold time of data bus is different by capacitor volume and pull-up
(pull-down) resistance value.
Hold time of data bus is expressed in

t = CR X ln (1 V

/ V

)

by a circuit of the right figure.

For example, when V

= 0.2V

, C = 30pF, R = 1k

, hold time

of output "L" level is

t = 30pF X 1k

X ln (1 0.2V

/ V

)

= 6.7ns.

DBi

Note 3: Specify a product of -40°C to 85°C to use it.

Mitsubishi microcomputers

M16C / 62A Group

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

Timing (Vcc = 5V)

182

Switching characteristics (referenced to V

= 5V, V

= 0V at Topr = 20

C to 85

C / 40

C to

C (Note 2), CM15 = "1" unless otherwise specified)

= 5V

Table 1.23.22. Memory expansion mode and microprocessor mode

(with wait, accessing external memory, multiplex bus area selected)

Symbol

Standard

Measuring condition

Max.

Min.

Parameter

Unit

d(BCLK-AD)

Address output delay time

h(BCLK-AD)

Address output hold time (BCLK standard)

d(BCLK-CS)

Chip select output delay time

h(BCLK-CS)

Chip select output hold time (BCLK standard)

h(RD-AD)

Address output hold time (RD standard)

(Note1)

d(BCLK-RD)

RD signal output delay time

h(BCLK-RD)

RD signal output hold time

h(WR-AD)

Address output hold time (WR standard)

(Note1)

d(BCLK-WR)

WR signal output delay time

d(BCLK-DB)

Data output delay time (BCLK standard)

h(BCLK-DB)

Data output hold time (BCLK standard)

d(DB-WR)

Data output delay time (WR standard)

(Note1)

d(BCLK-ALE)

ALE signal output delay time (BCLK standard)

h(BCLK-ALE)

ALE signal output hold time (BCLK standard)

h(ALE-AD)

ALE signal output hold time (Adderss standard)

h(BCLK-WR)

WR signal output hold time

h(RD-CS)

Chip select output hold time (RD standard)

(Note1)

h(WR-CS)

Chip select output hold time (WR standard)

(Note1)

d(AD-RD)

Post-address RD signal output delay time

d(AD-WR)

Post-address WR signal output delay time

dZ(RD-AD)

Address output floating start time

h(WR-DB)

Data output hold time (WR standard)

(Note1)

Note 1: Calculated according to the BCLK frequency as follows:

th(RD AD) =

f(BCLK) X 2

[ns]

th(WR AD) =

f(BCLK) X 2

[ns]

th(RD CS) =

f(BCLK) X 2

[ns]

th(WR CS) =

f(BCLK) X 2

[ns]

td(DB WR) =

f(BCLK) X 2

[ns]

X 3

td(AD ALE) =

f(BCLK) X 2

[ns]

th(WR DB) =

f(BCLK) X 2

[ns]

d(AD-ALE)

ALE signal output delay time (Address standard)

(Note1)

Note 2: Specify a product of -40°C to 85°C to use it.

Figure 1.23.1

Mitsubishi microcomputers

M16C / 62A Group

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

Timing (Vcc = 5V)

186

BCLK

CSi

ALE

4ns.min

HiZ

40ns.min

0ns.min

ADi

BHE

Read timing

BCLK

CSi

ALE

4ns.min

h(WRAD)

ADi

BHE

(tcyc40)ns.min

0ns.min

DBi

Write timing

d(BCLKRD)

0ns.min

h(RDAD)

Memory Expansion Mode and Microprocessor Mode

(When accessing external memory area with wait)

Measuring conditions :
· V

=5V

· Input timing voltage : Determined with: V

=0.8V, V

=2.5V

· Output timing voltage : Determined with: V

=0.8V, V

=2.0V

WR,WRL,

WRH

d(BCLKCS)

25ns.max

tcyc

h(BCLKCS)

4ns.min

h(RDCS)

0ns.min

h(BCLKAD)

d(BCLKAD)

25ns.max

d(BCLKALE) 25ns.max

h(BCLKALE)

4ns.min

h(BCLKRD)

0ns.min

25ns.max

ac2(RDDB)

h(RDDB)

SU(DBRD)

d(BCLKCS)

25ns.max

tcyc

h(BCLKCS)

4ns.min

h(WRCS)

0ns.min

h(BCLKAD)

d(BCLKAD)

25ns.max

d(BCLKALE)

25ns.max

h(BCLKALE)

4ns.min

h(BCLKWR)

0ns.min

d(BCLKWR)

25ns.max

h(BCLKDB)

4ns.min

d(BCLKDB)

40ns.max

d(DBWR)

h(WRDB)

= 5V

Figure 1.23.5. V

= 5V timing diagram (4)

Mitsubishi microcomputers

M16C / 62A Group

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

Timing (Vcc = 5V)

187

Memory Expansion Mode and Microprocessor Mode

(When accessing external memory area with wait, and select multiplexed bus)

BCLK

CSi

ALE

4ns.min

tcyc

ADi
BHE

ADi
/DBi

d(ADALE)

Read timing

0ns.min

BCLK

CSi

ALE

4ns.min

tcyc

ADi

BHE

ADi
/DBi

Write timing

Address

Measuring conditions :
· V

=5V

· Input timing voltage : Determined with

=0.8V, V

=2.5V

· Output timing voltage : Determined with V

=0.8V, V

=2.0V

(tcyc/2)ns.min

Address

Data input

(tcyc/2)ns.min

d(BCLKALE)

(tcyc/2)ns.min

h(WRCS)

Address

(tcyc*3/240)ns.min

d(BCLKALE)

(tcyc/2)ns.min

(tcyc/2-25)ns.min

Address

25ns.max

SU(DBRD)

tac3(RDDB)

(tcyc/2)ns.min

h(ALEAD)

30ns.min

d(ADRD)

0ns.min

dz(RDAD)

8ns.max

d(ADWR)

0ns.min

Data output

WR,WRL,

WRH

d(BCLKCS)

25ns.max

h(RDCS)

h(BCLKCS)

4ns.min

h(BCLKAD)

h(RDDB)

0ns.min

40ns.min

25ns.max

d(BCLKAD)

4ns.min

h(BCLKALE)

d(BCLKRD)

25ns.max

h(RDAD)

h(BCLKRD)

0ns.min

d(BCLKCS)

25ns.max

h(BCLKCS)

h(BCLKDB)

4ns.min

h(WRDB)

d(DBWR)

h(BCLKAD)

d(ADALE)
(tcyc/225)ns.min

d(BCLKAD)

25ns.max

h(BCLKALE)

25ns.max

d(BCLKWR)

h(BCLKWR)

h(WRAD)

d(BCLKDB)

40ns.max

= 5V

Figure 1.23.6. V

= 5V timing diagram (5)

Mitsubishi microcomputers

M16C / 62A Group

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

Electrical characteristics (Vcc = 3V)

188

Measuring condition

2.5

OUT

= -50µA

LOWPOWER

e X

RAM

RAM retention voltage

Icc

Power supply current

T+-

T-

0.2

0.8

0.2

1.8

to P0

, P1

to P1

, P2

to P2

to P3

, P4

to P4

,P5

to P5

to P6

, P7

to P7

, P8

to P8

to P9

, P10

to P10

4.0

µA

When clock is stopped

RESET

= 3V

= 0V

-4.0

to P0

, P1

to P1

, P2

to P2

to P3

, P4

to P4

, P5

to P5

to P6

, P7

to P7

, P8

to P8

to P9

, P10

to P10

Square wave

f(X

CIN

) = 32kHz

40.0

Feedback resistance

CIN

Square wave, no division

f(X

) = 10MHz

Mask ROM
version

120.0

LOW output voltage

COUT

LOWPOWER

66.0

500.0

In single-chip
mode, the
output pins are
open and other
pins are V

Pull-up
resistance

f(X

) = 10MHz

Square wave, in RAM

f(X

CIN

) = 32kHz

µA

Flash memory
5V version

CLK

to CLK

,TA2

OUT

to TA4

OUT

TRG

, CTS

to CTS

, SCL, SDA

µA

20.0

f(X

CIN

) = 32kHz

f(X

CIN

) = 32kHz

(

)

(

)

f(X

CIN

) = 32kHz

40.0

(Topr
= 25

= 3V

Table 1.23.23. Electrical characteristics (referenced to V

= 2.7 to 3.3V, V

= 0V at Topr = 20

to 85

C / 40

C to 85

C (Note 1), f(X

) = 10MH

(Note 2) with wait unless otherwise

specified)

Mitsubishi microcomputers

M16C / 62A Group

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

Timing (Vcc = 3V)

189

Min.

Data input setup time

su(DB-RD)

su(RDY-BCLK )

Parameter

Symbol

Unit

Max.

Standard

RDY input setup time

Data input hold time

h(RD-DB)

h(BCLK -RDY)

RDY input hold time

HOLD input setup time

su(HOLD-BCLK )

HOLD input hold time

h(BCLK-HOLD )

Data input access time (no wait)

ac1(RD-DB)

ac2(RD-DB)

ac3(RD-DB)

Data input access time (with wait)
Data input access time (when accessing multiplex bus area)

HLDA output delay time

d(BCLK-HLDA)

(Note)

Note: Calculated according to the BCLK frequency as follows:

100

ns
ns

w(H

)

w(L)

Max.

Min.

Parameter

Symbol

Unit

Standard

External clock rise time

External clock input
cycle time

External clock input
HIGH pulse width

External clock input
LOW pulse width

External clock fall time

ac1(RD DB) =

f(BCLK) X 2

[ns]

ac2(RD DB) =

f(BCLK) X 2

3 X 10

[ns]

ac3(RD DB) =

f(BCLK) X 2

3 X 10

[ns]

Mask ROM, Flash memory 5V version

100

= 3V

Table 1.23.25. Memory expansion and microprocessor modes

Timing requirements (referenced to V

= 3V, V

= 0V at Topr = 20

C to 85

C / 40

C to 85

C (*)

unless otherwise specified)

* : Specify a product of -40

C to 85

C to use it.

Table 1.23.24. External clock input

Mitsubishi microcomputers

M16C / 62A Group

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

Timing (Vcc = 3V)

190

= 3V

Timing requirements (referenced to V

= 3V, V

= 0V at Topr = 20

C to 85

C / 40

C to 85

C (*)

unless otherwise specified)

* : Specify a product of -40

C to 85

C to use it.

Standard

Max.

Min.

Unit

Parameter

Symbol

w(TAL)

TAi

input LOW pulse width

c(TA)

TAi

input cycle time

150

w(TAH)

TAi

input HIGH pulse width

Standard

Max.

Min.

Unit

Parameter

Symbol

c(TA)

TAi

input cycle time

600

w(TAH)

TAi

input HIGH pulse width

300

w(TAL)

TAi

input LOW pulse width

300

Standard

Max.

Min.

Unit

Parameter

Symbol

c(TA)

TAi

input cycle time

300

w(TAH)

TAi

input HIGH pulse width

150

w(TAL)

TAi

input LOW pulse width

150

Standard

Max.

Min.

Unit

Parameter

Symbol

w(TAH)

TAi

input HIGH pulse width

150

w(TAL)

TAi

input LOW pulse width

150

Standard

Max.

Min.

Unit

Parameter

Symbol

c(UP)

TAi

OUT

input cycle time

3000

w(UPH)

TAi

OUT

input HIGH pulse width

1500

w(UPL)

TAi

OUT

input LOW pulse width

1500

su(UP-T

)

TAi

OUT

input setup time

600

h(T

IN-

UP)

TAi

OUT

input hold time

600

Table 1.23.27. Timer A input (gating input in timer mode)

Table 1.23.28. Timer A input (external trigger input in one-shot timer mode)

Table 1.23.29. Timer A input (external trigger input in pulse width modulation mode)

Table 1.23.30. Timer A input (up/down input in event counter mode)

Table 1.23.26. Timer A input (counter input in event counter mode)

Mitsubishi microcomputers

M16C / 62A Group

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

Timing (Vcc = 3V)

191

Timing requirements (referenced to V

= 3V, V

= 0V at Topr = 20

C to 85

C / 40

C to 85

C (*)

unless otherwise specified)

* : Specify a product of -40

C to 85

C to use it.

= 3V

Standard

Max.

Min.

Parameter

Symbol

Unit

c(TB)

TBi

input cycle time (counted on one edge)

150

w(TBH)

TBi

input HIGH pulse width (counted on one edge)

w(TBL)

TBi

input LOW pulse width (counted on one edge)

w(TBH)

TBi

input HIGH pulse width (counted on both edges)

160

w(TBL)

TBi

input LOW pulse width (counted on both edges)

160

c(TB)

TBi

input cycle time (counted on both edges)

300

Standard

Max.

Min.

Parameter

Symbol

Unit

c(TB)

TBi

input cycle time

600

w(TBH)

TBi

input HIGH pulse width

300

w(TBL)

TBi

input LOW pulse width

300

Standard

Max.

Min.

Parameter

Symbol

Unit

c(TB)

TBi

input cycle time

600

w(TBH)

TBi

input HIGH pulse width

300

w(TBL)

TBi

input LOW pulse width

300

Standard

Max.

Min.

Parameter

Symbol

Unit

c(AD)

TRG

input cycle time (trigger able minimum)

1500

w(ADL)

TRG

input LOW pulse width

200

Standard

Max.

Min.

Parameter

Symbol

Unit

w(INH)

INTi input HIGH pulse width

380

w(INL)

INTi input LOW pulse width

380

Standard

Max.

Min.

Parameter

Symbol

Unit

c(CK)

CLKi input cycle time

300

w(CKH)

CLKi input HIGH pulse width

150

w(CKL)

CLKi input LOW pulse width

150

h(C-Q)

TxDi hold time

su(D-C)

RxDi input setup time

h(C-D)

RxDi input hold time

d(C-Q)

TxDi output delay time

160

Table 1.23.31. Timer B input (counter input in event counter mode)

Table 1.23.32. Timer B input (pulse period measurement mode)

Table 1.23.33. Timer B input (pulse width measurement mode)

Table 1.23.34. A-D trigger input

Table 1.23.35. Serial I/O

_______

Table 1.23.36. External interrupt INTi inputs

Mitsubishi microcomputers

M16C / 62A Group

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

Timing (Vcc = 3V)

192

d(BCLK-AD)

Address output delay time

d(BCLK-CS)

Chip select output delay time

h(BCLK-AD)

Address output hold time (BCLK standard)

h(BCLK-CS)

Chip select output hold time (BCLK standard)

d(BCLK-ALE)

ALE signal output delay time

h(BCLK-ALE)

ALE signal output hold time

d(BCLK-RD)

RD signal output delay time

h(BCLK-RD)

RD signal output hold time

h(RD-AD)

Address output hold time (RD standard)

d(BCLK-WR)

WR signal output delay time

h(BCLK-WR)

WR signal output hold time

h(WR-AD)

Address output hold time (WR standard)

d(BCLK-DB)

Data output delay time (BCLK standard)

h(BCLK-DB)

Data output hold time (BCLK standard)

d(DB-WR)

Data output delay time (WR standard)

(Note1)

h(WR-DB)

Data output hold time (WR standard)(Note2)

Note 1: Calculated according to the BCLK frequency as follows:

td(DB WR) =

f(BCLK) X 2

[ns]

Symbol

Standard

Measuring condition

Max.

Min.

Parameter

Unit

Note 2: This is standard value shows the timing when the output is off,

and doesn't show hold time of data bus.
Hold time of data bus is different by capacitor volume and pull-up
(pull-down) resistance value.
Hold time of data bus is expressed in

t = CR X ln (1 V

/ V

)

by a circuit of the right figure.

For example, when V

= 0.2V

, C = 30pF, R = 1k

, hold time

of output "L" level is

t = 30pF X 1k

X ln (1 0.2V

/ V

)

= 6.7ns.

DBi

Note 3: Specify a product of -40°C to 85°C to use it.

Switching characteristics (referenced to V

= 3V, V

= 0V at Topr = 20

C to 85

C / 40

C to

C (Note 3), CM15="1" unless otherwise specified)

= 3V

Figure 1.23.7

Table 1.23.37. Memory expansion and microprocessor modes (with no wait)

Figure 1.23.7. Port P0 to P10 measurement circuit

P10

30pF

Mitsubishi microcomputers

M16C / 62A Group

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

Timing (Vcc = 3V)

193

Switching characteristics (referenced to V

= 3V, V

= 0V at Topr = 20

C to 85

C / 40

C to

C (Note 3), CM15="1" unless otherwise specified)

= 3V

Figure 1.23.7

Table 1.23.38. Memory expansion and microprocessor modes

(when accessing external memory area with wait)

d(BCLK-AD)

Address output delay time

d(BCLK-CS)

Chip select output delay time

h(BCLK-AD)

Address output hold time (BCLK standard)

h(BCLK-CS)

Chip select output hold time (BCLK standard)

d(BCLK-ALE)

ALE signal output delay time

h(BCLK-ALE)

ALE signal output hold time

d(BCLK-RD)

RD signal output delay time

h(BCLK-RD)

RD signal output hold time

h(RD-AD)

Address output hold time (RD standard)

d(BCLK-WR)

WR signal output delay time

h(BCLK-WR)

WR signal output hold time

h(WR-AD)

Address output hold time (WR standard)

d(BCLK-DB)

Data output delay time (BCLK standard)

h(BCLK-DB)

Data output hold time (BCLK standard)

d(DB-WR)

Data output delay time (WR standard)

(Note1)

h(WR-DB)

Data output hold time (WR standard)(Note2)

Note 1: Calculated according to the BCLK frequency as follows:

td(DB WR) =

f(BCLK)

[ns]

Symbol

Standard

Measuring condition

Max.

Min.

Parameter

Unit

Note 2: This is standard value shows the timing when the output is off,

and doesn't show hold time of data bus.
Hold time of data bus is different by capacitor volume and pull-up
(pull-down) resistance value.
Hold time of data bus is expressed in

t = CR X ln (1 V

/ V

)

by a circuit of the right figure.

For example, when V

= 0.2V

, C = 30pF, R = 1k

, hold time

of output "L" level is

t = 30pF X 1k

X ln (1 0.2V

/ V

)

= 6.7ns.

DBi

Note 3: Specify a product of -40°C to 85°C to use it.

Mitsubishi microcomputers

M16C / 62A Group

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

Timing (Vcc = 3V)

194

= 3V

Switching characteristics (referenced to V

= 3V, V

= 0V at Topr = 20

C to 85

C / 40

C to

C (Note 2), CM15="1" unless otherwise specified)

Table 1.23.39. Memory expansion and microprocessor modes

(when accessing external memory area with wait, and select multiplexed bus)

Symbol

Standard

Measuring condition

Max.

Min.

Parameter

Unit

d(BCLK-AD)

Address output delay time

h(BCLK-AD)

Address output hold time (BCLK standard)

d(BCLK-CS)

Chip select output delay time

h(BCLK-CS)

Chip select output hold time (BCLK standard)

h(RD-AD)

Address output hold time (RD standard)

(Note1)

d(BCLK-RD)

RD signal output delay time

h(BCLK-RD)

RD signal output hold time

h(WR-AD)

Address output hold time (WR standard)

(Note1)

d(BCLK-WR)

WR signal output delay time

d(BCLK-DB)

Data output delay time (BCLK standard)

h(BCLK-DB)

Data output hold time (BCLK standard)

d(DB-WR)

Data output delay time (WR standard)

(Note1)

h(BCLK-ALE)

ALE signal output hold time (BCLK standard)

d(AD-ALE)

ALE signal output delay time (Address standard)

(Note1)

h(ALE-AD)

ALE signal output hold time(Address standard)

h(BCLK-WR)

WR signal output hold time

h(RD-CS)

Chip select output hold time (RD standard)

(Note1)

h(WR-CS)

Chip select output hold time (WR standard)

(Note1)

d(AD-RD)

Post-address RD signal output delay time

d(AD-WR)

Post-address WR signal output delay time

dZ(RD-AD)

Address output floating start time

d(BCLK-ALE)

ALE signal output delay time (BCLK standard)

Note: Calculated according to the BCLK frequency as follows:

th(RD AD) =

f(BCLK) X 2

[ns]

th(WR AD) =

f(BCLK) X 2

[ns]

th(RD CS) =

f(BCLK) X 2

[ns]

th(WR CS) =

f(BCLK) X 2

[ns]

td(DB WR) =

f(BCLK) X 2

[ns]

X 3

td(AD ALE) =

f(BCLK) X 2

[ns]

th(WR DB) =

f(BCLK) X 2

[ns]

h(WR-DB)

Data output hold time (WR standard)

(Note1)

Note 2: Specify a product of -40°C to 85°C to use it.

Figure 1.23.7

Mitsubishi microcomputers

M16C / 62A Group

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

Timing (Vcc = 3V)

198

Read timing

Write timing

BCLK

CSi

ALE

4ns.min

HiZ

80ns.min

0ns.min

ADi

BHE

d(BCLKWR)

60ns.max

h(BCLKWR)

0ns.min

BCLK

CSi

d(BCLKCS)

60ns.max

d(BCLKAD)

ALE

h(BCLKALE)

h(BCLKCS)

4ns.min

tcyc

0ns.min

h(WRCS)

0ns.min

h(WRAD)

ADi
BHE

d(BCLKDB)

4ns.min

h(BCLKDB)

d(DBWR)

(tcyc80)ns.min

0ns.min

h(WRDB)

DBi

h(RDAD)

0ns.min

d(BCLKALE)

60ns.max

SU(DBRD)

Memory Expansion Mode and Microprocessor Mode

(When accessing external memory area with wait)

Measuring conditions :
· V

=3V

· Input timing voltage : Determined with V

=0.48V, V

=1.5V

· Output timing voltage : Determined with V

=1.5V, V

=1.5V

WR,WRL,

WRH

d(BCLKCS)

60ns.max

h(RDCS)

tcyc

d(BCLKAD)

60ns.max

h(BCLKAD)

4ns.min

h(BCLKALE)

60ns.max

d(BCLKRD)

h(BCLKRD) 0ns.min

ac2(RDDB)

h(RDDB) 0ns.min

h(BCLKAD)

60ns.max

d(BCLKALE) 60ns.max

4ns.min

80ns.max

h(BCLKCS)

4ns.min

= 3V

Figure 1.23.11. V

= 3V timing diagram (4)

Mitsubishi microcomputers

M16C / 62A Group

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

Timing (Vcc = 3V)

199

Memory Expansion Mode and Microprocessor Mode

(When accessing external memory area with wait, and select multiplexed bus)

Measuring conditions :
· V

=3V

· Input timing voltage : Determined with V

=0.48V,V

=1.5V

· Output timing voltage : Determined with V

=1.5V,V

=1.5V

Read timing

Write timing

0ns.min

BCLK

CSi

ALE

60ns.max

4ns.min

h(BCLKCS)
4ns.min

tcyc

ADi

BHE

80ns.max

h(BCLKDB)

4ns.min

d(DBWR)

(tcyc*3/280)ns.min

ADi
/DBi

Address

Data output

(tcyc/2)ns.min

Address

(tcyc/260)ns.min

d(BCLKALE)

d(BCLKWR)

4ns.min

BCLK

CSi

d(BCLKCS)

60ns.max

ALE

4ns.min

h(BCLKCS)

4ns.min

tcyc

ADi

BHE

ADi
/DBi

h(RDDB)

0ns.min

Address

(tcyc/2)ns.min

Data input

Address

tac3(RDDB)

dz(RDAD)

8ns.max

d(ADRD)

0ns.min

d(ADWR)

WR,WRL,

WRH

h(RDCS)

d(ADALE) (tcyc/245)ns.min

SU(DBRD)

80ns.min

h(ALEAD)

50ns.min

d(BCLKAD)

60ns.max

d(BCLKALE)

h(BCLKALE)

4ns.min

(tcyc/2)ns.min

h(RDAD)

h(BCLKAD)

h(BCLKRD)

0ns.min

d(BCLKRD)

60ns.max

d(BCLKCS)

60ns.max

h(WRCS)

(tcyc/2)ns.min

d(BCLKDB)

d(ADALE)

d(BCLKAD)
60ns.max

h(WRDB)

(tcyc/2)ns.min

h(BCLKAD)

h(WRAD)

h(BCLKWR)

h(BCLKALE)

0ns.min

60ns.max

= 3V

Figure 1.23.12. V

= 3V timing diagram (5)

Mitsubishi microcomputers

M16C / 62A Group

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

GZZ-SH13-36B<96A0>

MITSUBISHI ELECTRIC-CHIP 16-BIT

MICROCOMPUTER M30620M8A-XXXFP/GP

MASK ROM CONFIRMATION FORM

Mask ROM number

200

Date :

TEL
( )

Receipt

Section head
signature

Supervisor
signature

Customer

Company

name

Date

issued

Date :

Note : Please complete all items marked

Issuance

signature

Submitted by

Supervisor

1. Check sheet

Mitsubishi processes the mask files generated by the mask file generation utilities out of those held on

the floppy disks you give in to us, and forms them into masks. Hence, we assume liability provided that

there is any discrepancy between the contents of these mask files and the ROM data to be burned into

products we produce. Check thoroughly the contents of the mask files you give in.

Prepare 3.5 inches 2HD (IBM format) floppy disks. And store only one mask file in a floppy disk.

2. Mark specification

The mark specification differs according to the type of package. After entering the mark specification on

the separate mark specification sheet (for each package), attach that sheet to this masking check sheet

for submission to Mitsubishi.

For the M30620M8A-XXXFP, submit the 100P6S mark specification sheet. For the M30620M8A-XXXGP,

submit the 100P6Q mark specification sheet.

3. Usage Conditions

For our reference when of testing our products, please reply to the following questions about the usage

of the products you ordered.

(1) Which kind of X

-X

OUT

oscillation circuit is used?

Ceramic resonator

Quartz-crystal oscillator

External clock input

Other ( )

What frequency do not use?

f(X

) =

Microcomputer type No. :

M30620M8A-XXXFP

M30620M8A-XXXGP

File code :

(hex)

Mask file name :

.MSK (alpha-numeric 8-digit)

Mitsubishi microcomputers

M16C / 62A Group

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

GZZ-SH13-37B<96A0>

MITSUBISHI ELECTRIC-CHIP 16-BIT

MICROCOMPUTER M30620MAA-XXXFP/GP

MASK ROM CONFIRMATION FORM

Mask ROM number

202

Date :

TEL
( )

Receipt

Section head
signature

Supervisor
signature

Customer

Company

name

Date

issued

Date :

Note : Please complete all items marked

Issuance

signature

Submitted by

Supervisor

1. Check sheet

Mitsubishi processes the mask files generated by the mask file generation utilities out of those held on

the floppy disks you give in to us, and forms them into masks. Hence, we assume liability provided that

there is any discrepancy between the contents of these mask files and the ROM data to be burned into

products we produce. Check thoroughly the contents of the mask files you give in.

Prepare 3.5 inches 2HD (IBM format) floppy disks. And store only one mask file in a floppy disk.

2. Mark specification

The mark specification differs according to the type of package. After entering the mark specification on

the separate mark specification sheet (for each package), attach that sheet to this masking check sheet

for submission to Mitsubishi.

For the M30620MAA-XXXFP, submit the 100P6S mark specification sheet. For the M30620MAA-XXXGP,

submit the 100P6Q mark specification sheet.

3. Usage Conditions

For our reference when of testing our products, please reply to the following questions about the usage

of the products you ordered.

(1) Which kind of X

-X

OUT

oscillation circuit is used?

Ceramic resonator

Quartz-crystal oscillator

External clock input

Other ( )

What frequency do not use?

f(X

) =

Microcomputer type No. :

M30620MAA-XXXFP

M30620MAA-XXXGP

File code :

(hex)

Mask file name :

.MSK (alpha-numeric 8-digit)

Mitsubishi microcomputers

M16C / 62A Group

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

GZZ-SH13-28B<95A0>

MITSUBISHI ELECTRIC-CHIP 16-BIT

MICROCOMPUTER M30620MCA-XXXFP/GP

MASK ROM CONFIRMATION FORM

Mask ROM number

204

Date :

TEL
( )

Receipt

Section head
signature

Supervisor
signature

Customer

Company

name

Date

issued

Date :

Note : Please complete all items marked

Issuance

signature

Submitted by

Supervisor

1. Check sheet

Mitsubishi processes the mask files generated by the mask file generation utilities out of those held on

the floppy disks you give in to us, and forms them into masks. Hence, we assume liability provided that

there is any discrepancy between the contents of these mask files and the ROM data to be burned into

products we produce. Check thoroughly the contents of the mask files you give in.

Prepare 3.5 inches 2HD (IBM format) floppy disks. And store only one mask file in a floppy disk.

2. Mark specification

The mark specification differs according to the type of package. After entering the mark specification on

the separate mark specification sheet (for each package), attach that sheet to this masking check sheet

for submission to Mitsubishi.

For the M30620MCA-XXXFP, submit the 100P6S mark specification sheet. For the M30620MCA-XXXGP,

submit the 100P6Q mark specification sheet.

3. Usage Conditions

For our reference when of testing our products, please reply to the following questions about the usage

of the products you ordered.

(1) Which kind of X

-X

OUT

oscillation circuit is used?

Ceramic resonator

Quartz-crystal oscillator

External clock input

Other ( )

What frequency do not use?

f(X

) =

Microcomputer type No. :

M30620MCA-XXXFP

M30620MCA-XXXGP

File code :

(hex)

Mask file name :

.MSK (alpha-numeric 8-digit)

Mitsubishi microcomputers

M16C / 62A Group

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

GZZ-SH13-40B<96A0>

MITSUBISHI ELECTRIC-CHIP 16-BIT

MICROCOMPUTER M30622M4A-XXXFP/GP

MASK ROM CONFIRMATION FORM

Mask ROM number

206

Date :

TEL
( )

Receipt

Section head
signature

Supervisor
signature

Customer

Company

name

Date

issued

Date :

Note : Please complete all items marked

Issuance

signature

Submitted by

Supervisor

1. Check sheet

Mitsubishi processes the mask files generated by the mask file generation utilities out of those held on

the floppy disks you give in to us, and forms them into masks. Hence, we assume liability provided that

there is any discrepancy between the contents of these mask files and the ROM data to be burned into

products we produce. Check thoroughly the contents of the mask files you give in.

Prepare 3.5 inches 2HD (IBM format) floppy disks. And store only one mask file in a floppy disk.

2. Mark specification

The mark specification differs according to the type of package. After entering the mark specification on

the separate mark specification sheet (for each package), attach that sheet to this masking check sheet

for submission to Mitsubishi.

For the M30622M4A-XXXFP, submit the 100P6S mark specification sheet. For the M30622M4A-XXXGP,

submit the 100P6Q mark specification sheet.

3. Usage Conditions

For our reference when of testing our products, please reply to the following questions about the usage

of the products you ordered.

(1) Which kind of X

-X

OUT

oscillation circuit is used?

Ceramic resonator

Quartz-crystal oscillator

External clock input

Other ( )

What frequency do not use?

f(X

) =

Microcomputer type No. :

M30622M4A-XXXFP

M30622M4A-XXXGP

File code :

(hex)

Mask file name :

.MSK (alpha-numeric 8-digit)

Mitsubishi microcomputers

M16C / 62A Group

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

GZZ-SH13-38B<96A0>

MITSUBISHI ELECTRIC-CHIP 16-BIT

MICROCOMPUTER M30622M8A-XXXFP/GP

MASK ROM CONFIRMATION FORM

Mask ROM number

208

Date :

TEL
( )

Receipt

Section head
signature

Supervisor
signature

Customer

Company

name

Date

issued

Date :

Note : Please complete all items marked

Issuance

signature

Submitted by

Supervisor

1. Check sheet

Mitsubishi processes the mask files generated by the mask file generation utilities out of those held on

the floppy disks you give in to us, and forms them into masks. Hence, we assume liability provided that

there is any discrepancy between the contents of these mask files and the ROM data to be burned into

products we produce. Check thoroughly the contents of the mask files you give in.

Prepare 3.5 inches 2HD (IBM format) floppy disks. And store only one mask file in a floppy disk.

2. Mark specification

The mark specification differs according to the type of package. After entering the mark specification on

the separate mark specification sheet (for each package), attach that sheet to this masking check sheet

for submission to Mitsubishi.

For the M30622M8A-XXXFP, submit the 100P6S mark specification sheet. For the M30622M8A-XXXGP,

submit the 100P6Q mark specification sheet.

3. Usage Conditions

For our reference when of testing our products, please reply to the following questions about the usage

of the products you ordered.

(1) Which kind of X

-X

OUT

oscillation circuit is used?

Ceramic resonator

Quartz-crystal oscillator

External clock input

Other ( )

What frequency do not use?

f(X

) =

Microcomputer type No. :

M30622M8A-XXXFP

M30622M8A-XXXGP

File code :

(hex)

Mask file name :

.MSK (alpha-numeric 8-digit)

Mitsubishi microcomputers

M16C / 62A Group

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

GZZ-SH13-34B<96A0>

MITSUBISHI ELECTRIC-CHIP 16-BIT

MICROCOMPUTER M30622MAA-XXXFP/GP

MASK ROM CONFIRMATION FORM

Mask ROM number

210

Date :

TEL
( )

Receipt

Section head
signature

Supervisor
signature

Customer

Company

name

Date

issued

Date :

Note : Please complete all items marked

Issuance

signature

Submitted by

Supervisor

1. Check sheet

Mitsubishi processes the mask files generated by the mask file generation utilities out of those held on

the floppy disks you give in to us, and forms them into masks. Hence, we assume liability provided that

there is any discrepancy between the contents of these mask files and the ROM data to be burned into

products we produce. Check thoroughly the contents of the mask files you give in.

Prepare 3.5 inches 2HD (IBM format) floppy disks. And store only one mask file in a floppy disk.

2. Mark specification

The mark specification differs according to the type of package. After entering the mark specification on

the separate mark specification sheet (for each package), attach that sheet to this masking check sheet

for submission to Mitsubishi.

For the M30622MAA-XXXFP, submit the 100P6S mark specification sheet. For the M30622MAA-XXXGP,

submit the 100P6Q mark specification sheet.

3. Usage Conditions

For our reference when of testing our products, please reply to the following questions about the usage

of the products you ordered.

(1) Which kind of X

-X

OUT

oscillation circuit is used?

Ceramic resonator

Quartz-crystal oscillator

External clock input

Other ( )

What frequency do not use?

f(X

) =

Microcomputer type No. :

M30622MAA-XXXFP

M30622MAA-XXXGP

File code :

(hex)

Mask file name :

.MSK (alpha-numeric 8-digit)

Mitsubishi microcomputers

M16C / 62A Group

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

GZZ-SH13-39B<96A0>

MITSUBISHI ELECTRIC-CHIP 16-BIT

MICROCOMPUTER M30622MCA-XXXFP/GP

MASK ROM CONFIRMATION FORM

Mask ROM number

212

Date :

TEL
( )

Receipt

Section head
signature

Supervisor
signature

Customer

Company

name

Date

issued

Date :

Note : Please complete all items marked

Issuance

signature

Submitted by

Supervisor

1. Check sheet

Mitsubishi processes the mask files generated by the mask file generation utilities out of those held on

the floppy disks you give in to us, and forms them into masks. Hence, we assume liability provided that

there is any discrepancy between the contents of these mask files and the ROM data to be burned into

products we produce. Check thoroughly the contents of the mask files you give in.

Prepare 3.5 inches 2HD (IBM format) floppy disks. And store only one mask file in a floppy disk.

2. Mark specification

The mark specification differs according to the type of package. After entering the mark specification on

the separate mark specification sheet (for each package), attach that sheet to this masking check sheet

for submission to Mitsubishi.

For the M30622MCA-XXXFP, submit the 100P6S mark specification sheet. For the M30622MCA-XXXGP,

submit the 100P6Q mark specification sheet.

3. Usage Conditions

For our reference when of testing our products, please reply to the following questions about the usage

of the products you ordered.

(1) Which kind of X

-X

OUT

oscillation circuit is used?

Ceramic resonator

Quartz-crystal oscillator

External clock input

Other ( )

What frequency do not use?

f(X

) =

Microcomputer type No. :

M30622MCA-XXXFP

M30622MCA-XXXGP

File code :

(hex)

Mask file name :

.MSK (alpha-numeric 8-digit)

Mitsubishi microcomputers

M16C / 62A Group

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

GZZ-SH13-30B<95A0>

MITSUBISHI ELECTRIC-CHIP 16-BIT

MICROCOMPUTER M30624MGA-XXXFP/GP

MASK ROM CONFIRMATION FORM

Mask ROM number

214

Date :

TEL
( )

Receipt

Section head
signature

Supervisor
signature

Customer

Company

name

Date

issued

Date :

Note : Please complete all items marked

Issuance

signature

Submitted by

Supervisor

1. Check sheet

Mitsubishi processes the mask files generated by the mask file generation utilities out of those held on

the floppy disks you give in to us, and forms them into masks. Hence, we assume liability provided that

there is any discrepancy between the contents of these mask files and the ROM data to be burned into

products we produce. Check thoroughly the contents of the mask files you give in.

Prepare 3.5 inches 2HD (IBM format) floppy disks. And store only one mask file in a floppy disk.

2. Mark specification

The mark specification differs according to the type of package. After entering the mark specification on

the separate mark specification sheet (for each package), attach that sheet to this masking check sheet

for submission to Mitsubishi.

For the M30624MGA-XXXFP, submit the 100P6S mark specification sheet. For the M30624MGA-XXXGP,

submit the 100P6Q mark specification sheet.

3. Usage Conditions

For our reference when of testing our products, please reply to the following questions about the usage

of the products you ordered.

(1) Which kind of X

-X

OUT

oscillation circuit is used?

Ceramic resonator

Quartz-crystal oscillator

External clock input

Other ( )

What frequency do not use?

f(X

) =

Microcomputer type No. :

M30624MGA-XXXFP

M30624MGA-XXXGP

File code :

(hex)

Mask file name :

.MSK (alpha-numeric 8-digit)

Description (Flash Memory Version)

Mitsubishi microcomputers

M16C / 62A Group

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

217

Flash Memory

The M16C/62A (flash memory version) contains the flash memory that can be rewritten with a single volt-

age. For this flash memory, three flash memory modes are available in which to read, program, and erase:

parallel I/O and standard serial I/O modes in which the flash memory can be manipulated using a program-

mer and a CPU rewrite mode in which the flash memory can be manipulated by the Central Processing Unit

(CPU). Each mode is detailed in the pages to follow.

The flash memory is divided into several blocks as shown in Figure 1.25.1, so that memory can be erased

one block at a time. Each block has a lock bit to enable or disable execution of an erase or program

operation, allowing for data in each block to be protected.

In addition to the ordinary user ROM area to store a microcomputer operation control program, the flash

memory has a boot ROM area that is used to store a program to control rewriting in CPU rewrite and

standard serial I/O modes. This boot ROM area has had a standard serial I/O mode control program stored

in it when shipped from the factory. However, the user can write a rewrite control program in this area that

suits the user's application system. This boot ROM area can be rewritten in only parallel I/O mode.

Figure 1.25.1. Block diagram of flash memory version

0C0000

0D0000

Block 6 : 64K byte

Block 5 : 64K byte

0E0000

Block 4 : 64K byte

0F0000

Block 3 : 32K byte

0F8000

Block 2 : 8K byte

0FA000

Block 1 : 8K byte

Block 0 : 16K byte

0FC000

User ROM area

8K byte

0FE000

0FFFFF

Boot ROM area

Flash memory

size

Flash memory

start address

256Kbytes

0C0000

128Kbytes

0E0000

Note 1: The boot ROM area can be rewritten in

only parallel input/output mode. (Access
to any other areas is inhibited.)

Note 2: To specify a block, use the maximum

address in the block that is an even
address.

CPU Rewrite Mode (Flash Memory Version)

Mitsubishi microcomputers

M16C / 62A Group

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

218

CPU Rewrite Mode

In CPU rewrite mode, the on-chip flash memory can be operated on (read, program, or erase) under control

of the Central Processing Unit (CPU).

In CPU rewrite mode, only the user ROM area shown in Figure 1.25.1 can be rewritten; the boot ROM area

cannot be rewritten. Make sure the program and block erase commands are issued for only the user ROM

area and each block area.

The control program for CPU rewrite mode can be stored in either user ROM or boot ROM area. In the CPU

rewrite mode, because the flash memory cannot be read from the CPU, the rewrite control program must

be transferred to any area other than the internal flash memory before it can be executed.

Microcomputer Mode and Boot Mode

The control program for CPU rewrite mode must be written into the user ROM or boot ROM area in

parallel I/O mode beforehand. (If the control program is written into the boot ROM area, the standard

serial I/O mode becomes unusable.)

See Figure 1.25.1 for details about the boot ROM area.

Normal microcomputer mode is entered when the microcomputer is reset with pulling CNV

pin low. In

this case, the CPU starts operating using the control program in the user ROM area.

When the microcomputer is reset by pulling the P5

pin low, the CNV

pin high, and the P5

pin high, the

CPU starts operating using the control program in the boot ROM area. This mode is called the "boot"

mode. The control program in the boot ROM area can also be used to rewrite the user ROM area.

Block Address

Block addresses refer to the maximum even address of each block. These addresses are used in the

block erase command, lock bit program command, and read lock status command.

CPU Rewrite Mode (Flash Memory Version)

Mitsubishi microcomputers

M16C / 62A Group

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

219

Outline Performance (CPU Rewrite Mode)

In the CPU rewrite mode, the CPU erases, programs and reads the internal flash memory as instructed by

software commands. Operations must be executed from a memory other than the internal flash memory,

such as the internal RAM.

When the CPU rewrite mode select bit (bit 1 at address 03B7

) is set to "1", transition to CPU rewrite mode

occurs and software commands can be accepted.

In the CPU rewrite mode, write to and read from software commands and data into even-numbered ad-

dress ("0" for byte address A

) in 16-bit units. Always write 8-bit software commands into even-numbered

address. Commands are ignored with odd-numbered addresses.

Use software commands to control program and erase operations. Whether a program or erase operation

has terminated normally or in error can be verified by reading the status register.

Figure 1.26.1 shows the flash memory control register 0 and the flash memory control register 1.

_____

Bit 0 of the flash memory control register 0 is the RY/BY status flag used exclusively to read the operating

status of the flash memory. During programming and erase operations, it is "0". Otherwise, it is "1".

Bit 1 of the flash memory control register 0 is the CPU rewrite mode select bit. The CPU rewrite mode is

entered by setting this bit to "1", so that software commands become acceptable. In CPU rewrite mode, the

CPU becomes unable to access the internal flash memory directly. Therefore, write bit 1 in an area other

_______

than the internal flash memory. Also only when NMI pin is "H" level. To set this bit to "1", it is necessary to

write "0" and then write "1" in succession. The bit can be set to "0" by only writing a "0" .

Bit 2 of the flash memory control register 0 is a lock bit disable select bit. By setting this bit to "1", it is

possible to disable erase and write protect (block lock) effectuated by the lock bit data. The lock bit disable

select bit only disables the lock bit function; it does not change the lock data bit value. However, if an erase

operation is performed when this bit ="1", the lock bit data that is "0" (locked) is set to "1" (unlocked) after

erasure. To set this bit to "1", it is necessary to write "0" and then write "1" in succession. This bit can be

manipulated only when the CPU rewrite mode select bit = "1".

Bit 3 of the flash memory control register 0 is the flash memory reset bit used to reset the control circuit of

the internal flash memory. This bit is used when exiting CPU rewrite mode and when flash memory access

has failed. When the CPU rewrite mode select bit is "1", writing "1" for this bit resets the control circuit. To

release the reset, it is necessary to set this bit to "0".

Bit 5 of the flash memory control register 0 is a user ROM area select bit which is effective in only boot

mode. If this bit is set to "1" in boot mode, the area to be accessed is switched from the boot ROM area to

the user ROM area. When the CPU rewrite mode needs to be used in boot mode, set this bit to "1". Note

that if the microcomputer is booted from the user ROM area, it is always the user ROM area that can be

accessed and this bit has no effect. When in boot mode, the function of this bit is effective regardless of

whether the CPU rewrite mode is on or off. Write to this bit only when executing out of an area other than

the internal flash memory.

Bit 3 of the flash memory control register 1 turns power supply to the internal flash memory on/off. When

this bit is set to "1", power is not supplied to the internal flash memory, thus power consumption can be

reduced. However, in this state, the internal flash memory cannot be accessed. To set this bit to "1", it is

necessary to write "0" and then write "1" in succession. Use this bit mainly in the low speed mode (when

CIN

is the count source of BCLK).

When the CPU is shifted to the stop or wait modes, power to the internal flash memory is automatically shut

off. It is reconnected automatically when CPU operation is restored. Therefore, it is not particularly neces-

sary to set flash memory control register 1.

CPU Rewrite Mode (Flash Memory Version)

Mitsubishi microcomputers

M16C / 62A Group

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

220

Flash memory control register 0

Symbol

Address

When reset

FMR0

03B7

XX000001

b2 b1

FMR00

Bit symbol

Bit name

Function

R W

0: Busy (being written or erased)
1: Ready

CPU rewrite mode
select bit (Note 1)

0: Normal mode
(Software commands invalid)
1: CPU rewrite mode
(Software commands acceptable)

FMR01

0: Boot ROM area is accessed
1: User ROM area is accessed

Lock bit disable
select bit (Note 2)

0: Block lock by lock bit data is

enabled

1: Block lock by lock bit data is

disabled

Flash memory reset bit
(Note 3)

0: Normal operation
1: Reset

Nothing is assigned.
When write, set "0". When read, values are indeterminate.

User ROM area select bit (
Note 4) (Effective in only
boot mode)

FMR02

FMR03

FMR05

Note 1: For this bit to be set to "1", the user needs to write a "0" and then a "1" to it in

succession. When it is not this procedure, it is not enacted in "1". This is necessary to
ensure that no interrupt or DMA transfer will be executed during the interval. Write to
this bit only when executing out of an area other than the internal flash memory. Also
only when NMI pin is "H" level. Clear this bit to "0" after read array command.

Note 2: For this bit to be set to "1", the user needs to write a "0" and then a "1" to it in succession

when the CPU rewrite mode select bit = "1". When it is not this procedure, it is not
enacted in "1". This is necessary to ensure that no interrupt or DMA transfer will be
executed during the interval.

Note 3: Effective only when the CPU rewrite mode select bit = 1. Set this bit to 0 subsequently

after setting it to 1 (reset).

Note 4: Write to this bit only when executing out of an area other than the internal flash memory.

RY/BY status flag

Flash memory control register 1

Symbol

Address

When reset

FMR1

03B6

XXXX0XXX

b5 b4

Bit symbol

Bit name

Function

R W

Flash memory power
supply-OFF bit (Note)

0: Flash memory power supply is
connected
1: Flash memory power supply-off

FMR13

Note : For this bit to be set to "1", the user needs to write a "0" and then a "1" to it in

succession. When it is not this procedure, it is not enacted in "1". This is necessary to
ensure that no interrupt or DMA transfer will be executed during the interval. During
parallel I/O mode,programming,erase or read of flash memory is not controlled by this
bit,only by external pins. Write to this bit only when executing out of an area other than
the internal flash memory.

Reserved bit

Must always be set to "0"

Reserved bit

Must always be set to "0"

Reserved bit

Must always be set to "0"

Figure 1.26.1. Flash memory control registers

Figure 1.26.2 shows a flowchart for setting/releasing the CPU rewrite mode. Figure 1.26.3 shows a flow-

chart for shifting to the low speed mode. Always perform operation as indicated in these flowcharts.

CPU Rewrite Mode (Flash Memory Version)

Mitsubishi microcomputers

M16C / 62A Group

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

221

End

Start

Execute read array command or reset flash
memory by setting flash memory reset bit (by
writing "1" and then "0" in succession) (Note 3)

Single-chip mode, memory expansion

mode, or boot mode

Set processor mode register (Note 1)

Using software command execute erase,
program, or other operation
(Set lock bit disable bit as required)

Jump to transferred control program in RAM

(Subsequent operations are executed by control

program in this RAM)

Transfer CPU rewrite mode control

program to internal RAM

Note 1: During CPU rewrite mode, set the BCLK as shown below using the main clock divide ratio select bits (bit 6

at address 0006

and bits 6 and 7 at address 0007

6.25 MHz or less when wait bit (bit 7 at address 0005

) = "0" (without internal access wait state)

12.5 MHz or less when wait bit (bit 7 at address 0005

) = "1" (with internal access wait state)

Note 2: For CPU rewrite mode select bit to be set to "1", the user needs to write a "0" and then a "1" to it in

succession. When it is not this procedure, it is not enacted in "1". This is necessary to ensure that no
interrupt or DMA transfer will be executed during the interval. Write to this bit only when executing out of
an area other than the internal flash memory. Also only when NMI pin is "H" level.

Note 3: Before exiting the CPU rewrite mode after completing erase or program operation, always be sure to

execute a read array command or reset the flash memory.

Note 4: "1" can be set. However, when this bit is "1", user ROM area is accessed.

(Boot mode only)
Write "0" to user ROM area select bit (Note 4)

Write "0" to CPU rewrite mode select bit

(Boot mode only)
Set user ROM area select bit to "1"

Set CPU rewrite mode select bit to "1" (by
writing "0" and then "1" in succession)(Note 2)

Program in ROM

Program in RAM

Figure 1.26.2. CPU rewrite mode set/reset flowchart

Figure 1.26.3. Shifting to the low speed mode flowchart

End

Start

oscillating

Transfer the program to be executed in the

low speed mode, to the internal RAM.

Switch the count source of BCLK.
X

stop. (Note 2)

Jump to transferred control program in RAM

(Subsequent operations are executed by control

program in this RAM)

Note 1: For flash memory power supply-OFF bit to be set to "1", the user needs to write a "0" and then a "1" to it in

succession. When it is not this procedure, it is not enacted in "1". This is necessary to ensure that no
interrupt or DMA transfer will be executed during the interval.

Note 2: Before the count source for BCLK can be changed from X

to X

CIN

or vice versa, the clock to which

the count source is going to be switched must be oscillating stably.

Wait time until the internal circuit stabilizes
(Set NOP instruction about twice)

Set flash memory power supply-OFF bit to "0"

Set flash memory power supply-OFF bit to "1"
(by writing "0" and then "1" in succession)(Note 1)

Program in ROM

Program in RAM

Process of low speed mode

Wait until the X

has stabilized

Switch the count source of BCLK (Note 2)

CPU Rewrite Mode (Flash Memory Version)

Mitsubishi microcomputers

M16C / 62A Group

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

222

Precautions on CPU Rewrite Mode

Described below are the precautions to be observed when rewriting the flash memory in CPU rewrite

mode.

(1) Operation speed

During CPU rewrite mode, set the BCLK as shown below using the main clock divide ratio select bit

(bit 6 at address 0006

and bits 6 and 7 at address 0007

6.25 MHz or less when wait bit (bit 7 at address 0005

) = 0 (without internal access wait state)

12.5 MHz or less when wait bit (bit 7 at address 0005

) = 1 (with internal access wait state)

(2) Instructions inhibited against use

The instructions listed below cannot be used during CPU rewrite mode because they refer to the

internal data of the flash memory:

UND instruction, INTO instruction, JMPS instruction, JSRS instruction, and BRK instruction

(3) Interrupts inhibited against use

The address match interrupt cannot be used during CPU rewrite mode because they refer to the

internal data of the flash memory. If interrupts have their vector in the variable vector table, they can be

_______

used by transferring the vector into the RAM area. The NMI and watchdog timer interrupts can be

used because the flash memory conterol register 0 and 1 is forcibly initialized and return to normal

mode when each interrupt occurs. But it is needed that the jump addresses for each interrupt are set

in the fixed vector table and there is an interrupt program. Since the rewrite operation is halted when

_______

the NMI and watchdog timer interrupts occur, it is needed that CPU rewriting mode select bit is set to

"1" and the erase/program operation is performed over again.

(4) Internal reserved area expansion bit (Bit 3 at address 0005

)

The reserved area of the internal memory can be changed by using the internal reserved area expan-

sion bit (bit 3 at address 0005

). However, if the CPU rewrite mode select bit (bit 1 at address 03B7

)

is set to 1, the internal reserved area expansion bit (bit 3 at address 0005

) also is set to 1 automati-

cally. Similarly, if the CPU rewrite mode select bit (bit 1 at address 03B7

) is set to 0, the internal

reserved area expansion bit (bit 3 at address 0005

) also is set to 0 automatically.

The precautions above apply to the products which RAM size is over 15 Kbytes or flash memory size

is over 192 Kbytes.

(5) Reset

Reset input is always accepted. After a reset, the addresses 0C0000

through 0CFFFF

are made

a reserved area and cannot be accessed. Therefore, if your product has this area in the user ROM

area, do not write any address of this area to the reset vector. This area is made accessible by

changing the internal reserved area expansion bit (bit 3 at address 0005

) in a program.

(6) Access disable

Write CPU rewrite mode select bit, flash memory power supply-OFF bit and user ROM area select bit

only when executing out of an area other than the internal flash memory.

(7) How to access

For CPU rewrite mode select bit, lock bit disable select bit, and flash memory power supply-OFF bit to

be set to "1", the user needs to write a "0" and then a "1" to it in succession. When it is not this

procedure, it is not enacted in "1". This is necessary to ensure that no interrupt or DMA transfer will be

executed during the interval.

Write CPU rewrite mode select bit only when executing out of an area other than the internal flash

_______

memory. Also only when NMI pin is "H" level.

CPU Rewrite Mode (Flash Memory Version)

Mitsubishi microcomputers

M16C / 62A Group

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

224

Command

Page program

Clear status register

Read array

Read status register

(Note 3)

First bus cycle

Second bus cycle

Third bus cycle

Write

SRD

Read

Write

Lock bit program

Write

Erase all unlock block

Write

WA1

WD1

Write

(Note 2)

WA0

(Note 3)

WD0

(Note 3)

Block erase

Write

(Note 4)

Read lock bit status

Write

Read

(Note 5)

Mode

Address

Mode

Address

Mode

Address

Data

to D

)

Data

to D

)

Data

to D

)

(Note 6)

Note 1: When a software command is input, the high-order byte of data (D

to D

) is ignored.

Note 2: SRD = Status Register Data
Note 3: WA = Write Address, WD = Write Data

WA and WD must be set sequentially from 00

to FE

(byte address; however, an even address). The page size is

256 bytes.

Note 4: BA = Block Address (Enter the maximum address of each block that is an even address.)
Note 5: D

corresponds to the block lock status. Block not locked when D

= 1, block locked when D

= 0.

Note 6: X denotes a given address in the user ROM area (that is an even address).

Software Commands

Table 1.26.1 lists the software commands available with the M16C/62A (flash memory version).

After setting the CPU rewrite mode select bit to 1, write a software command to specify an erase or

program operation. Note that when entering a software command, the upper byte (D

to D

) is ignored.

The content of each software command is explained below.

Table 1.26.1. List of software commands (CPU rewrite mode)

Read Array Command (FF

)

The read array mode is entered by writing the command code "FF

" in the first bus cycle. When an

even address to be read is input in one of the bus cycles that follow, the content of the specified

address is read out at the data bus (D

), 16 bits at a time.

The read array mode is retained intact until another command is written.

Read Status Register Command (70

)

When the command code "70

" is written in the first bus cycle, the content of the status register is

read out at the data bus (D

) by a read in the second bus cycle.

The status register is explained in the next section.

Clear Status Register Command (50

)

This command is used to clear the bits SR3 to 5 of the status register after they have been set. These

bits indicate that operation has ended in an error. To use this command, write the command code

"50

" in the first bus cycle.

CPU Rewrite Mode (Flash Memory Version)

Mitsubishi microcomputers

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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

225

n = FE

Start

Write 41

n = 0

Write address n and

data n

RY/BY status flag

= 1?

Check full status

Page program

completed

n = n + 2

YES

Figure 1.26.4. Page program flowchart

Page Program Command (41

)

Page program allows for high-speed programming in units of 256 bytes. Page program operation

starts when the command code "41

" is written in the first bus cycle. In the second bus cycle through

the 129th bus cycle, the write data is sequentially written 16 bits at a time. At this time, the addresses

-A

need to be incremented by 2 from "00

" to "FE

." When the system finishes loading the data,

it starts an auto write operation (data program and verify operation).

Whether the auto write operation is completed can be confirmed by reading the status register or the

flash memory control register 0. At the same time the auto write operation starts, the read status

status register bit 7 (SR7) is set to 0 at the same time the auto write operation starts and is returned to

1 upon completion of the auto write operation. In this case, the read status register mode remains

active until the Read Array command (FF

) or Read Lock Bit Status command (71

) is written or the

flash memory is reset using its reset bit.

____

The RY/BY status flag of the flash memory control register 0 is 0 during auto write operation and 1

when the auto write operation is completed as is the status register bit 7.

After the auto write operation is completed, the status register can be read out to know the result of the

auto write operation. For details, refer to the section where the status register is detailed.

Figure 1.26.4 shows an example of a page program flowchart.

Each block of the flash memory can be write protected by using a lock bit. For details, refer to the

section where the data protect function is detailed.

Additional writes to the already programmed pages are prohibited.

CPU Rewrite Mode (Flash Memory Version)

Mitsubishi microcomputers

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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

226

Write 20

Write D0

Block address

Check full status

check(Note)

Block erase

completed

Start

RY/BY status flag

= 1?

YES

Error

Erase error

Note: Refer to Figure 1.26.8.

Figure 1.26.5. Block erase flowchart

Block Erase Command (20

/D0

)

By writing the command code "20

" in the first bus cycle and the confirmation command code "D0

in the second bus cycle that follows to the block address of a flash memory block, the system initiates

an auto erase (erase and erase verify) operation.

Whether the auto erase operation is completed can be confirmed by reading the status register or the

flash memory control register 0. At the same time the auto erase operation starts, the read status

status register bit 7 (SR7) is set to 0 at the same time the auto erase operation starts and is returned

to 1 upon completion of the auto erase operation. In this case, the read status register mode remains

active until the Read Array command (FF

) or Read Lock Bit Status command (71

) is written or the

flash memory is reset using its reset bit.

____

The RY/BY status flag of the flash memory control register 0 is 0 during auto erase operation and 1

when the auto erase operation is completed as is the status register bit 7.

After the auto erase operation is completed, the status register can be read out to know the result of

the auto erase operation. For details, refer to the section where the status register is detailed.

Figure 1.26.5 shows an example of a block erase flowchart.

Each block of the flash memory can be protected against erasure by using a lock bit. For details, refer

to the section where the data protect function is detailed.

CPU Rewrite Mode (Flash Memory Version)

Mitsubishi microcomputers

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SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

227

Write 77

Write D0

block address

SR4 = 0?

Lock bit program

completed

Lock bit program in

error

YES

Start

RY/BY status flag

= 1?

YES

Erase All Unlock Blocks Command (A7

/D0

)

By writing the command code "A7

" in the first bus cycle and the confirmation command code "D0

in the second bus cycle that follows, the system starts erasing blocks successively.

Whether the erase all unlock blocks command is terminated can be confirmed by reading the status

When the lock bit disable select bit of the flash memory control register 0 = 1, all blocks are erased no

matter how the lock bit is set. On the other hand, when the lock bit disable select bit = 0, the function of

the lock bit is effective and only nonlocked blocks (where lock bit data = 1) are erased.

Lock Bit Program Command (77

/D0

)

By writing the command code "77

" in the first bus cycle and the confirmation command code "D0

in the second bus cycle that follows to the block address of a flash memory block, the system sets the

lock bit for the specified block to 0 (locked).

Figure 1.26.6 shows an example of a lock bit program flowchart. The status of the lock bit (lock bit

data) can be read out by a read lock bit status command.

Whether the lock bit program command is terminated can be confirmed by reading the status register

or the flash memory control register 0, in the same way as for page program.

For details about the function of the lock bit and how to reset the lock bit, refer to the section where the

data protect function is detailed.

Figure 1.26.6. Lock bit program flowchart

CPU Rewrite Mode (Flash Memory Version)

Mitsubishi microcomputers

M16C / 62A Group

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

229

Data Protect Function (Block Lock)

Each block in Figure 1.25.1 has a nonvolatile lock bit to specify that the block be protected (locked)

against erase/write. The lock bit program command is used to set the lock bit to 0 (locked). The lock bit of

each block can be read out using the read lock bit status command.

Whether block lock is enabled or disabled is determined by the status of the lock bit and how the flash

memory control register 0's lock bit disable select bit is set.

(1) When the lock bit disable select bit = "0", a specified block can be locked or unlocked by the lock bit

status (lock bit data). Blocks whose lock bit data = "0" are locked, so they are disabled against

erase/write. On the other hand, the blocks whose lock bit data = "1" are not locked, so they are

enabled for erase/write.

(2) When the lock bit disable select bit = "1", all blocks are nonlocked regardless of the lock bit data, so

they are enabled for erase/write. In this case, the lock bit data that is "0" (locked) is set to "1"

(nonlocked) after erasure, so that the lock bit-actuated lock is removed.

Status Register

The status register indicates the operating status of the flash memory and whether an erase or program

operation has terminated normally or in an error. The content of this register can be read out by only

writing the read status register command (70

). Table 1.26.2 details the status register.

The status register is cleared by writing the Clear Status Register command (50

After a reset, the status register is set to "80

Each bit in this register is explained below.

Write state machine (WSM) status (SR7)

After power-on, the write state machine (WSM) status is set to "1".

The write state machine (WSM) status indicates the operating status of the device, as for output on the

____

RY/BY pin. This status bit is set to "0" during auto write or auto erase operation and is set to "1" upon

completion of these operations.

Erase status (SR5)

The erase status informs the operating status of auto erase operation to the CPU. When an erase

error occurs, it is set to "1".

The erase status is reset to "0" when cleared.

CPU Rewrite Mode (Flash Memory Version)

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230

Each bit of

SRD

SR4 (bit4)

SR5 (bit5)

SR7 (bit7)

SR6 (bit6)

Status name

Definition

SR1 (bit1)

SR2 (bit2)

SR3 (bit3)

SR0 (bit0)

"1"

"0"

Program status

Erase status

Write state machine (WSM) status

Reserved

Block status after program

Reserved

Ready

Busy

Terminated in error

Terminated normally

Program status (SR4)

The program status informs the operating status of auto write operation to the CPU. When a write

error occurs, it is set to "1".

The program status is reset to "0" when cleared.

When an erase command is in error (which occurs if the command entered after the block erase

command (20

) is not the confirmation command (D0

), both the program status and erase status

(SR5) are set to "1".

When the program status or erase status = "1", only the following flash commands will be accepted:

Read Array, Read Status Register, and Clear Status Register.

Also, in one of the following cases, both SR4 and SR5 are set to "1" (command sequence error):

(1) When the valid command is not entered correctly

(2) When the data entered in the second bus cycle of lock bit program (77

/D0

), block erase

(20

/D0

), or erase all unlock blocks (A7

/D0

) is not the D0

or FF

. However, if FF

entered, read array is assumed and the command that has been set up in the first bus cycle is

canceled.

Block status after program (SR3)

If excessive data is written (phenomenon whereby the memory cell becomes depressed which results

in data not being read correctly), "1" is set for the program status after-program at the end of the page

write operation. In other words, when writing ends successfully, "80

" is output; when writing fails,

"90

" is output; and when excessive data is written, "88

" is output.

Table 1.26.2. Definition of each bit in status register

CPU Rewrite Mode (Flash Memory Version)

Mitsubishi microcomputers

M16C / 62A Group

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

231

Read status register

SR4=1 and SR5

=1 ?

Command

sequence error

YES

SR5=0?

YES

Block erase error

SR4=0?

YES

Program error (page

or lock bit)

SR3=0?

YES

Program error

(block)

End (block erase, program)

Execute the clear status register command (50

)

to clear the status register. Try performing the
operation one more time after confirming that the
command is entered correctly.

Should a block erase error occur, the block in error
cannot be used.

Execute the read lock bit status command (71

)

to see if the block is locked. After removing lock,
execute write operation in the same way. If the
error still occurs, the page in error cannot be
used.

After erasing the block in error, execute write
operation one more time. If the same error still
occurs, the block in error cannot be used.

Note: When one of SR5 to SR3 is set to 1, none of the page program, block erase,

erase all unlock blocks and lock bit program commands is accepted. Execute the
clear status register command (50

) before executing these commands.

Full Status Check

By performing full status check, it is possible to know the execution results of erase and program

operations. Figure 1.26.8 shows a full status check flowchart and the action to be taken when each

error occurs.

Figure 1.26.8. Full status check flowchart and remedial procedure for errors

Functions To Inhibit Rewriting Flash Memory Version (Flash Memory Version)

Mitsubishi microcomputers

M16C / 62A Group

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

232

Symbol

Address

When reset

ROMCP

0FFFFF

ROM code protect level
2 set bit (Note 1, 2)

00: Protect enabled
01: Protect enabled
10: Protect enabled
11: Protect disabled

ROM code protect control address

Bit name

Function

Bit symbol

00: Protect removed
01: Protect set bit effective
10: Protect set bit effective
11: Protect set bit effective

00: Protect enabled
01: Protect enabled
10: Protect enabled
11: Protect disabled

ROM code protect reset
bit (Note 3)

ROM code protect level
1 set bit (Note 1)

ROMCP2

ROMCR

ROMCP1

b3 b2

b5 b4

b7 b6

Note 1: When ROM code protect is turned on, the on-chip flash memory is protected against

readout or modification in parallel input/output mode.

Note 2: When ROM code protect level 2 is turned on, ROM code readout by a shipment

inspection LSI tester, etc. also is inhibited.

Note 3: The ROM code protect reset bits can be used to turn off ROM code protect level 1 and

ROM code protect level 2. However, since these bits cannot be changed in parallel input/
output mode, they need to be rewritten in serial input/output or some other mode.

Reserved bit

Always set this bit to 1.

1 1

Functions To Inhibit Rewriting Flash Memory Version

To prevent the contents of the flash memory version from being read out or rewritten easily, the device

incorporates a ROM code protect function for use in parallel I/O mode and an ID code check function for

use in standard serial I/O mode.

ROM code protect function

The ROM code protect function is used to prohibit reading out or modifying the contents of the flash

memory during parallel I/O mode and is set by using the ROM code protect control address register

(0FFFFF

). Figure 1.27.1 shows the ROM code protect control address (0FFFFF

). (This address ex-

ists in the user ROM area.)

If one of the pair of ROM code protect bits is set to 0, ROM code protect is turned on, so that the contents

of the flash memory version are protected against readout and modification. ROM code protect is imple-

mented in two levels. If level 2 is selected, the flash memory is protected even against readout by a

shipment inspection LSI tester, etc. When an attempt is made to select both level 1 and level 2, level 2 is

selected by default.

If both of the two ROM code protect reset bits are set to "00," ROM code protect is turned off, so that the

contents of the flash memory version can be read out or modified. Once ROM code protect is turned on,

the contents of the ROM code protect reset bits cannot be modified in parallel I/O mode. Use the serial I/

O or some other mode to rewrite the contents of the ROM code protect reset bits.

Figure 1.27.1. ROM code protect control address

Functions To Inhibit Rewriting Flash Memory Version (Flash Memory Version)

Mitsubishi microcomputers

M16C / 62A Group

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

233

ID Code Check Function

Use this function in standard serial I/O mode. When the contents of the flash memory are not blank, the ID

code sent from the peripheral unit is compared with the ID code written in the flash memory to see if they

match. If the ID codes do not match, the commands sent from the peripheral unit are not accepted. The ID

code consists of 8-bit data, the areas of which, beginning with the first byte, are 0FFFDF

, 0FFFE3

0FFFEB

, 0FFFEF

, 0FFFF3

, 0FFFF7

, and 0FFFFB

. Write a program which has had the ID code

preset at these addresses to the flash memory.

Figure 1.27.2. ID code store addresses

Reset vector

Watchdog timer vector

Single step vector

Address match vector

BRK instruction vector

Overflow vector

Undefined instruction vector

ID7

ID6

ID5

ID4

ID3

ID2

ID1

DBC vector

NMI vector

0FFFFC

to 0FFFFF

0FFFF8

to 0FFFFB

0FFFF4

to 0FFFF7

0FFFF0

to 0FFFF3

0FFFEC

to 0FFFEF

0FFFE8

to 0FFFEB

0FFFE4

to 0FFFE7

0FFFE0

to 0FFFE3

0FFFDC

to 0FFFDF

4 bytes

Address

Appendix Parallel I/O Mode (Flash Memory Version)

Mitsubishi microcomputers

M16C / 62A Group

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

234

Parallel I/O Mode

The parallel I/O mode inputs and outputs the software commands, addresses and data needed to operate

(read, program, erase, etc.) the internal flash memory. This I/O is parallel.

Use an exclusive programer supporting M16C/62A (flash memory version).

Refer to the instruction manual of each programer maker for the details of use.

User ROM and Boot ROM Areas

In parallel I/O mode, the user ROM and boot ROM areas shown in Figure 1.25.1 can be rewritten. Both

areas of flash memory can be operated on in the same way.

Program and block erase operations can be performed in the user ROM area. The user ROM area and its

blocks are shown in Figure 1.25.1.

The boot ROM area is 8 Kbytes in size. In parallel I/O mode, it is located at addresses 0FE000

through

0FFFFF

. Make sure program and block erase operations are always performed within this address

range. (Access to any location outside this address range is prohibited.)

In the boot ROM area, an erase block operation is applied to only one 8 Kbyte block. The boot ROM area

has had a standard serial I/O mode control program stored in it when shipped from the Mitsubishi factory.

Therefore, using the device in standard serial input/output mode, you do not need to write to the boot

ROM area.

Appendix Standard Serial I/O Mode (Flash Memory Version)

Mitsubishi microcomputers

M16C / 62A Group

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

235

Pin Description

Apply program/erase protection voltage to Vcc pin and 0 V to Vss pin.

CNV

Connect to Vcc pin.

RESET

Reset input pin. While reset is "L" level, a 20 cycle or longer clock
must be input to X

pin.

Connect a ceramic resonator or crystal oscillator between X

and

OUT

pins. To input an externally generated clock, input it to X

and open X

OUT

pin.

OUT

BYTE

Connect this pin to V

or V

, AV

REF

Connect AV

to V

and AV

to V

, respectively.

Enter the reference voltage for AD from this pin.

to P0

Input "H" or "L" level signal or open.

to P1

Input "H" or "L" level signal or open.

to P2

Input "H" or "L" level signal or open.

to P3

Input "H" or "L" level signal or open.

to P4

Input "H" or "L" level signal or open.

to P5

Input "H" or "L" level signal or open.

Input "H" level signal.

Input "L" level signal.

to P6

Input "H" or "L" level signal or open.

Standard serial I/O mode 1: BUSY signal output pin
Standard serial I/O mode 2: Monitors the boot program operation
check signal output pin.

Serial data input pin

Serial data output pin

to P7

Input "H" or "L" level signal or open.

to P8

, P8

Input "H" or "L" level signal or open.

to P9

Input "H" or "L" level signal or open.

P10

to P10

Input "H" or "L" level signal or open.

Name

Power input

CNV

Reset input

Clock input

Clock output

BYTE

Analog power supply input

Reference voltage input

Input port P0

Input port P1

Input port P2

Input port P3

Input port P4

Input port P5

CE input

EPM input

Input port P6

BUSY output

SCLK input

RxD input

TxD output

Input port P7

Input port P8

Input port P9

Input port P10

I/O

NMI input

Connect this pin to Vcc.

Standard serial I/O mode 1: Serial clock input pin
Standard serial I/O mode 2: Input "L".

Pin functions (Flash memory standard serial I/O mode)

Appendix Standard Serial I/O Mode (Flash Memory Version)

Mitsubishi microcomputers

M16C / 62A Group

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

236

Figure 1.29.1. Pin connections for serial I/O mode (1)

2 3

4 5

8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30

100

/INT3

REF

/INT4

/INT5

OUT

RESET

CNVss

CIN

COUT

BYTE

(/D

/-)

(/D

)

(/D

)

(/D

)

(/D

)

(/D

)

(/D

)

(/D

)

(/-/D

)

/TA2

OUT

/TA2

/TA3

OUT

/ALE

/TA3

/HOLD

/HLDA

/BCLK

/RD

Vcc

Vss

/RDY/CLK

OUT

/CS1

/CS2

/CS3

AVcc

/CLK

/RxD

/CLK

/RxD

P10

/AN

P10

/AN

P10

/AN

P10

/AN

P10

/AN

P10

/AN

/KI

P10

/AN

/KI

P10

/AN

/KI

/DA

/TB3

/DA

/TB4

/ANEX0/CLK4

/ANEX1/S

OUT

/TB1

/TB2

OUT

/AD

TRG

/INT

/TA4

/INT

/TA4

OUT

/CTS

/RTS

/CTS

/RTS

/CTS

/CLKS

/CTS

/RTS

/TA1

/CLK

/TA1

OUT

/RxD

/SCL/TA0

/TB5

/NMI

/CS0

/WRL/WR

/WRH/BHE

/TB0

/CLK3

/SDA/TA0

OUT

Vcc

Vss

RxD

TxD

SCLK

CNVss

EPM

BUSY

RESET

Connect
oscillator
circuit.

CNVss

Vcc

EPM

Vss

RESET

Vss to Vcc

Vcc

Signal

Value

Mode setup method

Package: 100P6S-A

M16C/62A Group

(Flash memory version)

Appendix Standard Serial I/O Mode (Flash Memory Version)

Mitsubishi microcomputers

M16C / 62A Group

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

237

Figure 1.29.2. Pin connections for serial I/O mode (2)

CNVss

Vcc

EPM

Vss

RESET

Vss to Vcc

Vcc

Signal

Value

Mode setup method

CNV

RESET

1 2

6 7

9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25

100

75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51

/CTS

/RTS

/CTS

/CLKS

/ALE

/HOLD

/HLDA

/BCLK

/RD

/RDY/CLK

OUT

/CS1

/CS2

/CS3

/CLK

/RxD

/CLK

/RxD

/CTS

/RTS

/CS0

/WRL/WR

/WRH/BHE

/CLK

/TA1

OUT

/RxD

/SCL/TA0

/TB5

/SDA/TA0

OUT

REF

AVcc

P10

/AN

P10

/AN

P10

/AN

P10

/AN

/ANEX0/CLK4

/ANEX1/S

OUT

/AD

TRG

P10

/AN

/KI

P10

/AN

/KI

P10

/AN

/KI

P10

/AN

(/D

/-)

(/D

)

(/D

)

(/D

)

(/D

)

(/D

)

(/D

)

(/D

)

(/-/D

)

Vcc

Vss

/INT

/TA2

OUT

RESET

CNVss

CIN

COUT

BYTE

/TA3

OUT

/TA3

/DA

/TB3

/DA

/TB4

/TB1

/TB2

OUT

/TA4

OUT

/INT

/NMI

/TB0

/CLK3

/INT

/TA2

/TA4

/CTS

/RTS

/TA1

BUSY

EPM

SCLK

Connect
oscillator
circuit.

Package: 100P6Q-A

M16C/62A Group

(Flash memory version)

Appendix Standard Serial I/O Mode (Flash Memory Version)

Mitsubishi microcomputers

M16C / 62A Group

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

238

Standard serial I/O mode

The standard serial I/O mode inputs and outputs the software commands, addresses and data needed to

operate (read, program, erase, etc.) the internal flash memory. This I/O is serial. There are actually two

standard serial I/O modes: mode 1, which is clock synchronized, and mode 2, which is asynchronized. Both

modes require a purpose-specific peripheral unit.

The standard serial I/O mode is different from the parallel I/O mode in that the CPU controls flash memory

rewrite (uses the CPU's rewrite mode), rewrite data input and so forth. It is started when the reset is re-

_____

________

leased, which is done when the P5

(CE) pin is "H" level, the P5

(EPM) pin "L" level and the CNVss pin "H"

level. (In the ordinary command mode, set CNVss pin to "L" level.)

This control program is written in the boot ROM area when the product is shipped from Mitsubishi. Accord-

ingly, make note of the fact that the standard serial I/O mode cannot be used if the boot ROM area is

rewritten in the parallel I/O mode. Figures 1.29.1 and 1.29.2 show the pin connections for the standard

serial I/O mode. Serial data I/O uses UART1 and transfers the data serially in 8-bit units. Standard serial I/

O switches between mode 1 (clock synchronized) and mode 2 (clock asynchronized) according to the level

of CLK

pin when the reset is released.

To use standard serial I/O mode 1 (clock synchronized), set the CLK

pin to "H" level and release the reset.

The operation uses the four UART1 pins CLK

, RxD

, TxD

and RTS

(BUSY). The CLK

pin is the transfer

clock input pin through which an external transfer clock is input. The TxD

pin is for CMOS output. The

RTS

(BUSY) pin outputs an "L" level when ready for reception and an "H" level when reception starts.

To use standard serial I/O mode 2 (clock asynchronized), set the CLK

pin to "L" level and release the

reset. The operation uses the two UART1 pins RxD

and TxD

In the standard serial I/O mode, only the user ROM area indicated in Figure 1.29.19 can be rewritten. The

boot ROM cannot.

In the standard serial I/O mode, a 7-byte ID code is used. When there is data in the flash memory, com-

mands sent from the peripheral unit are not accepted unless the ID code matches.

Appendix Standard Serial I/O Mode 1 (Flash Memory Version)

Mitsubishi microcomputers

M16C / 62A Group

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

239

Overview of standard serial I/O mode 1 (clock synchronized)

In standard serial I/O mode 1, software commands, addresses and data are input and output between the

MCU and peripheral units (serial programer, etc.) using 4-wire clock-synchronized serial I/O (UART1).

Standard serial I/O mode 1 is engaged by releasing the reset with the P6

(CLK

) pin "H" level.

In reception, software commands, addresses and program data are synchronized with the rise of the

transfer clock that is input to the CLK

pin, and are then input to the MCU via the RxD

pin. In transmis-

sion, the read data and status are synchronized with the fall of the transfer clock, and output from the

TxD

pin.

The TxD

pin is for CMOS output. Transfer is in 8-bit units with LSB first.

When busy, such as during transmission, reception, erasing or program execution, the RTS

(BUSY) pin

is "H" level. Accordingly, always start the next transfer after the RTS

(BUSY) pin is "L" level.

Also, data and status registers in memory can be read after inputting software commands. Status, such

as the operating state of the flash memory or whether a program or erase operation ended successfully or

not, can be checked by reading the status register. Here following are explained software commands,

status registers, etc.

Appendix Standard Serial I/O Mode 1 (Flash Memory Version)

Mitsubishi microcomputers

M16C / 62A Group

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

240

Software Commands

Table 1.29.1 lists software commands. In the standard serial I/O mode 1, erase operations, programs and

reading are controlled by transferring software commands via the RxD

pin. Software commands are

explained here below.

Table 1.29.1. Software commands (Standard serial I/O mode 1)

Control command

2nd byte 3rd byte 4th byte 5th byte 6th byte

Page read

Page program

Block erase

Erase all unlocked blocks

Read status register

Clear status register

Read lock bit status

Lock bit program

Lock bit enable

Lock bit disable

ID check function

Download function

Version data output function

Boot ROM area output
function

Read check data

Address
(middle)

SRD

output

Address
(middle)

Address

(low)

Size (low)

Version

data

output

Address
(middle)

Check

data (low)

Address

(high)

Address

(high)

Address

(high)

SRD1

output

Address

(high)

Address

(high)

Address
(middle)

Size

(high)

Version

data

output

Address

(high)

Check

data

(high)

Data

output

Data

input

Lock bit

data

output

Address

(high)

Check-

sum

Version

data

output

Data

output

Data

output

Data

input

ID size

Data

input

Version

data

output

Data

output

Data

output

Data

input

ID1

required

number

of times

Version

data

output

Data

output

Data

output to

259th byte

Data input

to 259th

byte

To ID7

Version

data

output to

9th byte

Data

output to

259th

byte

When ID is
not verified

Not

acceptable

Not

acceptable

Not

acceptable

Not

acceptable

Acceptable

Not

acceptable

Not

acceptable

Not

acceptable

Not

acceptable

Not

acceptable

Acceptable

Not

acceptable

Acceptable

Not

acceptable

Not

acceptable

1st byte

transfer

Note 1: Shading indicates transfer from flash memory microcomputer to peripheral unit. All other data is trans-

ferred from the peripheral unit to the flash memory microcomputer.

Note 2: SRD refers to status register data. SRD1 refers to status register 1 data.

Note 3: All commands can be accepted when the flash memory is totally blank.

Appendix Standard Serial I/O Mode 1 (Flash Memory Version)

Mitsubishi microcomputers

M16C / 62A Group

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

241

Page Read Command

This command reads the specified page (256 bytes) in the flash memory sequentially one byte at a

time. Execute the page read command as explained here following.

(1) Transfer the "FF

" command code with the 1st byte.

(2) Transfer addresses A

to A

and A

to A

with the 2nd and 3rd bytes respectively.

(3) From the 4th byte onward, data (D

) for the page (256 bytes) specified with addresses A

will be output sequentially from the smallest address first in sync with the fall of the clock.

Figure 1.29.3. Timing for page read

Read Status Register Command

This command reads status information. When the "70

" command code is sent with the 1st byte, the

contents of the status register (SRD) specified with the 2nd byte and the contents of status register 1

(SRD1) specified with the 3rd byte are read.

Figure 1.29.4. Timing for reading the status register

data0

data255

CLK1

RxD1

TxD1

RTS1(BUSY)

(M16C reception data)

(M16C transmit data)

SRD

output

SRD1

output

CLK1

RxD1

TxD1

RTS1(BUSY)

(M16C reception data)

(M16C transmit data)

Appendix Standard Serial I/O Mode 1 (Flash Memory Version)

Mitsubishi microcomputers

M16C / 62A Group

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

242

Clear Status Register Command

This command clears the bits (SR3SR5) which are set when the status register operation ends in

error. When the "50

" command code is sent with the 1st byte, the aforementioned bits are cleared.

When the clear status register operation ends, the RTS

(BUSY) signal changes from the "H" to the

"L" level.

Figure 1.29.5. Timing for clearing the status register

Page Program Command

This command writes the specified page (256 bytes) in the flash memory sequentially one byte at a

time. Execute the page program command as explained here following.

(1) Transfer the "41

" command code with the 1st byte.

(2) Transfer addresses A

to A

and A

to A

with the 2nd and 3rd bytes respectively.

(3) From the 4th byte onward, as write data (D

) for the page (256 bytes) specified with addresses

to A

is input sequentially from the smallest address first, that page is automatically written.

When reception setup for the next 256 bytes ends, the RTS

(BUSY) signal changes from the "H" to

the "L" level. The result of the page program can be known by reading the status register. For more

information, see the section on the status register.

Each block can be write-protected with the lock bit. For more information, see the section on the data

protection function. Additional writing is not allowed with already programmed pages.

Figure 1.29.6. Timing for the page program

CLK1

RxD1

TxD1

RTS1(BUSY)

(M16C reception data)

(M16C transmit data)

CLK1

RxD1

TxD1

RTS1(BUSY)

data0

data255

(M16C reception data)

(M16C transmit data)

Appendix Standard Serial I/O Mode 1 (Flash Memory Version)

Mitsubishi microcomputers

M16C / 62A Group

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

243

Block Erase Command

This command erases the data in the specified block. Execute the block erase command as explained

here following.

(1) Transfer the "20

" command code with the 1st byte.

(2) Transfer addresses A

to A

and A

to A

with the 2nd and 3rd bytes respectively.

(3) Transfer the verify command code "D0

" with the 4th byte. With the verify command code, the

erase operation will start for the specified block in the flash memory. Write the highest address of

the specified block for addresses A

to A

When block erasing ends, the RTS

(BUSY) signal changes from the "H" to the "L" level. After block

erase ends, the result of the block erase operation can be known by reading the status register. For

more information, see the section on the status register.

Each block can be erase-protected with the lock bit. For more information, see the section on the data

protection function.

Figure 1.29.7. Timing for block erasing

CLK1

RxD1

TxD1

RTS1(BUSY)

(M16C reception data)

(M16C transmit data)

Appendix Standard Serial I/O Mode 1 (Flash Memory Version)

Mitsubishi microcomputers

M16C / 62A Group

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

244

Erase All Unlocked Blocks Command

This command erases the content of all blocks. Execute the erase all unlocked blocks command as

explained here following.

(1) Transfer the "A7

" command code with the 1st byte.

(2) Transfer the verify command code "D0

" with the 2nd byte. With the verify command code, the

erase operation will start and continue for all blocks in the flash memory.

When block erasing ends, the RTS

(BUSY) signal changes from the "H" to the "L" level. The result of the

erase operation can be known by reading the status register. Each block can be erase-protected with the

lock bit. For more information, see the section on the data protection function.

Figure 1.29.8. Timing for erasing all unlocked blocks

Lock Bit Program Command

This command writes "0" (lock) for the lock bit of the specified block. Execute the lock bit program

command as explained here following.

(1) Transfer the "77

" command code with the 1st byte.

(2) Transfer addresses A

to A

and A

to A

with the 2nd and 3rd bytes respectively.

(3) Transfer the verify command code "D0

" with the 4th byte. With the verify command code, "0" is

written for the lock bit of the specified block. Write the highest address of the specified block for

addresses A

to A

When writing ends, the RTS

(BUSY) signal changes from the "H" to the "L" level. Lock bit status can

be read with the read lock bit status command. For information on the lock bit function, reset proce-

dure and so on, see the section on the data protection function.

Figure 1.29.9. Timing for the lock bit program

CLK1

RxD1

TxD1

RTS1(BUSY)

(M16C reception data)

(M16C transmit data)

CLK1

RxD1

TxD1

RTS1(BUSY)

(M16C reception data)

(M16C transmit data)

Appendix Standard Serial I/O Mode 1 (Flash Memory Version)

Mitsubishi microcomputers

M16C / 62A Group

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

245

Lock Bit Enable Command

This command enables the lock bit in blocks whose bit was disabled with the lock bit disable com-

mand. The command code "7A

" is sent with the 1st byte of the serial transmission. This command

only enables the lock bit function; it does not set the lock bit itself.

Read Lock Bit Status Command

This command reads the lock bit status of the specified block. Execute the read lock bit status com-

mand as explained here following.

(1) Transfer the "71

" command code with the 1st byte.

(2) Transfer addresses A

to A

and A

to A

with the 2nd and 3rd bytes respectively.

(3) The lock bit data of the specified block is output with the 4th byte. The lock bit data is the 6th

bit(D

) of the output data. Write the highest address of the specified block for addresses A

Figure 1.29.10. Timing for reading lock bit status

Figure 1.29.11. Timing for enabling the lock bit

CLK1

RxD1

TxD1

RTS1(BUSY)

(M16C reception data)

(M16C transmit data)

CLK1

RxD1

TxD1

RTS1(BUSY)

(M16C reception data)

(M16C transmit data)

Appendix Standard Serial I/O Mode 1 (Flash Memory Version)

Mitsubishi microcomputers

M16C / 62A Group

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

246

Lock Bit Disable Command

This command disables the lock bit. The command code "75

" is sent with the 1st byte of the serial

transmission. This command only disables the lock bit function; it does not set the lock bit itself.

However, if an erase command is executed after executing the lock bit disable command, "0" (locked)

lock bit data is set to "1" (unlocked) after the erase operation ends. In any case, after the reset is

cancelled, the lock bit is enabled.

Figure 1.29.12. Timing for disabling the lock bit

Download Command

This command downloads a program to the RAM for execution. Execute the download command as

explained here following.

(1) Transfer the "FA

" command code with the 1st byte.

(2) Transfer the program size with the 2nd and 3rd bytes.

(3) Transfer the check sum with the 4th byte. The check sum is added to all data sent with the 5th

byte onward.

(4) The program to execute is sent with the 5th byte onward.

When all data has been transmitted, if the check sum matches, the downloaded program is executed.

The size of the program will vary according to the internal RAM.

Figure 1.29.13. Timing for download

CLK1

RxD1

TxD1

RTS1(BUSY)

(M16C reception data)

(M16C transmit data)

Program

data

Program

data

Data size (high)

Data size (low)

Check
sum

CLK1

RxD1

TxD1

RTS1(BUSY)

(M16C reception data)

(M16C transmit data)

Appendix Standard Serial I/O Mode 1 (Flash Memory Version)

Mitsubishi microcomputers

M16C / 62A Group

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

247

Version Information Output Command

This command outputs the version information of the control program stored in the boot area. Execute

the version information output command as explained here following.

(1) Transfer the "FB

" command code with the 1st byte.

(2) The version information will be output from the 2nd byte onward. This data is composed of 8

ASCII code characters.

Figure 1.29.14. Timing for version information output

Boot ROM Area Output Command

This command outputs the control program stored in the boot ROM area in one page blocks (256

bytes). Execute the boot ROM area output command as explained here following.

(1) Transfer the "FC

" command code with the 1st byte.

(2) Transfer addresses A

to A

and A

to A

with the 2nd and 3rd bytes respectively.

(3) From the 4th byte onward, data (D

) for the page (256 bytes) specified with addresses A

will be output sequentially from the smallest address first, in sync with the fall of the clock.

Figure 1.29.15. Timing for boot ROM area output

'X'

'V'

'E'

'R'

CLK1

RxD1

TxD1

RTS1(BUSY)

(M16C reception data)

(M16C transmit data)

data0

data255

CLK1

RxD1

TxD1

RTS1(BUSY)

(M16C reception data)

(M16C transmit data)

Appendix Standard Serial I/O Mode 1 (Flash Memory Version)

Mitsubishi microcomputers

M16C / 62A Group

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

248

ID Check

This command checks the ID code. Execute the boot ID check command as explained here following.

(1) Transfer the "F5

" command code with the 1st byte.

(2) Transfer addresses A

to A

, A

to A

and A

to A

of the 1st byte of the ID code with the 2nd,

3rd and 4th bytes respectively.

(3) Transfer the number of data sets of the ID code with the 5th byte.

(4) The ID code is sent with the 6th byte onward, starting with the 1st byte of the code.

Figure 1.29.16. Timing for the ID check

ID Code

When the flash memory is not blank, the ID code sent from the peripheral units and the ID code written

in the flash memory are compared to see if they match. If the codes do not match, the command sent

from the peripheral units is not accepted. An ID code contains 8 bits of data. Area is, from the 1st byte,

addresses 0FFFDF

, 0FFFE3

, 0FFFEB

, 0FFFEF

, 0FFFF3

, 0FFFF7

and 0FFFFB

. Write

a program into the flash memory, which already has the ID code set for these addresses.

Figure 1.29.17. ID code storage addresses

ID size

ID1

ID7

CLK1

RxD1

TxD1

RTS1(BUSY)

(M16C reception

data)

(M16C transmit

data)

Reset vector

Watchdog timer vector

Single step vector

Address match vector

BRK instruction vector

Overflow vector

Undefined instruction vector

ID7

ID6

ID5

ID4

ID3

ID2

ID1

DBC vector

NMI vector

0FFFFC

to 0FFFFF

0FFFF8

to 0FFFFB

0FFFF4

to 0FFFF7

0FFFF0

to 0FFFF3

0FFFEC

to 0FFFEF

0FFFE8

to 0FFFEB

0FFFE4

to 0FFFE7

0FFFE0

to 0FFFE3

0FFFDC

to 0FFFDF

4 bytes

Address

Appendix Standard Serial I/O Mode 1 (Flash Memory Version)

Mitsubishi microcomputers

M16C / 62A Group

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

250

Data Protection (Block Lock)

Each of the blocks in Figure 1.29.19 have a nonvolatile lock bit that specifies protection (block lock)

against erasing/writing. A block is locked (writing "0" for the lock bit) with the lock bit program command.

Also, the lock bit of any block can be read with the read lock bit status command.

Block lock disable/enable is determined by the status of the lock bit itself and execution status of the lock

bit disable and lock enable bit commands.

(1) After the reset has been cancelled and the lock bit enable command executed, the specified block

can be locked/unlocked using the lock bit (lock bit data). Blocks with a "0" lock bit data are locked

and cannot be erased or written in. On the other hand, blocks with a "1" lock bit data are unlocked

and can be erased or written in.

(2) After the lock bit disable command has been executed, all blocks are unlocked regardless of lock bit

data status and can be erased or written in. In this case, lock bit data that was "0" (locked) before the

block was erased is set to "1" (unlocked) after erasing, therefore the block is actually unlocked with

the lock bit.

Figure 1.29.19. Blocks in the user area

0C0000

0D0000

Block 6 : 64K byte

Block 5 : 64K byte

0E0000

Block 4 : 64K byte

0F0000

Block 3 : 32K byte

0F8000

Block 2 : 8K byte

0FA000

Block 1 : 8K byte

Block 0 : 16K byte

0FC000

User ROM area

0FFFFF

Flash memory

size

Flash memory

start address

256Kbytes

0C0000

128Kbytes

0E0000

Appendix Standard Serial I/O Mode 1 (Flash Memory Version)

Mitsubishi microcomputers

M16C / 62A Group

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

251

Status Register (SRD)

The status register indicates operating status of the flash memory and status such as whether an erase

operation or a program ended successfully or in error. It can be read by writing the read status register

command (70

). Also, the status register is cleared by writing the clear status register command (50

Table 1.29.2 gives the definition of each status register bit. After clearing the reset, the status register

outputs "80

Table 1.29.2. Status register (SRD)

Write State Machine (WSM) Status (SR7)

The write state machine (WSM) status indicates the operating status of the flash memory. When

power is turned on, "1" (ready) is set for it. The bit is set to "0" (busy) during an auto write or auto erase

operation, but it is set back to "1" when the operation ends.

Erase Status (SR5)

The erase status reports the operating status of the auto erase operation. If an erase error occurs, it is

set to "1". When the erase status is cleared, it is set to "0".

Program Status (SR4)

The program status reports the operating status of the auto write operation. If a write error occurs, it is

set to "1". When the program status is cleared, it is set to "0".

Block Status After Program (SR3)

If excessive data is written (phenomenon whereby the memory cell becomes depressed which results

in data not being read correctly), "1" is set for the block status after-program at the end of the page

write operation. In other words, when writing ends successfully, "80

" is output; when writing fails,

"90

" is output; and when excessive data is written, "88

" is output.

If "1" is written for any of the SR5, SR4 or SR3 bits, the page program, block erase, erase all unlocked

blocks and lock bit program commands are not accepted. Before executing these commands, execute

the clear status register command (50

) and clear the status register.

SRD0 bits

SR7 (bit7)

SR6 (bit6)

SR5 (bit5)

SR4 (bit4)

SR3 (bit3)

SR2 (bit2)

SR1 (bit1)

SR0 (bit0)

Status name

Write state machine (WSM) status

Reserved

Erase status

Program status

Block status after program

Reserved

Definition

"1" "0"

Ready

Terminated in error

Busy

Terminated normally

Appendix Standard Serial I/O Mode 1 (Flash Memory Version)

Mitsubishi microcomputers

M16C / 62A Group

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

252

Status Register 1 (SRD1)

Status register 1 indicates the status of serial communications, results from ID checks and results from

check sum comparisons. It can be read after the SRD by writing the read status register command (70

Also, status register 1 is cleared by writing the clear status register command (50

Table 1.29.3 gives the definition of each status register 1 bit. "00

" is output when power is turned ON

and the flag status is maintained even after the reset.

Table 1.29.3. Status register 1 (SRD1)

Boot Update Completed Bit (SR15)

This flag indicates whether the control program was downloaded to the RAM or not, using the down-

load function.

Check Sum Match Bit (SR12)

This flag indicates whether the check sum matches or not when a program, is downloaded for execu-

tion using the download function.

ID Check Completed Bits (SR11 and SR10)

These flags indicate the result of ID checks. Some commands cannot be accepted without an ID

check.

Data Receive Time Out (SR9)

This flag indicates when a time out error is generated during data reception. If this flag is attached

during data reception, the received data is discarded and the microcomputer returns to the command

wait state.

SRD1 bits

SR15 (bit7)

SR14 (bit6)

SR13 (bit5)

SR12 (bit4)

SR11 (bit3)

SR10 (bit2)

SR9 (bit1)

SR8 (bit0)

Status name

Boot update completed bit

Reserved

Check sum match bit

ID check completed bits

Data receive time out

Reserved

Definition

"1" "0"

Update co

mpleted

Match

00
01
10
11

Not update

Mismatch

Normal operation

Not verified
Verification mismatch
Reserved
Verified

Time out

Appendix Standard Serial I/O Mode 1 (Flash Memory Version)

Mitsubishi microcomputers

M16C / 62A Group

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

253

Full Status Check

Results from executed erase and program operations can be known by running a full status check. Figure

1.29.20 shows a flowchart of the full status check and explains how to remedy errors which occur.

Read status register

SR4=1 and SR5

=1 ?

Command

sequence error

YES

SR5=0?

YES

Block erase error

SR4=0?

YES

Program error (page

or lock bit)

SR3=0?

YES

Program error

(block)

End (block erase, program)

Execute the clear status register command (50

)

to clear the status register. Try performing the
operation one more time after confirming that the
command is entered correctly.

Should a block erase error occur, the block in error
cannot be used.

Execute the read lock bit status command (71

)

to see if the block is locked. After removing lock,
execute write operation in the same way. If the
error still occurs, the page in error cannot be
used.

After erasing the block in error, execute write
operation one more time. If the same error still
occurs, the block in error cannot be used.

Note: When one of SR5 to SR3 is set to 1, none of the page program, block erase,

erase all unlock blocks and lock bit program commands is accepted. Execute the
clear status register command (50

) before executing these commands.

Figure 1.29.20. Full status check flowchart and remedial procedure for errors

Appendix Standard Serial I/O Mode 2 (Flash Memory Version)

Mitsubishi microcomputers

M16C / 62A Group

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

255

Overview of standard serial I/O mode 2 (clock asynchronized)

In standard serial I/O mode 2, software commands, addresses and data are input and output between the

MCU and peripheral units (serial programer, etc.) using 2-wire clock-asynchronized serial I/O (UART1).

Standard serial I/O mode 2 is engaged by releasing the reset with the P6

(CLK

) pin "L" level.

The TxD

pin is for CMOS output. Data transfer is in 8-bit units with LSB first, 1 stop bit and parity OFF.

After the reset is released, connections can be established at 9,600 bps when initial communications (Fig-

ure 1.29.22) are made with a peripheral unit. However, this requires a main clock with a minimum 2 MHz

input oscillation frequency. Baud rate can also be changed from 9,600 bps to 19,200, 38,400 or 57,600 bps

by executing software commands. However, communication errors may occur because of the oscillation

frequency of the main clock. If errors occur, change the main clock's oscillation frequency and the baud

rate.

After executing commands from a peripheral unit that requires time to erase and write data, as with erase

and program commands, allow a sufficient time interval or execute the read status command and check

how processing ended, before executing the next command.

Data and status registers in memory can be read after transmitting software commands. Status, such as

the operating state of the flash memory or whether a program or erase operation ended successfully or not,

can be checked by reading the status register. Here following are explained initial communications with

peripheral units, how frequency is identified and software commands.

Initial communications with peripheral units

After the reset is released, the bit rate generator is adjusted to 9,600 bps to match the oscillation fre-

quency of the main clock, by sending the code as prescribed by the protocol for initial communications

with peripheral units (Figure 1.29.22).

(1) Transmit "B0

" from a peripheral unit. If the oscillation frequency input by the main clock is 10 or 16

MHz, the MCU with internal flash memory outputs the "B0

" check code. If the oscillation frequency

is anything other than 10 or 16 MHz, the MCU does not output anything.

(2) Transmit "00

" from a peripheral unit 16 times. (The MCU with internal flash memory sets the bit

rate generator so that "00

" can be successfully received.)

(3) The MCU with internal flash memory outputs the "B0

" check code and initial communications end

successfully *

. Initial communications must be transmitted at a speed of 9,600 bps and a transfer

interval of a minimum 15 ms. Also, the baud rate at the end of initial communications is 9,600 bps.

*1. If the peripheral unit cannot receive "B0

" successfully, change the oscillation frequency of the main clock.

Figure 1.29.22. Peripheral unit and initial communication

MCU with internal

flash memory

Peripheral unit

(1) Transfer "B0

If the oscillation frequency input
by the main clock is 10 or 16
MHz, the MCU outputs "B0

". If

other than 10 or 16 MHz, the
MCU does not output anything.

(2) Transfer "00

" 16 times

At least 15ms
transfer interval

1st

2nd

15 th

16th

(3) Transfer check code "B0

"B0

"00

"B0

"00

Reset

The bit rate generator setting completes (9600bps)

Appendix Standard Serial I/O Mode 2 (Flash Memory Version)

Mitsubishi microcomputers

M16C / 62A Group

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

257

Software Commands

Table 1.29.5 lists software commands. In the standard serial I/O mode 2, erase operations, programs and

reading are controlled by transferring software commands via the RxD

pin. Standard serial I/O mode 2

adds four transmission speed commands - 9,600, 19,200, 38,400 and 57,600 bps - to the software com-

mands of standard serial I/O mode 1. Software commands are explained here below.

Table 1.29.5. Software commands (Standard serial I/O mode 2)

Control command

2nd byte 3rd byte 4th byte 5th byte 6th byte

Page read

Page program

Block erase

Erase all unlocked blocks

Read status register

Clear status register

Read lock bit status

Lock bit program

Lock bit enable

Lock bit disable

ID check function

Download function

Version data output function

Boot ROM area output

function

Read check data

Baud rate 9600

Baud rate 19200

Baud rate 38400

Baud rate 57600

Address
(middle)

SRD

output

Address
(middle)

Address

(low)

Size (low)

Version

data

output

Address
(middle)

Check

data (low)

Address

(high)

Address

(high)

Address

(high)

SRD1

output

Address

(high)

Address

(high)

Address
(middle)

Size

(high)

Version

data

output

Address

(high)

Check

data

(high)

Data

output

Data

input

Lock bit

data

output

Address

(high)

Check-

sum

Version

data

output

Data

output

Data

output

Data

input

ID size

Data

input

Version

data

output

Data

output

Data

output

Data

input

ID1

required

number

of times

Version

data

output

Data

output

Data

output to

259th byte

Data input

to 259th

byte

To ID7

Version

data

output to

9th byte

Data

output to

259th byte

When ID is
not verified

Not

acceptable

Not

acceptable

Not

acceptable

Not

acceptable

Acceptable

Not

acceptable

Not

acceptable

Not

acceptable

Not

acceptable

Not

acceptable

Acceptable

Not

acceptable

Acceptable

Not

acceptable

Not

acceptable

Acceptable

1st byte

transfer

Note 1: Shading indicates transfer from flash memory microcomputer to peripheral unit. All other data is trans-

ferred from the peripheral unit to the flash memory microcomputer.

Note 2: SRD refers to status register data. SRD1 refers to status register 1 data.

Note 3: All commands can be accepted when the flash memory is totally blank.

Appendix Standard Serial I/O Mode 2 (Flash Memory Version)

Mitsubishi microcomputers

M16C / 62A Group

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

258

Page Read Command

This command reads the specified page (256 bytes) in the flash memory sequentially one byte at a

time. Execute the page read command as explained here following.

(1) Transfer the "FF

" command code with the 1st byte.

(2) Transfer addresses A

to A

and A

to A

with the 2nd and 3rd bytes respectively.

(3) From the 4th byte onward, data (D

) for the page (256 bytes) specified with addresses A

will be output sequentially from the smallest address first.

Figure 1.29.23. Timing for page read

Read Status Register Command

This command reads status information. When the "70

" command code is sent with the 1st byte, the

contents of the status register (SRD) specified with the 2nd byte and the contents of status register 1

(SRD1) specified with the 3rd byte are read.

Figure 1.29.24. Timing for reading the status register

data0

data255

RxD1

TxD1

(M16C reception data)

(M16C transmit data)

SRD

output

SRD1

output

RxD1

TxD1

(M16C reception data)

(M16C transmit data)

Appendix Standard Serial I/O Mode 2 (Flash Memory Version)

Mitsubishi microcomputers

M16C / 62A Group

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

259

Clear Status Register Command

This command clears the bits (SR3SR5) which are set when the status register operation ends in

error. When the "50

" command code is sent with the 1st byte, the aforementioned bits are cleared.

Figure 1.29.25. Timing for clearing the status register

Page Program Command

This command writes the specified page (256 bytes) in the flash memory sequentially one byte at a

time. Execute the page program command as explained here following.

(1) Transfer the "41

" command code with the 1st byte.

(2) Transfer addresses A

to A

and A

to A

with the 2nd and 3rd bytes respectively.

(3) From the 4th byte onward, as write data (D

) for the page (256 bytes) specified with addresses

to A

is input sequentially from the smallest address first, that page is automatically written.

The result of the page program can be known by reading the status register. For more information,

see the section on the status register.

Each block can be write-protected with the lock bit. For more information, see the section on the data

protection function. Additional writing is not allowed with already programmed pages.

Figure 1.29.26. Timing for the page program

RxD1

TxD1

(M16C reception data)

(M16C transmit data)

RxD1

TxD1

data0

data255

(M16C reception data)

(M16C transmit data)

Appendix Standard Serial I/O Mode 2 (Flash Memory Version)

Mitsubishi microcomputers

M16C / 62A Group

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

261

Erase All Unlocked Blocks Command

This command erases the content of all blocks. Execute the erase all unlocked blocks command as

explained here following.

(1) Transfer the "A7

" command code with the 1st byte.

(2) Transfer the verify command code "D0

" with the 2nd byte. With the verify command code, the

erase operation will start and continue for all blocks in the flash memory.

The result of the erase operation can be known by reading the status register. Each block can be erase-

protected with the lock bit. For more information, see the section on the data protection function.

Figure 1.29.28. Timing for erasing all unlocked blocks

Lock Bit Program Command

This command writes "0" (lock) for the lock bit of the specified block. Execute the lock bit program

command as explained here following.

(1) Transfer the "77

" command code with the 1st byte.

(2) Transfer addresses A

to A

and A

to A

with the 2nd and 3rd bytes respectively.

(3) Transfer the verify command code "D0

" with the 4th byte. With the verify command code, "0" is

written for the lock bit of the specified block. Write the highest address of the specified block for

addresses A

to A

Lock bit status can be read with the read lock bit status command. For information on the lock bit

function, reset procedure and so on, see the section on the data protection function.

Figure 1.29.29. Timing for the lock bit program

RxD1

TxD1

(M16C reception data)

(M16C transmit data)

RxD1

TxD1

(M16C reception data)

(M16C transmit data)

Appendix Standard Serial I/O Mode 2 (Flash Memory Version)

Mitsubishi microcomputers

M16C / 62A Group

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

262

Lock Bit Enable Command

This command enables the lock bit in blocks whose bit was disabled with the lock bit disable com-

mand. The command code "7A

" is sent with the 1st byte of the serial transmission. This command

only enables the lock bit function; it does not set the lock bit itself.

Read Lock Bit Status Command

This command reads the lock bit status of the specified block. Execute the read lock bit status com-

mand as explained here following.

(1) Transfer the "71

" command code with the 1st byte.

(2) Transfer addresses A

to A

and A

to A

with the 2nd and 3rd bytes respectively.

(3) The lock bit data of the specified block is output with the 4th byte. The lock bit data is the 6th

bit(D

) of the output data. Write the highest address of the specified block for addresses A

Figure 1.29.30. Timing for reading lock bit status

Figure 1.29.31. Timing for enabling the lock bit

RxD1

TxD1

(M16C reception data)

(M16C transmit data)

RxD1

TxD1

(M16C reception data)

(M16C transmit data)

Appendix Standard Serial I/O Mode 2 (Flash Memory Version)

Mitsubishi microcomputers

M16C / 62A Group

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

263

Lock Bit Disable Command

This command disables the lock bit. The command code "75

" is sent with the 1st byte of the serial

transmission. This command only disables the lock bit function; it does not set the lock bit itself.

However, if an erase command is executed after executing the lock bit disable command, "0" (locked)

lock bit data is set to "1" (unlocked) after the erase operation ends. In any case, after the reset is

cancelled, the lock bit is enabled.

Figure 1.29.32. Timing for disabling the lock bit

Download Command

This command downloads a program to the RAM for execution. Execute the download command as

explained here following.

(1) Transfer the "FA

" command code with the 1st byte.

(2) Transfer the program size with the 2nd and 3rd bytes.

(3) Transfer the check sum with the 4th byte. The check sum is added to all data sent with the 5th

byte onward.

(4) The program to execute is sent with the 5th byte onward.

When all data has been transmitted, if the check sum matches, the downloaded program is executed.
The size of the program will vary according to the internal RAM.

Figure 1.29.33. Timing for download

RxD1

TxD1

(M16C reception data)

(M16C transmit data)

Program

data

Program

data

Data size (high)

Data size (low)

Check
sum

RxD1

TxD1

(M16C reception data)

(M16C transmit data)

Appendix Standard Serial I/O Mode 2 (Flash Memory Version)

Mitsubishi microcomputers

M16C / 62A Group

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

264

Version Information Output Command

This command outputs the version information of the control program stored in the boot area. Execute

the version information output command as explained here following.

(1) Transfer the "FB

" command code with the 1st byte.

(2) The version information will be output from the 2nd byte onward. This data is composed of 8

ASCII code characters.

Figure 1.29.34. Timing for version information output

Boot ROM Area Output Command

This command outputs the control program stored in the boot ROM area in one page blocks (256

bytes). Execute the boot ROM area output command as explained here following.

(1) Transfer the "FC

" command code with the 1st byte.

(2) Transfer addresses A

to A

and A

to A

with the 2nd and 3rd bytes respectively.

(3) From the 4th byte onward, data (D

) for the page (256 bytes) specified with addresses A

will be output sequentially from the smallest address first.

Figure 1.29.35. Timing for boot ROM area output

'X'

'V'

'E'

'R'

RxD1

TxD1

(M16C reception data)

(M16C transmit data)

data0

data255

RxD1

TxD1

(M16C reception data)

(M16C transmit data)

Appendix Standard Serial I/O Mode 2 (Flash Memory Version)

Mitsubishi microcomputers

M16C / 62A Group

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

265

ID Check

This command checks the ID code. Execute the boot ID check command as explained here following.

(1) Transfer the "F5

" command code with the 1st byte.

(2) Transfer addresses A

to A

, A

to A

and A

to A

of the 1st byte of the ID code with the 2nd,

3rd and 4th bytes respectively.

(3) Transfer the number of data sets of the ID code with the 5th byte.

(4) The ID code is sent with the 6th byte onward, starting with the 1st byte of the code.

Figure 1.29.36. Timing for the ID check

ID Code

When the flash memory is not blank, the ID code sent from the peripheral units and the ID code written

in the flash memory are compared to see if they match. If the codes do not match, the command sent

from the peripheral units is not accepted. An ID code contains 8 bits of data. Area is, from the 1st byte,

addresses 0FFFDF

, 0FFFE3

, 0FFFEB

, 0FFFEF

, 0FFFF3

, 0FFFF7

and 0FFFFB

. Write

a program into the flash memory, which already has the ID code set for these addresses.

Figure 1.29.37. ID code storage addresses

ID size

ID1

ID7

RxD1

TxD1

(M16C reception

data)

(M16C transmit

data)

Reset vector

Watchdog timer vector

Single step vector

Address match vector

BRK instruction vector

Overflow vector

Undefined instruction vector

ID7

ID6

ID5

ID4

ID3

ID2

ID1

DBC vector

NMI vector

0FFFFC

to 0FFFFF

0FFFF8

to 0FFFFB

0FFFF4

to 0FFFF7

0FFFF0

to 0FFFF3

0FFFEC

to 0FFFEF

0FFFE8

to 0FFFEB

0FFFE4

to 0FFFE7

0FFFE0

to 0FFFE3

0FFFDC

to 0FFFDF

4 bytes

Address

Appendix Standard Serial I/O Mode 2 (Flash Memory Version)

Mitsubishi microcomputers

M16C / 62A Group

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

266

Read Check Data

This command reads the check data that confirms that the write data, which was sent with the page

program command, was successfully received.

(1) Transfer the "FD

" command code with the 1st byte.

(2) The check data (low) is received with the 2nd byte and the check data (high) with the 3rd.

To use this read check data command, first execute the command and then initialize the check data.

Next, execute the page program command the required number of times. After that, when the read

check command is executed again, the check data for all of the read data that was sent with the page

program command during this time is read. The check data is the result of CRC operation of write

data.

Figure 1.29.38. Timing for the read check data

Check data (low)

RxD1

TxD1

(M16C reception data)

(M16C transmit data)

Check data (high)

Baud Rate 9600

This command changes baud rate to 9,600 bps. Execute it as follows.

(1) Transfer the "B0

" command code with the 1st byte.

(2) After the "B0

" check code is output with the 2nd byte, change the baud rate to 9,600 bps.

Figure 1.29.39. Timing of baud rate 9600

RxD1

TxD1

(M16C reception data)

(M16C transmit data)

Appendix Standard Serial I/O Mode 2 (Flash Memory Version)

Mitsubishi microcomputers

M16C / 62A Group

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

267

Baud Rate 19200

This command changes baud rate to 19,200 bps. Execute it as follows.

(1) Transfer the "B1

" command code with the 1st byte.

(2) After the "B1

" check code is output with the 2nd byte, change the baud rate to 19,200 bps.

Figure 1.29.40. Timing of baud rate 19200

Baud Rate 38400

This command changes baud rate to 38,400 bps. Execute it as follows.

(1) Transfer the "B2

" command code with the 1st byte.

(2) After the "B2

" check code is output with the 2nd byte, change the baud rate to 38,400 bps.

Figure 1.29.41. Timing of baud rate 38400

Baud Rate 57600

This command changes baud rate to 57,600 bps. Execute it as follows.

(1) Transfer the "B3

" command code with the 1st byte.

(2) After the "B3

" check code is output with the 2nd byte, change the baud rate to 57,600 bps.

Figure 1.29.42. Timing of baud rate 57600

RxD1

TxD1

(M16C reception data)

(M16C transmit data)

RxD1

TxD1

(M16C reception data)

(M16C transmit data)

RxD1

TxD1

(M16C reception data)

(M16C transmit data)

Contents for change

Revision

date

Version

Revision history

M16C/62A Group data sheet

Mitsubishi microcomputers

M16C / 62A Group

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

270

Revision History

REV.A1

99.12.21

Page 145 Note 2

· Before data can be written to the SI/Oi transmit/receive register (addresses

0360

, 0364

), the CLKi pin input must be in the low state. Also, before rewriting

the SI/Oi Control Register (addresses 0362

, 0366

)'s bit 7 (S

OUTi

initial value

set bit), make sure the CLKi pin input is held low. ---> · Before data can be written

to the SI/Oi transmit/receive register (addresses 0360

, 0364

), the CLKi pin

input must be in the high state. Also, before rewriting the SI/Oi Control Register

(addresses 0362

, 0366

)'s bit 7 (S

OUTi

initial value set bit), make sure the CLKi

pin input is held high.

00.7.3

REV. A2

Page 43, Figure 1.10.6

Note: Writing a value to an address after "1" is written to this bit returns the bit to

"0" . Other bits do not automatically return to "0" and they must therefore

be reset by the program.

Page 144, Figure 1.16.32, bit 5 of the SI/Oi control register (i=3, 4)

Transfer direction lect bit --->Transfer direction select bit

Page 144, Figure 1.16.32, Note 2

When using the port as an input/output port by setting the SI/Oi port select bit (i =

3, 4) to "1", be sure to set the sync clock select bit to "1".

--->

When using the port as an input/output port by setting the SI/Oi port select bit (i =

3, 4) to "0", be sure to set the sync clock select bit to "1".

00.7.10

Page 115, 139, Bit 3 of the UART2 special mode register 2 (bit symbol)

ASL --> ALS

01.3.27

REV. B

Page 2 Note is added in Figure 1.1.1.

Page 3 Note is added in Figure 1.1.2.

Page 10 Explanation of "Memory" is partly revised.

Page 10 Figure 1.3.1 is partly revised.

Page 22 Figure 1.7.1 is partly revised.

Page 23 Figure 1.7.2 is partly revised.

Page 23 "Internal Reserved Area Expansion Bit (PM13)" is added.

Page 24 Figure 1.7.3 is partly revised.

Page 25 Explanation of "(3) Selecting separate/multiplex bus" is partly revised.

Page 28 Explanation of "(2) Chip select signal" is partly added.

Page 29 Figure 1.9.2 is added.

Page 37 Explanation of "(2) Sub-clock" is partly revised.

Page 38 Figure 1.10.4 is partly revised.

Page 39 Explanation of "Stop Mode" is partly revised.

Page 39 Table 1.10.2 is partly revised.

Page 40 Explanation of "Wait Mode" is partly revised.

Page 40 Table 1.10.3 is partly revised.

Page 42 Explanation of "Power Control" is partly revised.

Page 62 Explanation of "Address Match Interruptl" is partly revised.

Contents for change

Revision

date

Version

Revision history

M16C/62A Group data sheet

Mitsubishi microcomputers

M16C / 62A Group

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

271

Page 63 Explanation of "Precautions for Interrupts" is partly revised.

Page 64 Note is added in Figure 1.11.13.

Page 65 Explanation of "Watchdog Timer" is partly revised.

Page 73 Table 1.13.5 is partly revised.

Page 75 Explanation of "DMA request bit" is partly revised.

Page 80 Figure 1.14.5 is partly revised.

Page 84 Table 1.14.3 is partly revised.

Page 93 Table 1.14.8 is partly revised.

Page 93 Figure 1.14.19 is partly revised.

Page 95 Figure 1.15.1 is partly revised.

Page 96 Figure 1.15.2 is partly revised.

Page 97 Figure 1.15.3 is partly revised.

Page 98-99 Explanation of "Three-phase motor driving waveform output mode" is partly

revised.

Page 98 Figure 1.15.4 is partly revised.

Page 100 Figure 1.15.5 is partly revised.

Page 101 Explanation of "Triangular wave modulation" is partly revised.

Page 103 Figure 1.15.7 is partly revised.

Page 104 Explanation of "Satooth modulation" is partly revised.

Page 106 Figure 1.15.9 is partly revised.

Page 111 Figure 1.16.4 is partly revised.

Page 114 Figure 1.16.7 is partly revised.

Page 115 Figure 1.16.8 is partly revised.

Page 116 Figure 1.16.9 is partly revised.

Page 123 Explanation of "(d) Bus collision detection function (UART2)" is partly revised.

Page 134 Explanation of "(a) Function for outputting a parity error signal" is revised.

Page 136 Figure 1.16.26 is partly revised.

Page 141 Table 1.16.12 is partly revised.

Page 145 Figure 1.16.32 is partly revised.

Page 146 Table 1.16.13 is partly revised.

Page 148 Note 2 in Table 1.17.1 is partly revised.

Page 153 Table 1.17.3 is partly revised.

Page 157 Explanation of "(a) Sample and hold" is partly revised.

Page 162 Explanation of "Programmable I/O Ports" is partly revised.

Page 167 Note 2 is added in Figure 1.20.6.

Page 168 Note 2 is added in Figure 1.20.7.

Page 169 Figure 1.20.8 is partly revised.

Page 171 Table 1.20.1 and Table 1.20.2 are partly revised.

"Usage Precaution" is excluded (which have described on pages 171-174 of Rev. A2).

Page 172 Explanation of "Items to be submitted when ordering masked ROM version" is

revised.

Page 173-199 All symbols of Ta are revised to Topr.

Page 188 Table 1.23.23 is partly revised.

Page 216 Table 1.25.1 is partly revised.

Page 219 Explanation of "Outline Performance (CPU Rewrite Mode)" is partly revised.

01.3.27

REV. B

Contents for change

Revision

date

Version

Revision history

M16C/62A Group data sheet

Mitsubishi microcomputers

M16C / 62A Group

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

272

Page 220 Figure 1.26.1 is partly revised.

Page 221 Figure 1.26.2 is partly revised.

Page 222 Explanation of "(1) Operation speed" is partly revised.

Page 222 Explanation of "(3) Interrupts inhibited against use" is revised.

Page 222 Explanation of "(6) Access disable" is partly revised.

Page 222 Explanation of "(7) How to access" is partly revised.

Page 223 "(8) Writing in the user ROM area" and "(9) Using the lock bit" are added.

Page 226 Figure 1.26.5 is partly revised.

Page 230 Explanation of "Program status (SR4)" is partly revised.

Page 232 Explanation of "ROM code protect function" is partly revised.

Page 234 Explanation of "Parallel I/O Mode" is partly revised.

Page 239 Explanation of "Overview of standard serial I/O mode 1 (clock synchronized)" is

partly revised.

Page 241 Explanation of "Page Read Command" is partly revised.

Page 243 Explanation of "Block Erase Command" is partly revised.

Page 245 Figure 1.29.10 and explanation of "Read Lock Bit Status Command" are partly

revised.

Page 247 Explanation of "Boot ROM area Output Command" is partly revised.

Page 250 Explanation of "Data Protection (Block Lock)" is partly revised.

Page 251 Explanation of "Block Status After Program (SR3)" is partly revised.

Page 252 Table 1.29.3 is partly revised.

Page 258 Explanation of "Page Read Command" is partly revised.

Page 259 Explanation of "Clear Status Register Command" is partly revised.

Page 259 Explanation of "Page Program Command" is partly revised.

Page 260 Explanation of "Block Erase Command" is partly revised.

Page 261 Explanation of "Erase All Unlocked Blocks Command" is partly revised.

Page 261 Explanation of "Lock Bit Program Command" is partly revised.

Page 262 Figure 1.29.30 and explanation of "Read Lock Bit Status Command" is partly

revised.

Page 264 Explanation of "Boot ROM Area Output Command" is partly revised.

Page 269 Table of "Differences in SFR between M16C/62A and M16C/62" is added.

01.3.27

REV. B

01.4.6

Page 21 Explanation of "Processor Mode" is partly revised.

Page 65 Explanation of "Watchdog Timer" is partly revised.

Page 158 Explanation of "D-A Converter" is partly revised.

Page 83 Figure 1.14.8 is partly revised.

Page 176 Table 1.23.6 is partly revised.

01.4.23

01.5.10

REV. B1

Page 65 Explanation of "Watchdog Timer" is partly added.

Keep safety first in your circuit designs!

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