MITSUBISHI MICROCOMPUTERS
M35046-XXXSP/FP
SCREEN CHARACTER and PATTERN DISPLAY CONTROLLERS
DESCRIPTION
The M35046-XXXSP/FP is a character pattern display control IC can
display on the liquid crystal display and the plasma display. It uses a
silicon gate CMOS process and it housed in a 20-pin shrink DIP pack-
age (M35046-XXXSP) or a 20-pin shrink SOP package (M35046-
XXXFP).
For M35046-001SP/FP that is a standard ROM version of M35046-
XXXSP/FP respectively, the character pattern is also mentioned.
FEATURES
Screen composition .................................... 24 columns
12 lines
Number of characters displayed ................................... 288 (Max.)
Character composition ..................................... 12
18 dot matrix
Characters available .............................................. 256 characters
Character sizes available .................... 4 (horizontal)
4 (vertical)
Display locations available
Horizontal direction .............................................. 1000 locations
Vertical direction .................................................. 1023 locations
Blinking .................................................................. Character units
Cycle : division of vertical synchronization signal into 32 or 64
Duty
: 25%, 50%, or 75%
Data input .................................. By the 16-bit serial input function
Coloring
Character color ..................................................... Character unit
Background coloring ............................................. Character unit
Matrix-outline (shadow) coloring .............. 8 colors (RGB output)
Specified by register
Border coloring ........................................ 8 colors (RGB output)
Specified by register
Raster coloring ........................................ 8 colors (RGB output)
Specified by register
Blanking
Character size blanking
Border size blanking
Matrix-outline blanking
All blanking (all raster area)
Output ports
4 shared output ports (toggled between RGB output)
4 dedicated output ports
Display RAM erase function
Display input frequency range ............... F
OSC
= 20MHz to 80MHz
Horizontal synchronous input frequency
........................................................ H.sync = 15 kHz to 130 kHz
Display oscillation stop function
APPLICATION
Liquid crystal display, Plasma display, Video projecter
Outline 20P4B
PIN CONFIGURATION (TOP VIEW)
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
CPOUT
@
V
DD2
VERT
HOR
P5/B
P4
P3/G
P2
P1/R
P0/BLNK0
@
V
SS
V
SS2
@
AC
CS
SCK
SIN
TCK
V
DD1
@
P6
P7
M35046 - XXXSP
Outline 20P2Q-A
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
CPOUT
@
V
DD2
VERT
HOR
P5/B
P4
P3/G
P2
P1/R
P0/BLNK0
@
V
SS1
VIR
@
AC
CS
SCK
SIN
TCK
V
DD1
@
P6
P7
M35046 - XXXFP
MITSUBISHI MICROCOMPUTERS
M35046-XXXSP/FP
SCREEN CHARACTER and PATTERN DISPLAY CONTROLLERS
2
Symbol
CPOUT
V
SS2
__
AC
__
CS
SCK
SIN
TCK
V
DD1
P6
P7
V
SS1
P0/BLNK0
P1/R
P2
P3/G
P4
P5/B
HOR
VERT
V
DD2
Input/
Output
Output
Input
Input
Input
Input
Input
Output
Output
Output
Output
Output
Output
Output
Output
Input
Input
Function
Connect loop filter to this pin.
Connect to GND.
When "L", this pin resets the internal IC circuit. Hysteresis input. Built-in pull-up resistor.
This is the chip select input pin, and when serial data transmission is being carried out, it
goes to "L". Hysteresis input. Built-in pull-up resistor.
__
When CS pin is "L", SIN serial data is taken in when SCK rises. Hysteresis input. Built-in
pull-up resistor.
This is the pin for serial input of data and addresses for the display control register and
the display data memory. Hysteresis input. Built-in pull-up resistor.
This is the pin for external clock input.
Please connect to +5V with the power pin.
This is the output port. Port data is set by PTD6.
This is the output port. Port data is set by PTD7.
Please connect to GND using circuit earthing pin.
This pin can be toggled between port pin output and BLNK0 signal output.
This pin can be toggled between port pin output and R signal output.
This is the output port. Port data is set by PTD2.
This pin can be toggled between port pin output and G signal output.
This is the output port. Port data is set by PTD4.
This pin can be toggled between port pin output and B signal output.
This pin inputs the horizontal synchronous signal. Hysteresis input.
This pin inputs the vertical synchronous signal. Hysteresis input.
Please connect to +5V with the power pin.
Pin name
Phase difference
Earthing pin
Auto-clear input
Chip select input
Serial clock input
Serial data input
External clock
Power pin
Port P6 output
Port P7 output
Earthing pin
Port P0 output
Port P1 output
Port P2 output
Port P3 output
Port P4 output
Port P5 output
Horizontal synchro-
nous signal input
Vertical synchro-
nous signal input
Power pin
Pin
Number
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
PIN DESCRIPTION
1.0k
1
0.01
F
2
47pF
2
CPOUT
1 Use at 1% precision
2 Use at 10% precision
1pin
MITSUBISHI MICROCOMPUTERS
M35046-XXXSP/FP
SCREEN CHARACTER and PATTERN DISPLAY CONTROLLERS
3
BLOCK DIAGRAM
4
1
5
6
8
20
3
11
2
CS
SCK
SIN
V
DD1
V
DD2
AC
V
SS
VIR
Clock oscillation
circuit for display
Timing generator
Polarity switching circuit
Address control
circuit
Data control
circuit
Display control
register
Display RAM
Display character ROM
Shift register
Blinking circuit
Reading address
control circuit
Display location
detection circuit
H counter
CPOUT
7
TCK
18
HOR
19
12
VERT
Synchronous signal
switching circuit
Display control
circuit
Port output
control circuit
Polarity
switching
circuti
Input control circuit
P0/BLNK0
13
P1/R
15
P3/G
17
P5/B
14
P2
16
P4
9P
6
10
P7
MITSUBISHI MICROCOMPUTERS
M35046-XXXSP/FP
SCREEN CHARACTER and PATTERN DISPLAY CONTROLLERS
4
DAF
DAE
DAD
DAC
DAB
DAA
DA9
DA8
DA7
DA6
DA5
DA4
DA3
DA2
DA1
DA0
0
BB
BG
BR
BLINK
B
G
R
C7
C6
C5
C4
C3
C2
C1
C0
0
BB
BG
BR
BLINK
B
G
R
C7
C6
C5
C4
C3
C2
C1
C0
0
EXCK0
VJT
DIVS1 DIVS0 DIV10
DIV9
DIV8
DIV7
DIV6
DIV5
DIV4
DIV3
DIV2
DIV1
DIV0
0
RSEL0 PTD7
PTD6
PTD5
PTD4
PTD3
PTD2
PTD1
PTD0
PTC5
PTC4
PTC3
PTC2
PTC1
PTC0
0
RSEL1 SPACE2 SPACE1 SPACE0 TEST9
HP9
HP8
HP7
HP6
HP5
HP4
HP3
HP2
HP1
HP0
0
EXCK1 TEST3 TEST2 TEST1 TEST0
VP9
VP8
VP7
VP6
VP5
VP4
VP3
VP2
VP1
VP0
0
TEST14 TEST5 TEST4 DSP11 DSP10 DSP9
DSP8
DSP7
DSP6 DSP5
DSP4
DSP3 DSP2
DSP1
DSP0
0
TEST10 VSZ1H1 VSZ1H0 VSZ1L1 VSZ1L0 V1SZ1 V1SZ0
LIN9
LIN8
LIN7
LIN6
LIN5
LIN4
LIN3
LIN2
0
TEST11 VSZ2H1 VSZ2H0 VSZ2L1 VSZ2L0 V18SZ1 V18SZ0 LIN17 LIN16 LIN15 LIN14 LIN13 LIN12 LIN11 LIN10
0
TEST12 HSZ21 HSZ20 HSZ11 HSZ10 BETA14 TEST8 TEST7 TEST6
FB
FG
FR
RB
RG
RR
0
TEST13 BLINK2 BLINK1 BLINK0 DSPON STOP RAMERS SYAD
BLK1
BLK0
POLH POLV VMASK
__
B/F
BCOL
000
16
11F
16
120
16
121
16
122
16
123
16
124
16
125
16
126
16
127
16
128
16
SCREEN CONSTITUTION
The screen lines and rows are determined from each address of the
display RAM. The screen constitution is shown in Figure 2.
MEMORY CONSTITUTION
Address 000
16
to 11F
16
are assigned to the display RAM, address
120
16
to 128
16
are assigned to the display control registers. The in-
ternal circuit is reset and all display control registers (address 120
16
__
to 128
16
) are set to "0" when the AC pin level is "L". And then RAM is
erased.
Memory constitution is shown in Figure 1.
.........
.........
Background
coloring
Character color
Character code
Row
Line
1
2
3
4
5
6
7
8
9
10
11
12
000
16
001
16
002
16
003
16
004
16
005
16
006
16
007
16
008
16
009
16
00A
16
00B
16
00C
16
00D
16
00E
16
00F
16
010
16
011
16
012
16
013
16
014
16
015
16
016
16
017
16
018
16
019
16
01A
16
01B
16
01C
16
01D
16
01E
16
01F
16
020
16
021
16
022
16
023
16
024
16
025
16
026
16
027
16
028
16
029
16
02A
16
02B
16
02C
16
02D
16
02E
16
02F
16
030
16
031
16
032
16
033
16
034
16
035
16
036
16
037
16
038
16
039
16
03A
16
03B
16
03C
16
03D
16
03E
16
03F
16
040
16
041
16
042
16
043
16
044
16
045
16
046
16
047
16
048
16
049
16
04A
16
04B
16
04C
16
04D
16
04E
16
04F
16
050
16
051
16
052
16
053
16
054
16
055
16
056
16
057
16
058
16
059
16
05A
16
05B
16
05C
16
05D
16
05E
16
05F
16
060
16
061
16
062
16
063
16
064
16
065
16
066
16
067
16
068
16
069
16
06A
16
06B
16
06C
16
06D
16
06E
16
06F
16
070
16
071
16
072
16
073
16
074
16
075
16
076
16
077
16
078
16
079
16
07A
16
07B
16
07C
16
07D
16
07E
16
07F
16
080
16
081
16
082
16
083
16
084
16
085
16
086
16
087
16
088
16
089
16
08A
16
08B
16
08C
16
08D
16
08E
16
08F
16
090
16
091
16
092
16
093
16
094
16
095
16
096
16
097
16
098
16
099
16
09A
16
09B
16
09C
16
09D
16
09E
16
09F
16
0A0
16
0A1
16
0A2
16
0A3
16
0A4
16
0A5
16
0A6
16
0A7
16
0A8
16
0A9
16
0AA
16
0AB
16
0AC
16
0AD
16
0AE
16
0AF
16
0B0
16
0B1
16
0B2
16
0B3
16
0B4
16
0B5
16
0B6
16
0B7
16
0B8
16
0B9
16
0BA
16
0BB
16
0BC
16
0BD
16
0BE
16
0BF
16
0C0
16
0C1
16
0C2
16
0C3
16
0C4
16
0C5
16
0C6
16
0C7
16
0C8
16
0C9
16
0CA
16
0CB
16
0CC
16
0CD
16
0CE
16
0CF
16
0D0
16
0D1
16
0D2
16
0D3
16
0D4
16
0D5
16
0D6
16
0D7
16
0D8
16
0D9
16
0DA
16
0DB
16
0DC
16
0DD
16
0DE
16
0DF
16
0E0
16
0E1
16
0E2
16
0E3
16
0E4
16
0E5
16
0E6
16
0E7
16
0E8
16
0E9
16
0EA
16
0EB
16
0EC
16
0ED
16
0EE
16
0EF
16
0F0
16
0F1
16
0F2
16
0F3
16
0F4
16
0F5
16
0F6
16
0F7
16
0F8
16
0F9
16
0FA
16
0FB
16
0FC
16
0FD
16
0FE
16
0FF
16
100
16
101
16
102
16
103
16
104
16
105
16
106
16
107
16
108
16
109
16
10A
16
10B
16
10C
16
10D
16
10E
16
10F
16
110
16
111
16
112
16
113
16
114
16
115
16
116
16
117
16
118
16
119
16
11A
16
11B
16
11C
16
11D
16
11E
16
11F
16
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
The hexadecimal numbers in the boxes show the display RAM address.
Fig. 2
Screen constitution
Fig. 1
Memory constitution
Blink-
ing
MITSUBISHI MICROCOMPUTERS
M35046-XXXSP/FP
SCREEN CHARACTER and PATTERN DISPLAY CONTROLLERS
5
For details, see (2) Setting display frequencies under Register
Supplementary Description.
It should be fixed to "0".
Alleviates continuous vertical jitters.
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
DIV0
DIV1
DIV2
DIV3
DIV4
DIV5
DIV6
DIV7
DIV8
DIV9
DIV10
DIVS0
DIVS1
VJT
EXCK0
0
1
2
3
4
5
6
7
8
9
A
B
C
D
E
REGISTERS DESCRIPTION
(1) Address 120
16
Set display frequency by frequency
value setting. Set N1 to be "N1=f
OSC
/
fH".
f
OSC
(MHz) : External clock frequency
for TCK pin (=display fre-
quency)
f
H
(kHz) : Horizontal synchronous sig-
nal frequency for HOR pin
Set registers DIVS0, DIVS1 (address
120
16
), RSEL0 (address 121
16
) and
RSEL1 (address 122
16
) according to
external clock frequency.
For details, see (2) Setting display fre-
quencies under Register Supplemen-
tary Description.
Any of this settings above is reguired
only when EXCK1=1, EXCK0=1.
Register
DA
Status
Contents
Function
Remarks
Display clock input
20 to 30MHz
Do not set
Do not set
20 to 80MHz
EXCK0
0
1
0
1
EXCK1
0
0
1
1
Set display frequency area.
See setting External Clock Input Mode
(to be input from the TCK terminal).
EXCK1 : address 123
16
1
H
C
l
o
c
k
n
u
m
b
e
r
(
N
1
)
E
x
t
e
r
n
a
l
c
l
o
c
k
H
o
r
i
z
o
n
t
a
l
s
y
n
c
h
r
o
n
i
z
e
d
s
i
g
n
a
l
Set external clock frequency value of horizontal oscillation fre-
quency.
N1 = (DIVn
2
n
)
N1: frequency value
10
n = 0
PDF 
ZIP