MITSUBISHI LSIs

MH8V7245BAZTJ -5, -6

Preliminary Spec.

MITSUBISHI
ELECTRIC

9/Nov. /1998

HYPER PAGE MODE 603979776 - BIT ( 8388608 - WORD BY 72 - BIT ) DYNAMIC RAM

MIT-DS-0284-0.0

( / 23 )

Specifications subject to
change without notice.

DESCRIPTION

The MH8V7245BAZTJ is 8388608-word x 72-bit dynamic
ram module. This consist of nine industry standard 8M x 8
dynamic RAMs in TSOP and three industry standard input
buffer in TSSOP.
The mounting of TSOP on a card edge dual in-line package
provides any application where high densities and large of
quantities memory are required.
This is a socket-type memory module ,suitable for easy
interchange or addition of module.

FEATURES

MH8V7245BAZTJ-5

Type name

/RAS

access

time

(max.ns)

/CAS

Address

/OE

Cycle

Power

access

time

(max.ns)

access

time

(max.ns)

access

time

(max.ns)

time

(min.ns)

dissipation

(typ.W)

110

Utilizes industry standard 8M x 8 RAMs in TSOP and industry
standard input buffer in TSSOP
168-pin (84-pin dual dual in-line package)
Single +3.3V(±0.3V) supply operation
Low stand-by power dissipation
116.2mW(Max) . . . . . . . . . . LVCMOS input level
Low operation power dissipation
MH8V7245BAZTJ -5 . . . . . . . . . . . . . . . . . . 4.32W(Max)
MH8V7245BAZTJ -6 . . . . . . . . . . . . . . . . . . 4.00W(Max)
All input are directly LVTTL compatible
All output are three-state and directly LVTTL compatible
Includes(0.22uF x 11) decoupling capacitors
4096 refresh cycle every 64ms (A0~11)
Hyper-page mode,Read-modify-write,
/CAS before /RAS refresh,Hidden refresh capabilities
JEDEC standard pin configuration & Buffered PD pin
Buffered input except /RAS and DQ
Gold plating contact pads

APPLICATION

Main memory unit for computers , Microcomputer memory

PD&ID TABLE

PD1 PD2 PD3 PD4 PD5 PD6 PD7 PD8 ID0

ID1

- 6

- 5

1 = NC , 0 = drive to VOL
PD pin . . . buffered. When /PDE is low, PD information can be read
ID pin . . . non-buffered

3.61

3.03

PIN CONFIGURATION

1pin

10pin

11pin

40pin

41pin

84pin

85pin

94pin

95pin

124pin

125pin

168pin

FRONT SIDE

BACK SIDE

MH8V7245BAZTJ-6

MITSUBISHI LSIs

MH8V7245BAZTJ -5, -6

Preliminary Spec.

MITSUBISHI
ELECTRIC

9/Nov. /1998

HYPER PAGE MODE 603979776 - BIT ( 8388608 - WORD BY 72 - BIT ) DYNAMIC RAM

MIT-DS-0284-0.0

( / 23 )

Specifications subject to
change without notice.

PIN CONFIGURATION

Reserved: Reserved use
RFU: Reserved for future use

Pin No.

Pin Name

Pin No.

Pin Name

Pin No.

Pin Name

Pin No.

Pin Name

100

101

102

103

104

105

106

107

108

109

110

111

112

113

114

115

116

117

118

119

120

121

122

123

124

125

126

127

128

129

130

131

132

133

134

136

137

138

139

140

141

142

143

144

145

146

147

148

149

150

151

152

153

154

155

156

157

158

159

160

161

162

163

164

165

166

167

168

135

Reserved

Vss

DQ36

DQ37

DQ38

DQ39

Vcc

DQ40

DQ41

DQ42

DQ43

DQ44

Vss

DQ45

DQ46

DQ47

DQ48

DQ49

Vcc

DQ50

DQ51

DQ52

DQ53

Vss

Reserved

Vcc

RFU

Vss

Vcc

RFU

Reserved

Vss

DQ0

DQ1

DQ2

DQ3

Vcc

DQ4

DQ5

DQ6

DQ7

DQ8

Vss

DQ9

DQ10

DQ11

DQ12

DQ13

Vcc

DQ14

DQ15

DQ16

DQ17

Vss

Reserved

Vcc

/WE0

/CAS0

/RAS0

/OE0

Vss

Reserved

Vcc

RFU

DQ26

Vss

/OE2

/RAS2

/CAS4

Reserved

/WE2

Vcc

Reserved

DQ18

DQ19

Vss

DQ20

DQ21

DQ22

DQ23

Vcc

DQ24

RFU

DQ25

DQ27

DQ30

Vss

DQ28

DQ29

DQ31

Vcc

DQ32

Vss

PD1

PD3

PD5

PD7

ID0

Vcc

DQ34

DQ33

DQ35

DQ62

Vss

RFU

Reserved

/PDE

Vcc

Reserved

DQ54

DQ55

Vss

DQ56

DQ57

DQ58

DQ59

Vcc

DQ60

RFU

DQ61

DQ63

DQ66

Vss

DQ64

DQ65

DQ67

Vcc

DQ68

Vss

PD2

PD4

PD6

PD8

ID1

Vcc

DQ70

DQ69

DQ71

A10

A11

Reserved

MITSUBISHI LSIs

MH8V7245BAZTJ -5, -6

Preliminary Spec.

MITSUBISHI
ELECTRIC

9/Nov. /1998

HYPER PAGE MODE 603979776 - BIT ( 8388608 - WORD BY 72 - BIT ) DYNAMIC RAM

MIT-DS-0284-0.0

( / 23 )

Specifications subject to
change without notice.

BLOCK DIAGRAM

A1~A11

D0~D4

D5~D8

D0~D8

. . .

Vcc

Vss

D0~D8
& INPUT BUFFER

ROW ADDRESS STROBE INPUT
COLUMN ADDRESS STROBE INPUT
WRITE CONTROL INPUT
OUTPUT ENABLE INPUT

DATA I/O

ADDRESS INPUT

POWER SUPPLY
GROUND

/RAS

/CAS
/WE

/OE

A, B

DQ
Vcc
Vss

PIN NAME

FUNCTION

DQ32
DQ33
DQ34
DQ35

DQ28
DQ29
DQ30
DQ31

DQ24
DQ25
DQ26
DQ27

DQ20
DQ21
DQ22
DQ23

DQ16
DQ17
DQ18
DQ19

DQ12
DQ13
DQ14
DQ15

DQ8
DQ9
DQ10
DQ11

DQ4
DQ5
DQ6
DQ7

DQ0
DQ1
DQ2
DQ3

/RAS0

/CAS0

/WE0

/OE0

/RAS

/CAS

/OE

DQ1
~DQ8

DQ68
DQ69
DQ70
DQ71

DQ64
DQ65
DQ66
DQ67

DQ60
DQ61
DQ62
DQ63

DQ56
DQ57
DQ58
DQ59

DQ52
DQ53
DQ54
DQ55

DQ48
DQ49
DQ50
DQ51

DQ44
DQ45
DQ46
DQ47

DQ40
DQ41
DQ42
DQ43

DQ36
DQ37
DQ38
DQ39

/RAS2

/CAS4

/WE2

/OE2

D : M5M465805BTP

/RAS

/CAS

/OE

DQ1
~DQ8

/RAS

/CAS

/OE

DQ1
~DQ8

/RAS

/CAS

/OE

DQ1
~DQ8

/RAS

/CAS

/OE

DQ1
~DQ8

/RAS

/CAS

/OE

DQ1
~DQ8

/RAS

/CAS

/OE

DQ1
~DQ8

/RAS

/CAS

/OE

DQ1
~DQ8

/RAS

/CAS

/OE

DQ1
~DQ8

MITSUBISHI LSIs

MH8V7245BAZTJ -5, -6

Preliminary Spec.

MITSUBISHI
ELECTRIC

9/Nov. /1998

HYPER PAGE MODE 603979776 - BIT ( 8388608 - WORD BY 72 - BIT ) DYNAMIC RAM

MIT-DS-0284-0.0

( / 23 )

Specifications subject to
change without notice.

FUNCTION

The MH8V7245BAZTJ provide, in addition to normal read,
write, and read-modify-write operations,

a number of other functions, e.g., Hyper page mode, /CAS
before /RAS refresh, and delayed-write. The input conditions
for each are shown in Table 1.

Table 1 Input conditions for each mode

Operation

/RAS

/CAS

Inputs

Input/Output

Refresh

Remark

Row

address

Column

Output

Read

Write (Early write)

Write (Delayed write)

Read-modify-write

/CAS before /RAS refresh

ACT

NAC

ACT

DNC

NAC

APD

DNC

OPN

VLD

IVD

VLD

OPN

YES

Hyper page mode
identical

Note : ACT : active, NAC : nonactive, DNC : don' t care, VLD : valid, IVD : Invalid, APD : applied, OPN : open

/OE

ACT

DNC

ACT

DNC

APD

DNC

Input

VLD

OPN

DNC

OPN

Standby

NAC

DNC

OPN

DNC

Hidden refresh

MITSUBISHI LSIs

MH8V7245BAZTJ -5, -6

Preliminary Spec.

MITSUBISHI
ELECTRIC

9/Nov. /1998

HYPER PAGE MODE 603979776 - BIT ( 8388608 - WORD BY 72 - BIT ) DYNAMIC RAM

MIT-DS-0284-0.0

( / 23 )

Specifications subject to
change without notice.

(Ta = 0~70°C, Vcc = 3.3V±0.3V, Vss = 0V, unless otherwise noted)

(Ta=0~70°C, Vcc=3.3V±0.3V, Vss=0V, unless otherwise noted) (Note 2)

ABSOLUTE MAXIMUM RATINGS

Symbol

Vcc

Topr
Tstg

Parameter

Conditions

Ratings

-0.5~ 4.6

10.7

0~70

-40~100

With respect to Vss

Ta=25°C

Supply voltage

Output current

Power dissipation

Operating temperature
Storage temperature

RECOMMENDED OPERATING CONDITIONS

Unit

Limits

Min

Nom

Max

V
V

3.6

Vcc+0.3

0.8

3.3

3.0

2.0

-0.3

Parameter

Supply voltage

Supply voltage
High-level input voltage, all inputs
Low-level input voltage

Vcc

Symbol

Vss

VIH

VIL

(Ta=0~70°C, unless otherwise noted) (Note 1)

ELECTRICAL CHARACTERISTICS

CAPACITANCE

Symbol

VOH

VOL

IOZ

I I

ICC1 (AV)

ICC2

ICC4(AV)

ICC6(AV)

High-level output voltage

Parameter

Limits

Min

Max

Unit

Typ

Test conditions

Low-level output voltage

Off-state output current
Input current (except /RAS)

Average supply
current
from Vcc operating

(Note 3,4,5)

(Note 3,5)

Supply current from Vcc , stand-by

Average supply current
from Vcc
Hyper-Page-Mode

Average supply current from
Vcc
/CAS before /RAS refresh
mode

IOH=-2.0mA

IOL=2.0mA
Q floating 0V

VOUT

Vcc

VIN

Vcc+0.3, Other input pins=0V

/RAS, /CAS cycling
tRC=tWC=min.
output open

/RAS=/CAS =VIH, output open

/RAS=/CAS=WE

Vcc -0.2, output open

/RAS=VIL,/CAS cycling
tPC=min.
output open

/CAS before /RAS refresh cycling
tRC=min.
output open

Note 2: Current flowing into an IC is positive, out is negative.
3: Icc1 (AV), Icc4 (AV) and Icc6 (AV) are dependent on cycle rate. Maximum current is measured at the fastest cycle rate.
4: Icc1 (AV) and Icc4 (AV) are dependent on output loading. Specified values are obtained with the output open.
5: Column address can be changed once or less while /RAS=VIL and /CAS=VIH

I I (RAS)

Input current (/RAS)

VIN

Vcc+0.3, Other input pins=0V

2.4

-10

-10
-90

Vcc

0.4

Limits

Min

Max

Unit

Typ

CI (/RAS)

C(DQ)

Symbol

Parameter

Test conditions

Input capacitance, /RAS input

Input/Output capacitance,DATA

VI=Vss
f=1MHZ
Vi=25mVrms

Input capacitance, except /RAS input

Unit

°C
°C

- 5

- 6

1190

1100

830

1100

24.5

Note 1 : All voltage values are with respect to Vss

- 6

- 5

920

- 5

1190

MITSUBISHI LSIs

MH8V7245BAZTJ -5, -6

Preliminary Spec.

MITSUBISHI
ELECTRIC

9/Nov. /1998

HYPER PAGE MODE 603979776 - BIT ( 8388608 - WORD BY 72 - BIT ) DYNAMIC RAM

MIT-DS-0284-0.0

( / 23 )

Specifications subject to
change without notice.

(Ta=0~70°C, Vcc=3.3V±0.3V, Vss=0V, unless otherwise noted , see notes 6,14,15)

SWITCHING CHARACTERISTICS

Note 6: An initial pause of 500us is required after power-up followed by a minimum of eight initialization cycles (any combination of cycles
containing /CAS before /RAS refresh).
Note the /RAS may be cycled during the initial pause . And any 8 /RAS or /RAS /CAS cycles are required after prolonged periods
(greater than 64 ms) of /RAS inactivity before proper device operation is achieved.
7: Measured with a load circuit equivalent to 1 TTL load and 100pF,VOH=2.4V(IOH=-2mA) and VOL=0.4V(IOL=-2mA).
The reference levels for measuring of output signals are 2.0V(VOH)and 0.8V(VOL).
8: Assumes that tRCD

tRCD(max), tASC

tASC(max) and tCP

tCP(max).

9: Assumes that tRCD

tRCD(max) and tRAD

tRAD(max). If tRCD or tRAD is greater than the maximum recommended value shown in this table,

tRAC will increase by amount that tRCD exceeds the value shown.
10: Assumes that tRAD

tRAD(max) and tASC

tASC(max).

11: Assumes that tCP

tCP(max) and tASC

tASC(max).

12: tOEZ (max), tWEZ(max), tOFF(max) and tREZ(max) defines the time at which the output achieves the high impedance state (IOUT

I ± 10uA I )

and is not reference to VOH(min) or VOL(max).
13: Output is disabled after both /RAS and /CAS go to high.

Limits

Parameter

Symbol

Unit

- 5

Min

Max

- 6

Min

Max

tCAC

tRAC
tAA

tCPA

tOEA

tOHR

tCLZ

Access time from /CAS

Access time from /RAS
Column address access time

Access time from /CAS precharge

Output hold time from /RAS

Output low impedance time /CAS low

Access time from /OE

(Note 7,8)

(Note 7,9)

(Note 7,10)

(Note 7,11)

(Note 7)

(Note 13)

(Note 7)

ns
ns

(Ta=0~70°C, Vcc=3.3V±0.3V, Vss=0V, unless otherwise noted ,see notes 14,15)

Limits

Min

Max

Parameter

Symbol

Unit

(Note16)

(Note17)

(Note18)

TIMING REQUIREMENTS (For Read, Write, Read-Modify-Write ,Refresh, and Hyper-Page Mode Cycles)

Note 14: The timing requirements are assumed tT =2ns.
15: VIH(min) and VIL(max) are reference levels for measuring timing of input signals.
16: tRCD(max) is specified as a reference point only. If tRCD is less than tRCD(max), access time is tRAC. If tRCD is greater than tRCD(max), access
time is controlled exclusively by tCAC or tAA. .
17: tRAD(max) is specified as a reference point only. If tRAD

tRAD(max) and tASC

tASC(max), access time is controlled exclusively by tAA.

18: tASC(max) is specified as a reference point only. If tRCD

tRCD(max) and tASC

tASC(max), access time is controlled exclusively by tCAC.

19: Either tDZC or tDZO must be satisfied.
20: Either tRDD or tCDD or tODD must be satisfied.
21: tT is measured between VIH(min) and VIL(max).

(Note19)

(Note20)

(Note19)

(Note20)

-5

Min

Max

-6

tREF

tRP
tRCD

tCRP

tRPC
tCPN

tRAD

tASR
tASC

tRAH

tCAH
tDZC

tDZO

tCDD
tODD

Refresh cycle time

/RAS high pulse width
Delay time, /RAS low to /CAS low

Delay time, /CAS high to /RAS low

Delay time, /RAS high to /CAS low
/CAS high pulse width

Column address delay time from /RAS low

Row address setup time before /RAS low
Column address setup time before /CAS low

Row address hold time after /RAS low

Column address hold time after /CAS low
Delay time, data to /CAS low

Delay time, data to /OE low

Delay time, /CAS high to data

Delay time, /OE high to data

-5

8
5

3
8

-5

ns
ns

tOHC

Output hold time from /CAS

tOEZ

tOFF

tREZ

Output disable time after /CAS high

Output disable time after /RAS high

Output disable time after /OE high

(Note 12)

(Note 12,13)

tWEZ

Output disable time after /WE high

(Note 12)

(Note21)

Transition time

(Note20)

tRDD

Delay time, /RAS high to data

MITSUBISHI LSIs

MH8V7245BAZTJ -5, -6

Preliminary Spec.

MITSUBISHI
ELECTRIC

9/Nov. /1998

HYPER PAGE MODE 603979776 - BIT ( 8388608 - WORD BY 72 - BIT ) DYNAMIC RAM

MIT-DS-0284-0.0

( / 23 )

Specifications subject to
change without notice.

Read and Refresh Cycles

Limits

Parameter

Symbol

Unit

-5

(Note 22)

Write Cycle (Early Write and Delayed Write)

(Note 22)

10000

-5

Min

Max

Limits

Parameter

Symbol

Unit

(Note 24)

10000

ns
ns

-5

tWC

tRAS

tCAS
tCSH

tRSH

tWCS

tWCH
tCWL

tRWL

tWP
tDS

tDH

Write cycle time

/RAS low pulse width

/CAS low pulse width
/CAS hold time after /RAS low

Write setup time before /CAS low

Write hold time after /CAS low

/RAS hold time after /CAS low

/CAS hold time after /W low

/RAS hold time after /W low

Data setup time before /CAS low or /W low

Data hold time after /CAS low or /W low

Write pulse width

-5

Min

Max

Note 22: Either tRCH or tRRH must be satisfied for a read cycle.

-6

10000

Min

Max

10000

104

10
35

-5

-6

Min

Max

tRC
tRAS

tCAS

tCSH
tRSH

tRCS

tRCH

tRRH
tRAL

tORH

Read cycle time
/RAS low pulse width

/CAS low pulse width

/CAS hold time after /RAS low

Read Setup time after /CAS high

Read hold time after /CAS low

/RAS hold time after /CAS low

Read hold time after /RAS low
Column address to /RAS hold time

/RAS hold time after /OE low

ns
ns

104

35
20

-5

Read-Write and Read-Modify-Write Cycles

Limits

Parameter

Symbol

Unit

Min

Max

-5

(Note23)

(Note24)

Read write/read modify write cycle time

/RAS low pulse width

/CAS low pulse width
/CAS hold time after /RAS low

/RAS hold time after /CAS low
Read setup time before /CAS low

Delay time, /CAS low to /W low

Delay time, /RAS low to /W low

/OE hold time after /W low

tRWC

tRAS
tCAS

tCSH

tRSH
tRCS

tCWD

tRWD
tAWD

tOEH

ns
ns

(Note24)

10000

109

60
40

Note 23: tRWC is specified as tRWC(min)=tRAC(max)+tODD(min)+tRWL(min)+tRP(min)+4tT.
24:tWCS, tCWD,tRWD ,tAWD and,tCPWD are specified as reference points only. If tWCS

tWCS(min) the cycle is an early write cycle and the DQ pins will remain

high impedance throughout the entire cycle. If tCWD

tCWD(min), tRWD

tRWD (min), tAWD

tAWD(min) and tCPWD

tCPWD(min) (for Hyper page mode cycle only),

the cycle is a read-modify-write cycle and the DQ will contain the data read from the selected address. If neither of the above condition (delayed write) of the DQ (at access
time and until /CAS or /OE goes back to VIH) is indeterminate.

Min

Max

-6

10000

133

Delay time, address to /W low

tOCH

/CAS hold time after /OE low

tCAL

Column address to /CAS hold time

MITSUBISHI LSIs

MH8V7245BAZTJ -5, -6

Preliminary Spec.

MITSUBISHI
ELECTRIC

9/Nov. /1998

HYPER PAGE MODE 603979776 - BIT ( 8388608 - WORD BY 72 - BIT ) DYNAMIC RAM

MIT-DS-0284-0.0

( / 23 )

Specifications subject to
change without notice.

Hyper Page Mode Cycle (Read, Early Write, Read -Write, Read-Modify-Write Cycle,
Read Write Mix Cycle,Hi-Z control by /OE or /W) (Note 25)

Note 25: All previously specified timing requirements and switching characteristics are applicable to their respective Hyper page mode cycle.
26: tRAS(min) is specified as two cycles of /CAS input are performed.
27: tCP(max) is specified as a reference point only. If tCP

tCP(max),access time is controlled exclusively by tCAC.

Limits

Parameter

Symbol

Min

Max

(Note26)

(Note27)

100000

/CAS before /RAS Refresh Cycle (Note 28)

Limits

Parameter

Symbol

Unit

Min

Max

Note 28: Eight or more /CAS before /RAS cycles instead of eight /RAS cycles are necessary for proper operation of /CAS before /RAS refresh
mode.

-5

Min

Max

100000

-6

Min

Max

-6

Unit

ns
ns

tHPC
tHPRWC

tRAS

tCP

tCPRH
tCPWD

Hyper page mode read/write cycle time

/RAS low pulse width for read write cycle

/CAS high pulse width

/RAS hold time after /CAS precharge
Delay time, /CAS precharge to W low

Hyper page mode read write/read modify write cycle time

(Note24)

tCSR

tCHR

tRSR

tRHR

/CAS setup time before /RAS low

/CAS hold time after /RAS low

Read setup time before /RAS low
Read hold time after /RAS low

tDOH

Output hold time from /CAS low

ns
ns

tCHOL

tOEPE
tWPE

Hold time to maintain the data Hi-Z until /CAS access

/OE Pulse width (Hi-Z control)
/W Pulse width (Hi-Z control)

ns
ns

tHCWD

tHAWD
tHPWD

Delay time, /CAS low to /W low after read

Delay time, Address to /W low after read
Delay time, /CAS precharge to /W low after read

ns
ns

tHCOD

tHAOD
tHPOD

Delay time, /CAS low to /OE high after read

Delay time, Address to /OE high after read
Delay time, /CAS precharge to /OE high after read

MITSUBISHI LSIs

MH8V7245BAZTJ -5, -6

Preliminary Spec.

MITSUBISHI
ELECTRIC

9/Nov. /1998

HYPER PAGE MODE 603979776 - BIT ( 8388608 - WORD BY 72 - BIT ) DYNAMIC RAM

MIT-DS-0284-0.0

( / 23 )

Specifications subject to
change without notice.

Timing Diagrams

(Note 29)

Read Cycle

DQ
(INPUTS)

/RAS

DQ
(OUTPUTS)

/OE

/CAS

CRP

ASR

RAH

RAD

RCD

CSH

ASC

CAH

RCS

RAS

RSH

CAS

RAL

CAC

CLZ

RAC

RCH

RRH

ASR

CRP

Hi-Z

ROW

ADDRESS

Note 29

Indicates the don't care input.
V

IH(min)

IH(max)

or V

IL(min)

IL(max)

Indicates the invalid output.

ADDRESS

COLUMN

ADDRESS

DZC

Hi-Z

OEZ

ODD

OEA

OCH

DZO

ORH

REZ

OFF

CAL

OHR

OHC

CDD

WEZ

DATA VALID

RDD

A0~A11,B0

MITSUBISHI LSIs

MH8V7245BAZTJ -5, -6

Preliminary Spec.

MITSUBISHI
ELECTRIC

9/Nov. /1998

HYPER PAGE MODE 603979776 - BIT ( 8388608 - WORD BY 72 - BIT ) DYNAMIC RAM

MIT-DS-0284-0.0

( / 23 )

Specifications subject to
change without notice.

Read-Write, Read-Modify-Write Cycle

CRP

ASR

RAH

RCD

CSH

ASC

CAH

RCS

RAS

RWC

RSH

CAS

ASR

CRP

Hi-Z

ROW

COLUMN

ROW

ADDRESS

DATA VALID

ADDRESS

CLZ

CWL

RWL

Hi-Z

DZC

OEZ

DZO

ODD

OEH

AWD

CWD

RWD

DATA

VALID

CAC

RAC

OEA

RAD

/RAS

/OE

/ CAS

DQ
(INPUTS)

DQ
(OUTPUTS)

A0~A11,B0

MITSUBISHI LSIs

MH8V7245BAZTJ -5, -6

Preliminary Spec.

MITSUBISHI
ELECTRIC

9/Nov. /1998

HYPER PAGE MODE 603979776 - BIT ( 8388608 - WORD BY 72 - BIT ) DYNAMIC RAM

MIT-DS-0284-0.0

( / 23 )

Specifications subject to
change without notice.

Hyper Page Mode Read Cycle

CRP

ASR

RAH

RAD

RCD

CAH

RAS

CAC

RAC

ASR

Hi-Z

ADDRESS

COLUMN-1

ROW

ADDRESS

CAS

ROW

ASC

RCS

Hi-Z

DZC

DZO

OEA

OCH

DATA

VALID-1

CSH

HPC

CAS

RSH

COLUMN-2

COLUMN-3

CAH

ASC

CAH

ASC

CPRH

RCH

RRH

CDD

CPA

OEZ

ODD

REZ

OFF

CLZ

DOH

RDD

CAC

DATA

VALID-2

CPA

DOH

CAC

DATA

VALID-3

CAL

OHC

OHR

WEZ

/RAS

/OE

/ CAS

DQ
(INPUTS)

DQ
(OUTPUTS)

A0~A11,B0

MITSUBISHI LSIs

MH8V7245BAZTJ -5, -6

Preliminary Spec.

MITSUBISHI
ELECTRIC

9/Nov. /1998

HYPER PAGE MODE 603979776 - BIT ( 8388608 - WORD BY 72 - BIT ) DYNAMIC RAM

MIT-DS-0284-0.0

( / 23 )

Specifications subject to
change without notice.

Hyper Page Mode Early Write Cycle

CRP

ASR

RAH

RCD

CAH

RAS

ASR

ADDRESS

COLUMN-1

ROW

ADDRESS

CAS

ROW

ASC

WCS

CSH

HPC

CAS

RSH

COLUMN-2

COLUMN-3

CAH

ASC

Hi-Z

WCH

WCS

WCH

WCS

WCH

DATA

VALID-1

DATA

VALID-2

DATA

VALID-3

CAL

CRP

/RAS

/OE

/ CAS

DQ
(INPUTS)

DQ
(OUTPUTS)

A0~A11,B0

MITSUBISHI LSIs

MH8V7245BAZTJ -5, -6

Preliminary Spec.

MITSUBISHI
ELECTRIC

9/Nov. /1998

HYPER PAGE MODE 603979776 - BIT ( 8388608 - WORD BY 72 - BIT ) DYNAMIC RAM

MIT-DS-0284-0.0

( / 23 )

Specifications subject to
change without notice.

DZO

Hyper Page Mode Read-Write,Read-Modify-Write Cycle

CRP

ASR

RAH

RCD

CAH

RAS

ASR

Hi-Z

CAS

ASC

CSH

HPRWC

CAS

RWL

ADDRESS

COLUMN-1

ROW

ADDRESS

ROW

CAH

ASC

RCS

RWD

DZC

COLUMN-2

CWL

RCS

CWL

Hi-Z

DZC

CPWD

DATA

VALID-2

Hi-Z

CLZ

DZO

OEZ

ODD

OEZ

OEH

RAD

CWD

AWD

CWD

CAC

DATA

VALID-1

CAC

DATA

VALID-2

CLZ

RAC

OEA

CPA

OEA

ODD

DATA

VALID-1

CRP

/RAS

/OE

/ CAS

DQ
(INPUTS)

DQ
(OUTPUTS)

A0~A11,B0

MITSUBISHI LSIs

MH8V7245BAZTJ -5, -6

Preliminary Spec.

MITSUBISHI
ELECTRIC

9/Nov. /1998

HYPER PAGE MODE 603979776 - BIT ( 8388608 - WORD BY 72 - BIT ) DYNAMIC RAM

MIT-DS-0284-0.0

( / 23 )

Specifications subject to
change without notice.

DZO

WCH

Hyper Page Mode Mix Cycle (1)

CRP

ASR

RAH

RAD

RCD

CAH

RAS

CAC

RAC

Hi-Z

ADDRESS

COLUMN-1

ROW

ADDRESS

CAS

ROW

ASC

RCS

DZC

DZO

OEA

OCH

DATA

VALID-1

CSH

DATA

VALID-2

HPC

CAS

COLUMN-2

COLUMN-3

CAH

ASC

CAH

ASC

HPRWC

CPWD

WCS

CLZ

CPA

DATA

VALID-3

CAL

CWD

OEZ

ODD

WEZ

OEH

OEZ

CLZ

OEA

ASR

CRP

CAC

ODD

DATA

VALID-3

RWL

CWL

AWD

/RAS

/OE

/ CAS

DQ
(INPUTS)

DQ
(OUTPUTS)

A0~A11,B0

MITSUBISHI LSIs

MH8V7245BAZTJ -5, -6

Preliminary Spec.

MITSUBISHI
ELECTRIC

9/Nov. /1998

HYPER PAGE MODE 603979776 - BIT ( 8388608 - WORD BY 72 - BIT ) DYNAMIC RAM

MIT-DS-0284-0.0

( / 23 )

Specifications subject to
change without notice.

CPA

DATA

VALID-1

CAH

ASC

HPC

DATA

VALID-3

CAC

OEZ

ODD

DATA

VALID-2

Hi-Z

DZC

Hi-Z

COLUMN-1

CAH

ASC

CAH

ASC

COLUMN-2

COLUMN-3

WCH

CAC

OEA

CLZ

Hi-Z

CPA

CAL

CAS

RCH

WCS

WEZ

CAL

Hyper Page Mode Mix Cycle (2)

DZC

CAS

HCOD

HAOD

HPOD

HCWD

HAWD

HPWD

/RAS

/OE

/ CAS

DQ
(INPUTS)

DQ
(OUTPUTS)

A0~A11,B0

MITSUBISHI LSIs

MH8V7245BAZTJ -5, -6

Preliminary Spec.

MITSUBISHI
ELECTRIC

9/Nov. /1998

HYPER PAGE MODE 603979776 - BIT ( 8388608 - WORD BY 72 - BIT ) DYNAMIC RAM

MIT-DS-0284-0.0

( / 23 )

Specifications subject to
change without notice.

Hyper Page Mode Read Cycle ( Hi-Z control by OE )

CRP

ASR

RAH

RAD

RCD

CAH

RAS

CAC

RAC

ASR

Hi-Z

ADDRESS

COLUMN-1

ROW

ADDRESS

CAS

ROW

ASC

RCS

Hi-Z

DZC

DZO

OEA

DATA

VALID-1

CSH

HPC

CAS

RSH

COLUMN-2

COLUMN-3

CAH

ASC

CAH

ASC

CPRH

RAL

RCH

RRH

CDD

CPA

OEZ

ODD

REZ

OFF

CLZ

DOH

RDD

CAC

DATA

VALID-2

CPA

OEZ

CAC

DATA

VALID-3

CLZ

Hi-Z

OEPE

CHOL

OEPE

OEZ

OEA

OCH

DATA

VALID-1

OHR

OHC

CRP

WEZ

/RAS

/OE

/ CAS

DQ
(INPUTS)

DQ
(OUTPUTS)

A0~A11,B0

MITSUBISHI LSIs

MH8V7245BAZTJ -5, -6

Preliminary Spec.

MITSUBISHI
ELECTRIC

9/Nov. /1998

HYPER PAGE MODE 603979776 - BIT ( 8388608 - WORD BY 72 - BIT ) DYNAMIC RAM

MIT-DS-0284-0.0

( / 23 )

Specifications subject to
change without notice.

Hyper Page Mode Read Cycle ( Hi-Z control by W )

CRP

ASR

RAH

RAD

RCD

CAH

RAS

CAC

RAC

ASR

Hi-Z

ADDRESS

COLUMN-1

ROW

ADDRESS

CAS

ROW

ASC

RCS

Hi-Z

DZC

DZO

OEA

OCH

DATA

VALID-1

CSH

HPC

CAS

RSH

COLUMN-2

COLUMN-3

CAH

ASC

CAH

ASC

CPRH

RAL

RCH

CDD

CPA

OEZ

ODD

REZ

OFF

CLZ

DOH

RDD

CAC

DATA

VALID-2

CPA

WEZ

CAC

DATA

VALID-3

WPE

RCH

RCS

CLZ

Hi-Z

OHR

OHC

RRH

CRP

/RAS

/OE

/ CAS

DQ
(INPUTS)

DQ
(OUTPUTS)

A0~A11,B0

MITSUBISHI LSIs

MH8V7245BAZTJ -5, -6

Preliminary Spec.

MITSUBISHI
ELECTRIC

9/Nov. /1998

HYPER PAGE MODE 603979776 - BIT ( 8388608 - WORD BY 72 - BIT ) DYNAMIC RAM

MIT-DS-0284-0.0

( / 23 )

Specifications subject to
change without notice.

Hidden Refresh Cycle (Read)

(Note 31)

Note 31: Early write, delayed write, read write or read modify write cycle is applicable instead of read cycle.
Timing requirements and output state are the same as that of each cycle shown above.

CRP

ASR

RAH

RAD

RCD

CAH

RCS

RAS

CHR

CAC

CLZ

RAC

RRH

ASR

Hi-Z

ADDRESS

COLUMN

ROW

ADDRESS

DATA VALID

RAS

RSH

ROW

ASC

ADDRESS

RAL

Hi-Z

DZC

Hi-Z

DZO

OEA

ORH

ODD

OEZ

REZ

CDD

RCH

RDD

OHR

OHC

OFF

/RAS

/OE

/ CAS

DQ
(INPUTS)

DQ
(OUTPUTS)

A0~A11,B0

MITSUBISHI LSIs

MH8V7245BAZTJ -5, -6

Preliminary Spec.

MITSUBISHI
ELECTRIC

9/Nov. /1998

HYPER PAGE MODE 603979776 - BIT ( 8388608 - WORD BY 72 - BIT ) DYNAMIC RAM

MIT-DS-0284-0.0

( / 23 )

Specifications subject to
change without notice.

Keep safety first in your circuit designs!

Mitsubishi Electric Corporation puts the maximum effort into making
semiconductor products better and more reliable,but there is always the
possibility that trouble may occur with them. Trouble with semiconductors
consideration to safety when making your circuit designs,with appropriate
measures such as (i) placement of substitutive,auxiliary circuits,(ii) use of
non-flammable material or (iii) prevention against any malfunction or mishap.

Notes regarding these materials

1.These materials are intended as a reference to assist our customers in the
selection of the Mitsubishi semiconductor product best suited to the
customer's application;they do not convey any license under any
intellectual property rights,or any other rights,belonging to Mitsubishi
Electric Corporation or a third party.

2.Mitsubishi Electric Corporation assumes no responsibility for any damage,
or infringement of any third-party's rights,originating in the use of any
product data,diagrams,charts or circuit application examples contained in
these materials.

3.All information contained in these materials,including product data,
diagrams and charts,represent information on products at the time of
publication of these materials,and are subject to change by Mitsubishi
Electric Corporation without notice due to product improvements or other
reasons. It is therefore recommended that customers contact Mitsubishi
Electric Corporation or an authorized Mitsubishi Semiconductor product
distributor for the latest product information before purchasing a product
listed herein.

4.Mitsubishi Electric Corporation semiconductors are not designed or
manufactured for use in a device or system that is used under
circumstances in which human life is potentially at stake. Please contact
Mitsubishi Electric Corporation or an authorized Mitsubishi Semiconductor
product distributor when considering the use of a product contained herein
for special applications,such as apparatus or systems for transportation,
vehicular,medical,aerospace,nuclear,or undersea repeater use.

5.The prior written approval of Mitsubishi Electric Corporation is necessary to
reprint or reproduce in whole or in part these materials.

6.If these products or technologies are subject the Japanese export
control restrictions,they must be exported under a license from the
Japanese government and cannot be imported into a country other than
the approved destination.
Any diversion or reexport contrary to the export control laws and
regulations of Japan and/or the country of destination is prohibited.

7.Please contact Mitsubishi Electric Corporation or an authorized Mitsubishi
Semiconductor product distributor for further details on these materials or
the products contained therein.

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