8-1

MS622424

MOSEL VITELIC

MS622424 Rev. 1.0 January 1995

MS622424
HIGH PERFORMANCE
8K x 24 BIT
CMOS COLOR MAP

Features

Color Index Mode supports up to 8192 simulta-
neous colors out of 16.7 million total colors

24-bit RGB Mode allows full true color display

High-speed operation capable of supporting
resolutions up 1280 x 1024

Available in 100-pin PQFP and MQUAD
packages

Unique "Write-Buffer" at MPU port permits
dualport-like operation using an economical
singleport memory core

All TTL compatible inputs and outputs

60, 70 and 80 MHz pipelined operation

Standard MPU Interface

Description

The MS622424 is a high performance, full

CMOS, 8K x 24, 192K-bit pipelined static memory.
This device is specifically designed for use as a
color look-up table in high resolution video display
systems. When two of these devices are operated
in parallel, the resulting system will be capable of
supporting a display of 1280 x 1024 bit mapped
color graphics with 13 bits per pixel in the Color
Index Mode or 24 bits per pixel in the RGB Mode.

In the Color Index Mode, three internal 8Kx8's

provide 8192 simultaneous colors from a 16.7
million color palette. The palette can be partitioned
into several smaller palettes thereby supporting
multiple window display. In the RGB Mode, the 24-
bit input can be gamma corrected on one of three
gamma correction tables. The 24-bit gamma
corrected value will then be presented at the output.

This device is implemented in full CMOS for low

power consumption, and is available in an 100-pin
plastic or metal quad-flat-pack.

Functional Block Diagram

INPUT

LATCH

PIXIN(0-23)

PIX.RGB(0-1)

CEB1

CEB2

R/WB

CONFIGSEL(0-2)

CONFIGBUS(0-7)

CBLANKB

RSB

BD.REV(0-3)

MPU

CONTROL

2:1 MUX

PIXIN(0-12)

PIXIN(0-7)

PIXIN(0-12)

PIXIN(8-15)

PIXIN(0-12)

PIXIN(16-23)

PIX.RGB(MUX CONTROL)

3:1 MUX

ADDR 13

64X37

WRITE

FIFO

RGB 24

FIFO ADDR 13

FIFO RGB 24

8Kx8

OUTPUT

LATCH

POUT(0-23)

AFB

FFB

PIPE.OUT(0-3)

PIPELINE SYNCHRONIZATION PATH

CLOCK.IN

PIPE.IN(0-3)

8-2

MS622424

MOSEL VITELIC

MS622424 Rev. 1.0 January 1995

MPU Access Modes

CONFIGSEL<2:0>

MODE

000

Address Register low (R/W)

001

Address Register high (R/W)

010

Color Palette Buffer (R/W)

011

Command Register (R/W)

100

Status Register (read only)

101

Color Buffer Register
(read only)

110

Revision register (read only)

111

Color Palette read initialization
(R/W)

Functional Description

MPU Interface

The MPU interface allows the MPU to access the

internal registers and the color map. The
CONFIGSEL0瑿ONFIGSEL2 bits that are latched
on the falling edge of CEB define the access mode.
The access modes are defined in the table below.
The R/WB pin is also latched on the falling edge of
CEB and indicates a read operation when high and
a write operation when low. These functions are
illustrated in the truth table on the next page.

The RGB0 and RGB1 bits are the two bits of a

modulo 3 counter, which determine which color
(red, green, or blue, in that order) is selected. These
two bits are reset by a write to either the high or low
Address Register. In writes and reads to and from
the color palette, the Address Register is
incremented at the end of the RGB cycle.

In order to perform color pallette read without

asynchronous problems, initialization is required.
This is done by writing a command of
configsel(2:0)=111 before the actual read starts.
Upon finishing the color palette read operation, a
read command of configsel(2:0)=111 should also
be issued to switch MPU Access modes.

During a read from the color palette, the color

data output at POUT0璓OUT23 may be disturbed
because the address register will take over
addressing of the color map. To prevent random
color data from being displayed on the screen, the
data at POUT0璓OUT23 will be held at the value
defined by the last valid pixel address for the
duration of the read. A read of the color palette
should not be performed while the Write FIFO is not
empty because it may contend with the FIFO to
color map write. It is recommended that FIFO empty
flag status always be checked before issuing color
palette read instructions. If such a contention
occurs, then the color palette read will be disturbed
by the write cycle.

Write FIFO

The Write FIFO stores data and addresses that

are written to the Color Palette Buffer and Address
Registers. The FIFO is emptied by writing the data
to the color map during a blanking period as
indicated by CBLANKB. The host can write up to 64
locations that contain a 13-bit address and a 24-bit

color before the FIFO becomes full. When the FIFO
is full the full flag pin (FFB) goes low until at least
one location of the FIFO is transferred to the color
map. If the host attempts to write to the Color
Palette Buffer while the FFB is active, then the
device will transfer 4 locations from the FIFO to the
color map in order to make room for the incoming
data, regardless of the state of CBLANKB. This
process may disturb the data in the pixel stream. To
prevent random color data from being displayed on
the screen while the device performs these 4 writes,
the data at POUT0璓OUT23 will be held at the
value defined by the last valid pixel address. When
Pixel clock is much slower than 70 MHz, the
operating frequency of MPU should also be slowed
down accordingly in order to maintain the
synchronization of FIFO operations

Color Buffer Register

The Color Buffer Register stores the red and

green data that is written to the Color Palette Buffer.
Thus if a complete red, green, blue write cycle is not
completed (register data is not transferred to the
Write FIFO), then the host can recover the red and
green data it has written by reading the red and
green Color Buffer Registers.

The host can recover the red and green data by

first writing to the address register to reset the RGB
counter. Then the red and green data can be
recovered in two consecutive reads of the Color
Buffer Register.

8-3

MS622424

MOSEL VITELIC

MS622424 Rev. 1.0 January 1995

Truth Table

R/WB

CONFIGSEL<2:0>

RGB1

RGB0

FUNCTION

000 0

Write Address Register Low, reset RGB Counter

001 1

Write Address Register High, reset RGB Counter (1)

010 2

Write Red Color Palette Buffer, increment RGB counter

010 2

Write Green Color Palette Buffer, increment RGB counter

010 2

Write Blue Color Data to Write FIFO, transfer register
contents to Write FIFO, reset RGB counter, increment
Address Register

011 3

Write Command Register

100 4

Invalid Operation

101 5

Invalid Operation

110 6

Invalid Operation

111 7

Initialize color palette read

000 0

Read Address Register Low

001 1

Read Address Register High (2)

010 2

Read Red Color Palette, increment RGB counter (3)

010 2

Read Green Color Palette Buffer, increment RGB counter

010 2

Read Blue Color Palette Buffer, reset RGB counter,
increment Address register

011 3

Read Command Register

100 4

Read Status Register

101 5

Read Red Color Buffer Register, increment RGB counter

101 5

Read Green Color Buffer Register

101 5

Invalid Operation

110 6

Read Revision Register

111 7

Terminate color palette read

NOTE:
1. Only CONFIGBUS0瑿ONFIGBUS4 are recognized; the upper three bits are ignored.
2. Data is output to CONFIGBUS0瑿ONFIGBUS4 only. The upper three bits will output "0".
3. Reading the Red Color Palette may disturb the pixel stream.
4. RGB0 and RGB1 are internal RGB couter outputs.

8-4

MS622424

MOSEL VITELIC

MS622424 Rev. 1.0 January 1995

Internal Registers

Command Register

The Command Register is an 8-bit register.

CB5瑿B7

CB4

CB3

CB2

CB1

CB0

PIPE.IN0 reset

This bit is internally ANDed with PIPE.IN0 . Thus when CB0 is "0", then
PIPE.OUT0 will always be "0"

CB1

PIPE.IN1 reset

This bit is internally ANDed with PIPE.IN1 . Thus when CB1 is "0", then
PIPE.OUT1 will always be "0"

CB2

PIPE.IN2 set

This bit is internally ORed with PIPE.IN2 . Thus when CB2 is "1", then
PIPE.OUT2 will always be "1"

CB3

PIPE.IN3 set

This bit is internally ORed with PIPE.IN3 . Thus when CB3 is "1", then
PIPE.OUT3 will always be "1"

CB4

HFB/AFB

This bit programs the AFB flag indicator. When this bit is "0" the AFB pin
will indicate that the FIFO is half full. When this bit is "1" AFB will indicate
almost full.

CB5瑿B7

Reserved

Reserved for internal use.

Status Register

The Status Register is an 8-bit register.

SB5璖B7

SB4

SB3

SB2

SB1

SB0

RGB0

LSB of RGB counter. RGB0 and RGB1 form two bits of a modulo three
counter that determines which color is operated on (read only).

SB1

RGB1

MSB of RGB data counter (read only).

SB2

EFB

Empty Flag; Write FIFO is empty when this bit is low.

SB3

HFB/AFB

Half or Almost-Full Flag; Like the external AFB pin, this bit can be
programmed by CB4 to indicate that the Write FIFO is at least half full or
at least 7/8 full (eight or fewer empty locations left). This pin is active low.

SB4

FFB

Full Flag; Write FIFO is full when this bit is low.

SB5璖B7

Reserved

Reserved for internal use.

Revision Register

The Revision Register is an 8-bit register.

RVB4璕VB7

RVB3

RVB2

RVB1

RVB0

REV0

LSB of Revision Register. This register is mask programmed to indicate
the revision number.

RVB1

REV1

Second bit of Revision Register.

RVB2

REV2

MSB of Revision Register.

RVB3

Reserved

Reserved for internal use.

RVB4璕VB7

REV4�7

Corresponds to board revision input BD.REV0�3

8-5

MS622424

MOSEL VITELIC

MS622424 Rev. 1.0 January 1995

100-pin PQFP/MQUAD

PIN CONFIGURATION

Top View

VSS
VSS

CLOCK.IN

VCC

PIXIN11
PIXIN10

PIXIN9
PIXIN8
PIXIN7
PIXIN6
PIXIN5
PIXIN4
PIXIN3
PIXIN2
PIXIN1
PIXIN0

VSS

RSB

PIXIN22
PIXIN21

PIXIN23

PIXIN20
PIXIN19
PIXIN18

PIXIN17
PIXIN16
PIXIN15
PIXIN14
PIXIN13

CONFIGBUS0

CONFIGBUS1

CONFIGBUS2

CONFIGBUS3

CONFIGBUS4

CONFIGBUS5

CONFIGBUS6

CONFIGBUS7

CEB1

CEB2

R/WB

CONFIGSEL0

CONFIGSEL1

CONFIGSEL2

CBLANKB

FFB

VSS

VCC

POUT16

POUT17

POUT18

POUT20

POUT19

POUT21

POUT22

POUT23

VSS

POUT15
POUT14
POUT13
POUT12

POUT11
POUT10
POUT9
POUT8
VCC
VCC

VCC

POUT7
POUT6
POUT5
POUT4

PIXIN12

AFB

PIPE.IN3

PIPE.IN2

PIPE.IN1

PIPE.IN0

VCC

PIPE.OUT0

PIPE.OUT1

PIPE.OUT2

PIPE.OUT3

VSS

BD.REV1

BD.REV2

BD.REV3

VCC

PIX.RGB1

PIX.RGB0

BD.REV0

VSS/TEST

POUT3
POUT2
POUT1
POUT0

VSS

MS622424

协谢械泻褌褉芯薪薪褘泄 泻芯屑锌芯薪械薪褌: MS622424

协谢械泻褌褉芯薪薪褘泄泻芯屑锌芯薪械薪褌: MS622424