MS7200L/7201AL/7202AL

MOSEL VITELIC

MS7200L/01AL/02AL Rev. 1.0 January 1995

MS7200L/7201AL/7202AL
256 x 9, 512 x 9, 1K x 9
CMOS FIFO

Features

First-In/First-Out static RAM based dual port
memory

Three densities in a x9 configuration

Low power versions

Includes empty, full, and half full status flags

Direct replacement for industry standard
Mostek and IDT

Ultra high-speed 30 MHz FIFOs available with
33 ns cycle times.

Fully expandable in both depth and width

Simultaneous and asynchronous read and write

Auto retransmit capability

TTL compatible interface, single 5V ± 10%
power supply

Available in 28 pin 300 mil and 600 mil plastic
DIP, 32 Pin PLCC and 330 mil SOG

Descriptions

The MS7200L/7201AL/7202AL are dual-port

static RAM based CMOS First-In/First-Out (FIFO)
memories organized in nine-bit wide words. The
devices are configured so that data is read out in
the same sequential order that it was written in.
Additional expansion logic is provided to allow for
unlimited expansion of both word size and depth.

The dual-port RAM array is internally sequenced

by independent Read and Write pointers with no
external addressing needed. Read and write
operations are fully asynchronous and may occur
simultaneously, even with the device operating at
full speed. Status flags are provided for full, empty,
and half-full conditions to eliminate data underflow
and overflow. The x9 architecture provides an
additional bit which may be used as a parity or
control bit. In addition, the devices offer a retransmit
capability which resets the Read pointer and allows
for retransmission from the beginning of the data.

The MS7200L/7201AL/7202AL are available in a

range of frequencies from 10 to 30 MHz (33 - 100 ns
cycle times). A low power version with a 500µA
power down supply current is available. They are
manufactured on Mosel-Vitelic's high performance
1.2µ CMOS process and operate from a single 5V
power supply.

WRITE

CONTROL

WRITE

POINTER

READ

POINTER

READ

CONTROL

RESET

LOGIC

FLAG

LOGIC

EXPANSION

LOGIC

THREE

STATE

BUFFERS

DATA OUTPUTS (Q0-Q8)

DATA INPUTS (Q0-Q8)

FL / RT

RAM

ARRAY

256x9
512x9

1Kx9

Block Diagram

28-PIN PDIP

Pin Configurations

32-PIN PLCC

FL / RT

XO / HF

GND

300 mil
600 mil

DIP

330 mil

SOG

D6
D7
NC

FL / RT

XO / HF

Q7
Q6

32 Pin PLCC

Top View

15 16 17 18 19 20

1 32 31 30

MS7200L/7201AL/7202AL

MOSEL VITELIC

MS7200L/01AL/02AL Rev. 1.0 January 1995

Signal Descriptions

INPUTS:
Data In (D

- D

)

These data inputs accept 9-bit data words for

sequential storage in the FIFO during write
operations.

CONTROLS:
Reset (

)

The reset input is active LOW. When asserted,

the device is asynchronously reset, and both the
read and write internal pointers are set to the first
location in the FIFO. A Reset is required after
power-up before a write operation can occur. Both
Read Enable (

) and Write Enable (

) must be

HIGH during Reset.

Read Enable (

)

The read enable input is active LOW. As long as

the Empty Flag (

) is not set, the read cycle is

started on the falling edge of this signal. The data is
accessed on a First-In/First-Out basis, independent
of any write activity, and is presented on the Data
Output pins (Q0 - Q8). When

goes HIGH the Data

Output pins return to the high impedance state, and
the read pointer is incremented. When the FIFO is
empty or all of the data has been read, the Empty
Flag will be set and further read operations are
inhibited until a valid write operation has been
performed.

Write Enable (

)

The write enable input is active LOW. As long as

the Full Flag (

) is not set, the write cycle is started

on the falling edge of this signal. The data present
on the Data Input pins (D0 - D8) is stored
sequentially, independent of any read activity.
When

goes HIGH the write cycle is terminated

and the write pointer is incremented. When the
maximum capacity of the FIFO has been reached
the Full Flag will be set, and further write operations
are inhibited until a valid read operation has been
performed.

Expansion In (

)

This input pin serves two purposes. When

grounded, it indicates that the device is being
operated in the single device mode. In Depth
Expansion mode, this pin is connected to the
Expansion Out Output (

) of the previous device.

First Load/Retransmit (

)

This is a dual-purpose input. In single device

mode (when Expansion In (

) is grounded) this pin

acts as the retransmit input. A LOW pulse on this
will reset the read pointer to the first memory
location of the FIFO. The write pointer is unaffected.
Both the read enable (

) and write enable (

)

inputs must remain HIGH during the retransmit
cycle.

In Depth Expansion mode this pin acts as a first

load indicator. It must be grounded on the first
device in the chain to indicate which device is the
first to receive data.

OUTPUTS:
Data Output (Q

- Q

)

A 9 bit data word from the FIFO is output on these

pins during read operations. They are in the high
impedance state whenever

is HIGH.

Empty Flag (

)

This output is active LOW. When all of the data

has been read from the FIFO (defined as when the
Read pointer is one location behind the Write
pointer) this flag will be set. The Data Output pins
will be forced into the high impedance state, and all
further read operations will be inhibited until a valid
write operation has been performed (which will
reset this flag).

Full Flag (

)

This output is active LOW. To prevent data

overflow, when the maximum capacity of the FIFO
has been reached (defined as when the Write
pointer is one location behind the Read pointer) this
flag will be set. All further write operations will be
inhibited until a valid read operation has been
performed (which will reset this flag).

Expansion Out/Half Full Flag (

)

This dual-purpose output is active LOW. In single

device mode (when Expansion In (

) is grounded)

this flag will be set at the falling edge of the next
write operation after the FIFO has reached one-half
of its maximum capacity. This flag will remain set as
long as the difference between the read pointer and
the write pointer is greater than one-half of the
maximum capacity of the FIFO.

In Depth Expansion mode, this output is

connected to the Expansion In Input of the next
device in the chain. The Expansion Out pin
provides a pulse to the next device in the chain
when the last memory location has been reached.

MS7200L/7201AL/7202AL

MOSEL VITELIC

MS7200L/01AL/02AL Rev. 1.0 January 1995

Operating Range

Capacitance

(1)

= 25°C, f = 1.0MHz

Range

Ambient

Temperature

Vcc

Commercial

C to + 70

10%

Symbol

Parameter

Condition

Unit

TERM

Terminal Voltage with

Repect to GND

-0.5 to +7.0

BIAS

Temperature Under Bias

-10 to +125

STG

Storage Temperature

-60 to +150

Power Dissipation

1.0

OUT

DC Output Current

Absolute Maximum Ratings

(1)

Symbol

Parameter

Condition

Max.

Unit

Input Capacitance

= 0V

Output Capacitance

= 0V

DC Electrical Characteristics (over the commercial operating range)

Depth Expansion/Compound Expansion Mode

NOTE:
1.

is connected to

of previous device. See Figure 15.

= Reset Input.

= First Load/Retransmit.

= Empty Flag

Output.

Full Flag Output.

= Expansion Input.

Stresses greater than those listed under ABSOLUTE
MAXIMUM RATINGS may cause permanent damage to the
device. This is a stress rating only and functional operation
of the device at these or any other conditions above those
indicated in the operational sections of this specification is
not implied. Exposure to absolute maximum rating conditions
for extended periods may affect reliability.

Truth Tables

Single Device Configuration/Width Expansion Mode

NOTE: 1. Pointer will increment if flag is high.

Mode

Inputs

Internal Status

Outputs

Read Pointer

Write Pointer

Reset

Location Zero

Retransmit

Location Zero

Unchanged

Read/Write

Increment

(1)

Increment

(1)

Mode

Inputs

Internal Status

Outputs

Read Pointer

Write Pointer

Reset-First Device

(1)

Location Zero

Reset all Other Devices

(1)

Location Zero

Unchanged

Read/Write

(1)

Test

MS7200L/7201AL

7202AL

(-25, -35)

MS7200L/7201AL

7202AL

(-50, -80)

Parameter

Test Conditions

Min. Typ. Max. Min.

Typ. Max. Units

Input Low Voltage

0.8

Input High Voltage

2.0

Input Leakage Current

= Max, V

= 0Vto V

-1

Output Leakage Current

= Max, R= V

, V

= 0V toV

-10

Output Low Voltage

= Min, I

= 8mA

0.4

Output High Voltage

= Min, I

= -2mA

2.4

CC1

Operating Power Supply Current V

= Max, I

I/O

= 0mA, F = F

m ax

125

CC2

Average Standby Current

= Max,

I/O

= 0mA

CCSB(S)

Power Down Power Supply
Current (Standard Power)

= Max,

-0.2V, V

> V

-0.2V or V

0.2V

CCSB(L)

Power Down Power Supply
Current (Low Power)

= Max,

-0.2V, V

> V

-0.2V or V

0.2V

500

MS7200L/7201AL/7202AL

MOSEL VITELIC

MS7200L/01AL/02AL Rev. 1.0 January 1995

AC Electrical Characteristics (over the commercial operating range)

Parameter

MS7200L-25

MS7201AL-25
MS7202AL-25

MS7200L-35

MS7201AL-35
MS7202AL-35

MS7200L-50

MS7201AL-50
MS7202AL-50

MS7200L-80

MS7201AL-80
MS7202AL-80

Name

Parameter

Min.

Max.

Min.

Max.

Min.

Max.

Min.

Max.

Units

Shift Frequency

22.2

MHz

Read Cycle

Read Cycle Time

100

Access Time

RPW

Read Pulse Width

Read Recovery Time

RLZ

(2)

Read Pulse Low to Data Bus at Low Z

RHZ

(2,3)

Read Pulse High to Data Bus at High Z

Data Valid from Read Pulse High

Write Cycle

Write Cycle Time

100

WPW

(1)

Write Pulse Width

Write Recovery Time

Data Setup Time

Data Hold Time

WLZ

(2,3)

Write Pulse High to Data Bus at Low Z

Flag Timing

REF

Read Low to Empty Flag Low

RHF

Read High to Half Full Flag High

100

RFF

Read High to Full Flag High

WEF

Write High to Empty Flag High

WFF

Write Low to Full Flag Low

WHF

Write Low to Half Full Flag Low

100

RPE

Read Pulse Width After EF High

WPF

Write Pulse Width After

High

Reset Timing

RSC

Reset Cycle Time

100

(1)

Reset Pulse Width

RSS

Reset Set Up Time

RSR

Reset Recovery Time

EFL

Reset to Empty Flag Low

100

HFH

Reset to Half Full Flag High

100

FFH

Reset to Full Flag High

100

Retransmit Timing

RTC

Retransmit Cycle Time

100

(1)

Retransmit Pulse Width

RTS

Retransmit Set up Time

RTR

Retransmit Recovery Time

Expansion Timing

XOL

Read/Write to

Low

XOH

Read/Write to

High

Pulse Width

XIS

Set up Time

XIR

Recovery Time

NOTES:
1.

Pulse widths less than minimum value are not allowed.

Values guaranteed by design, not currently tested.

Only applies to read data flow-through mode.

MS7200L/7201AL/7202AL

MOSEL VITELIC

MS7200L/01AL/02AL Rev. 1.0 January 1995

INCLUDING
JIG AND
SCOPE

Figure 1a

30pF

R2
255

R1 480

OUTPUT

INCLUDING
JIG AND
SCOPE

5pF

R2
255

R1 480

OUTPUT

Figure 1b

167

OUTPUT

THEVENIN EQUIVALENT

Equivalent to:

ALL INPUT PULSES

90%

10%

5 ns

GND

3.0V

1.73V

Figure 2

AC Test Conditions

Key to Switching Waveforms

WAVEFORM

INPUTS

OUTPUTS

MUST BE
STEADY

WILL BE
STEADY

MAY CHANGE
FROM H TO L

WILL BE
CHANGING
FROM H TO L

MAY CHANGE
FROM L TO H

WILL BE
CHANGING
FROM L TO H

DON'T CARE:
ANY CHANGE
PERMITTED

CHANGING:
STATE
UNKNOWN

DOES NOT
APPLY

CENTER
LINE IS HIGH
IMPEDANCE
"OFF" STATE

AC Test Loads and Waveforms

Timing Waveforms

Input Pulse Levels

0V~ 3.0V

Input Rise and Fall Times

5 ns

Timing Reference Level

1.5V

RSS

RSC

EFL

RSR

HFH

, t

FFH

RSS

HF, FF

RESET

Q0-Q8

RPW

RLZ

RHZ

READ

DATA VALID

READ

DATA VALID

ASYNCHRONOUS READ OPERATION

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