MOSEL VITELIC

V29C51004T/V29C51004B
4 MEGABIT (524,288 x 8 BIT)
5 VOLT CMOS FLASH MEMORY

PRELIMINARY

V29C51004T/V29C51004B Rev. 1.5 October 2000

Features

512Kx8-bit Organization

Address Access Time: 70, 90 ns

Single 5V

10% Power Supply

Sector Erase Mode Operation

16KB Boot Block (lockable)

1K bytes per Sector, 512 Sectors
Sector-Erase Cycle Time: 10ms (Max)
Byte-Write Cycle Time: 20

s (Max)

Minimum 10,000 Erase-Program Cycles

Low power dissipation
Active Read Current: 20mA (Typ)
Active Program Current: 30mA (Typ)
Standby Current: 50

A (Max)

Hardware Data Protection

Low V

Program Inhibit Below 3.5V

Self-timed write/erase operations with end-of-
cycle detection
DATA Polling
Toggle Bit

CMOS and TTL Interface

Available in two versions
V29C51004T (Top Boot Block)
V29C51004B (Bottom Boot Block)

Packages:
32-pin TSOP-I
32-pin PLCC

Description

The V29C51004T/V29C51004B is a high speed

524,288 x 8 bit CMOS flash memory. Writing or
erasing the device is done with a single 5 Volt
power supply. The device has separate chip enable
CE, write enable WE, and output enable OE
controls to eliminate bus contention.

The V29C51004T/V29C51004B offers a combi-

nation of: Boot Block with Sector Erase/Write
Mode. The end of write/erase cycle is detected by
DATA Polling of I/O

or by the Toggle Bit I/O

The V29C51004T/V29C51004B features a

sector erase operation which allows each sector to
be erased and reprogrammed without affecting
data stored in other sectors. The device also
supports full chip erase.

Boot block architecture enables the device to

boot from a protected sector located either at the
top (V29C51004T) or the bottom (V29C51004B).
A l l i n p u t s a n d o u t p u t s a r e C M O S a n d T T L
compatible.

The V29C51004T/V29C51004B is ideal for

applications that require updatable code and data
storage.

Device Usage Chart

Operating

Temperature Range

Package Outline

Access Time (ns)

Temperature

Mark

C to 70

Blank

V29C51004T/V29C51004B Rev. 1.5 October 2000

MOSEL VITELIC

V29C51004T/V29C51004B

OPERATING VOLTAGE

51: 5V

DEVICE

SPEED

51004-01

004

BOOT BLOCK LOCATION

T: TOP

B: BOTTOM

70: 70ns
90: 90ns

BLANK (0

C TO 70

T = TSOP-I

J = PLCC

TEMP.

PKG.

Pin Configurations

I/O

51004-02

I/O

GND

I/O

32 Pin PLCC

Top View

15 16 17 18 19 20

32 31 30

Pin Names

Address Inputs

I/O

Data Input/Output

Chip Enable

Output Enable

Write Enable

10% Power Supply

GND

Ground

NC No

Connect

A11

A9
A8

A13
A14
A17

VCC

A18
A16
A15
A12

A7
A6
A5
A4

1
2
3
4
5
6

8
9
10
11
12
13
14
15
16

29
28
27
26
25

24
23
22
21
20

32-Pin TSOP I

Standard Pinout

Top View

OE
A10
CE
I/O7
I/O6
I/O5
I/O4
I/O3
GND
I/O2
I/O1

I/O0

19
18
17

51004-03

MOSEL VITELIC

V29C51004T/V29C51004B

V29C51004T/V29C51004B Rev. 1.5 October 2000

Functional Block Diagram

Capacitance

(1,2)

NOTE:

Capacitance is sampled and not 100% tested.

= 25

C, V

= 5V

10%, f = 1 MHz.

Latch Up Characteristics

(1)

NOTE:

Includes all pins except V

. Test conditions: V

= 5V, one pin at a time.

AC Test Load

Symbol

Parameter

Test Setup

Typ.

Max.

Units

Input Capacitance

= 0

OUT

Output Capacitance

OUT

= 0

IN2

Control Pin Capacitance

= 0

Parameter Min.

Max.

Unit

Input Voltage with Respect to GND on A

, OE

-1

+13

Input Voltage with Respect to GND on I/O, address or control pins

-1

+ 1

Current

-100

+100

Address buffer & latches

51004-07

I/O Buffer & Data Latches

I/O

Y-Decoder

4,194,304 Bit

Memory Cell Array

X-Decoder

Control Logic

51004-08

IN3064 or Equivalent

IN3064

or Equivalent

2.7 k

6.2 k

+5.0 V

IN3064 or Equivalent

= 100 pF

Device Under

Test

V29C51004T/V29C51004B Rev. 1.5 October 2000

MOSEL VITELIC

V29C51004T/V29C51004B

Absolute Maximum Ratings

(1)

NOTE:

Stress greater than those listed unders "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress
rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections
of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.

No more than one output maybe shorted at a time and not exceeding one second long.

DC Electrical Characteristics

(over the commercial operating range)

Symbol

Parameter

Commercial

Unit

Input Voltage (input or I/O pins)

-2 to +7

Input Voltage (A

pin, OE)

-2 to +13

Power Supply Voltage

-0.5 to +5.5

STG

Storage Temerpature (Plastic)

-65 to +125

OPR

Operating Temperature

0 to +70

OUT

Short Circuit Current

(2)

200 (Max.)

Parameter
Name

Parameter

Test Conditions

Min.

Max.

Unit

Input LOW Voltage

= V

Min.

0.8

Input HIGH Voltage

= V

Max.

Input Leakage Current

= GND to V

, V

= V

Max.

Output Leakage Current

OUT

= GND to V

, V

= V

Max.

Output LOW Voltage

= V

Min., I

= 2.1mA

0.4

Output HIGH Voltage

= V

Min, I

= -400

2.4

CC1

Read Current

CE = OE = V

, WE = V

, all I/Os open,

Address input = V

, at f = 1/t

Min.,

= V

Max.

CC2

Write Current

CE = WE = VIL, OE = V

, V

= V

Max.

TTL Standby Current

CE = OE = WE = V

, V

= V

Max.

SB1

CMOS Standby Current

CE = OE = WE = V

0.3V, V

= V

Max.

100

Device ID Voltage for A

CE = OE = V

, WE = V

11.5

12.5

Device ID Current for A

CE = OE = V

, WE = V

, A9 = V

Max.

MOSEL VITELIC

V29C51004T/V29C51004B

V29C51004T/V29C51004B Rev. 1.5 October 2000

AC Electrical Characteristics

(over all temperature ranges)

Read Cycle

Program (Erase/Program) Cycle

Parameter

Name

Parameter

-70

-90

Unit

Min.

Max.

Min.

Max.

Read Cycle Time

Address Access Time

ACS

Chip Enable Access Time

Output Enable Access Time

CLZ

CE Low to Output Active

OLZ

OE Low to Output Active

OE or CE High to Output in High Z

Output Hold from Address Change

Parameter

Name

Parameter

-70

-90

Unit

Min.

Typ.

Max.

Min.

Typ.

Max.

Write Cycle Time

Address Setup Time

Address Hold Time

CE Setup Time

CE Hold Time

OES

OE Setup Time

OEH

OE High Hold Time

WE Pulse Width

WPH

WE Pulse Width High

Data Setup Time

Data Hold Time

WHWH1

Programming Cycle

WHWH2

Sector Erase Cycle

WHWH3

Chip Erase Cycle

sec

V29C51004T/V29C51004B Rev. 1.5 October 2000

MOSEL VITELIC

V29C51004T/V29C51004B

Waveforms of Read Cycle

Waveforms of WE Controlled-Program Cycle

NOTES:
1.

I/O

: The output is the complement of the data written to the device.

PA: The address of the memory location to be programmed.

PD: The data at the byte address to be programmed.

CLZ

OLZ

ADDRESS

I/O

VALID DATA OUT

HIGH-Z

51004-09

HIGH-Z

5555H

WHWH1

WPH

OES

OUT

I/O

(1)

(3)

A0H

51004-10

ADDRESS

I/O

3rd bus cycle

(2)

MOSEL VITELIC

V29C51004T/V29C51004B

V29C51004T/V29C51004B Rev. 1.5 October 2000

Waveforms of CE Controlled-Program Cycle

Waveforms of Erase Cycle

(1)

NOTES:
1.

PA: The address of the memory location to be programmed.

PD: The data at the byte address to be programmed.

SA: The sector address for Sector Erase.

WHWH1

WPH

OES

OUT

I/O7

(2)

A0H

51004-11

ADDRESS

5555H

(1)

I/O

WPH

WHWH

2
3

ADDRESS

I/O

5555H

2AAAH

(5555H for Chip Erase)

AAH

55H

80H

AAH

55H

30H

(10H for

Chip Erase)

51004-12

V29C51004T/V29C51004B Rev. 1.5 October 2000

MOSEL VITELIC

V29C51004T/V29C51004B

Functional Description

The V29C51004T/V29C51004B consists of 512

equally-sized sectors of 1K bytes each. The 16 KB
lockable Boot Block is intended for storage of the
system BIOS boot code. The boot code is the first
piece of code executed each time the system is
powered on or rebooted.

The V29C51004 is available in two versions: the

V29C51004T with the Boot Block address starting
from 7C000H to 7FFFFH, and the V29C51004B
with the Boot Block address starting from 00000H
to 3FFFFH.

Read Cycle

A read cycle is performed by holding both CE

and OE signals LOW. Data Out becomes valid only
when these conditions are met. During a read cycle
WE must be HIGH prior to CE and OE going LOW.
WE must remain HIGH during the read operation
for the read to complete (see Table 1).

Output Disable

Returning OE or CE HIGH, whichever occurs first

will terminate the read operation and place the l/O
pins in the HIGH-Z state.

Standby

The device will enter standby mode when the CE

signal is HIGH. The l/O pins are placed in the
HIGH-Z, independent of the OE input state.

Command Sequence

T h e V 2 9 C 5 1 0 0 4 T / V 2 9 C 5 1 0 0 4 B d o e s n o t

provide the "reset" feature to return the chip to its
normal state when an incomplete command
sequence or an interruption has happened. In this
case, normal operation (Read Mode) can be
restored by issuing a "non-existent" command
sequence, for example Address: 5555H, Data FFH.

Byte Write Cycle

The V29C51004T/V29C51004B is programmed

on a byte-by-byte basis. The byte write operation is
initiated by using a specific four-bus-cycle
sequence: two unlock program cycles, a program
setup command and program data program cycles
(see Table 2).

During the byte write cycle, addresses are

latched on the falling edge of either CE or WE,
whichever is last. Data is latched on the rising edge
of CE or WE, whichever is first. The byte write cycle
can be CE controlled or WE controlled.

Sector Erase Cycle

The V29C51004T/V29C51004B features a

sector erase operation which allows each sector to
be erased and reprogrammed without affecting
data stored in other sectors. Sector erase operation
is initiated by using a specific six-bus-cycle
sequence: Two unlock program cycles, a setup
command, two additional unlock program cycles,
and the sector erase command (see Table 2). A
sector must be first erased before it can be re-

16KB Boot Block

1 KB

16KB Boot Block

V29C51004T

V29C51004B

7FFFFH

7C000H

00000H

03FFFH

51004-15

00000H

16KB Boot Block = 32 Sectors

Table 1. Operation Modes Decoding

NOTES:
1.

X = Don't Care, V

= HIGH, V

= LOW, V

= 12.5V Max.

PD: The data at the byte address to be programmed.

Decoding Mode

I/O

Read

READ

Byte Write

Standby

HIGH-Z

Autoselect Device ID

CODE

Autoselect Manufacture ID

CODE

Enabling Boot Block Protection Lock

Disabling Boot Block Protection Lock

Output Disable

HIGH-Z

V29C51004T/V29C51004B Rev. 1.5 October 2000

MOSEL VITELIC

V29C51004T/V29C51004B

written. While in the internal erase mode, the
device ignores any program attempt into the
device. The internal erase completion can be
determined via DATA polling or toggle bit status.

The V29C51004T/V29C51004B is shipped fully

erased (all bits = 1).

Chip Erase Cycle

The V29C51004T/V29C51004B features a chip-

erase operation. The chip erase operation is
i n i t i a t e d b y u s i n g a s p e c i f i c s i x - b u s - c y c l e
sequence: two unlock program cycles, a setup
command, two additional unlock program cycles,
and the chip erase command (see Table 2).

The automatic erase begins on the rising edge of

the last WE or CE pulse in the command sequence
and terminates when the data on DQ7 is "1".

Program Cycle Status Detection

There are two methods for determining the state

o f t h e V 2 9 C 5 1 0 0 4 T / V 2 9 C 5 1 0 0 4 B d u r i n g a
program (erase/write) cycle: DATA Polling (I/O

)

and Toggle Bit (I/O

DATA Polling (I/O

)

The V29C51004T/V29C51004B features DATA

polling to indicate the end of a program cycle.
When the device is in the program cycle, any
attempt to read the device will received the
complement of the loaded data on I/O

. Once the

program cycle is completed, I/O

will show true

data, and the device is then ready for the next
cycle.

Toggle Bit (I/O

)

The V29C51004T/V29C51004B also features

another method for determining the end of a
program cycle. When the device is in the program
cycle, any attempt to read the device will result in
l/O

toggling between 1 and 0. Once the program is

completed, the toggling will stop. The device is then
ready for the next operation. Examining the toggle
bit may begin at any time during a program cycle.

Boot Block Protection Enabling/Disabling

T h e V 2 9 C 5 1 0 0 4 T / V 2 9 C 5 1 0 0 4 B f e a t u r e s

hardware Boot Block Protection. The boot block
sector protection is enabled when high voltage
(12.5V) is applied to OE and A9 pins with CE pin
LOW and WE pin LOW. The sector protection is
disabled when high voltage is applied to OE, CE
and A9 pins with WE pin LOW. Other pins can be
HIGH or LOW. This is shown in table 1.

Autoselect Mode

The V29C51004T/V29C51004B features an

Autoselect mode to identify boot block locking
status, device ID and manufacturer ID.

Entering Autoselect mode is accomplished by

applying a high voltage (VH) to the A9 Pin, or
through a sequence of commands (as shown in
table 2). Device will exit this mode once high
voltage on A9 is removed or another command is
loaded into the device.

Table 2. Command Codes

NOTES:
1.

RA: Read Address

RD: Read Data

PA: The address of the memory location to be programmed.

PD: The data at the byte address to be programmed.

SA(5): Sector Address

Command
Sequence

First Bus
Program Cycle

Second Bus
Program Cycle

Third Bus
Program Cycle

Fourth Bus
Program Cycle

Fifth Bus
Program Cycle

Six Bus
Program Cycle

Address

Data

Address

Data

Address

Data

Address

Data

Address

Data

Address

Data

Read

XXXXH

F0H

Read

5555H

AAH

2AAAH

55H

5555H

F0H

RA(1)

RD(2)

Autoselect
Mode

5555H

AAH

2AAAH

55H

5555H

90H

See table 3 for detail.

Byte
Program

5555H

AAH

2AAAH

55H

5555H

A0H

PD(4)

Chip Erase

5555H

AAH

2AAAH

55H

5555H

80H

5555H

AAH

2AAAH

55H

5555H

10H

Sector Erase

5555H

AAH

2AAAH

55H

5555H

80H

5555H

AAH

2AAAH

55H

SA(5)

30H

V29C51004T/V29C51004B Rev. 1.5 October 2000

MOSEL VITELIC

V29C51004T/V29C51004B

Boot Block Protection Status

In Autoselect mode, performing a read at

address location 3CXX2H (V29C51004T) or
0CXX2H (V29C51004B) will indicate boot block
protection status. If the data is 01H, the boot block
is protected. If the data is 00H, the boot block is
unprotected. This is also shown is table 3.

Device ID

In Autoselect mode, performing a read at

address XXX1H will determine whether the device
is a Top Boot Block device or a Bottom Boot Block
device. If the data is 03H, the device is a Top Boot
Block. If the data is A3H, the device is a Bottom
Boot Block device (see Table 3).

Manufacturer ID

In Autoselect mode, performing a read at

address XXXX0H will determine the manufacturer
ID. 40H is the manufacturer code for Mosel Vitelic
Flash.

Hardware Data Protection

Detection: the program operation is inhibited

when VCC is less than 3.5V.

Noise Protection: a CE or WE pulse of less than

5ns will not initiate a program cycle.

Program Inhibit: holding any one of OE LOW, CE

HIGH or WE HIGH inhibits a program cycle.

Table 3. Autoselect Decoding

NOTE:
1.

X = Don't Care, V

= HIGH, V

= LOW.

Decoding Mode

Boot Block

Address

Data I/O

I/O

Boot Block Protection

Top

01H: protected

Bottom

00H: unprotected

Device ID

Top

03H

Bottom

A3H

Manufacture ID

40H

V29C51004T/V29C51004B Rev. 1.5 October 2000

MOSEL VITELIC

V29C51004T/V29C51004B

Package Diagrams

32-pin PLCC

32-pin TSOP-I

.420

.003

- 6

.017

.136

.003

.110

.046

.003

.025

.050 TYP

.450

.003

.490

.005

.045X45

.590

.005

.550

.003

19 18

17 16 15

31 32

0.032 TYP.

0.020 SBC

0.003 MAX

0.020 MAX.

0.024

0.004

SEATING
PLANE

0.010

See Detail "A"

Detail "A"

0.724 TYP. (0.728 MAX.)

0.787

0.008

0.009

0.002

0.315 TYP.

(0.319 MAX.)

0.035

0.002

0.047 MAX.

0.005 MIN.

0.007 MAX.

Units in inches

MOSEL VITELIC

WORLDWIDE OFFICES

V29C51004T/V29C51004B

10/00
Printed in U.S.A.

MOSEL VITELIC

3910 N. First Street, San Jose, CA 95134-1501 Ph: (408) 433-6000 Fax: (408) 433-0952 Tlx: 371-9461

The information in this document is subject to change without
notice.

MOSEL VITELIC makes no commitment to update or keep cur-
rent the information contained in this document. No part of this
document may be copied or reproduced in any form or by any
means without the prior written consent of MOSEL-VITELIC.

MOSEL VITELIC subjects its products to normal quality control
sampling techniques which are intended to provide an assurance
of high quality products suitable for usual commercial applica-
tions. MOSEL VITELIC does not do testing appropriate to provide
100% product quality assurance and does not assume any liabil-
ity for consequential or incidental arising from any use of its prod-
ucts. If such products are to be used in applications in which
personal injury might occur from failure, purchaser must do its
own quality assurance testing appropriate to such applications.

U.S. SALES OFFICES

U.S.A.

3910 NORTH FIRST STREET
SAN JOSE, CA 95134
PHONE: 408-433-6000

FAX: 408-433-0952

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