MOSEL VITELIC

V43648Y04V(C)TG-75
3.3 VOLT 8M x 64 HIGH PERFORMANCE
PC133 UNBUFFERED SODIMM

PRELIMINARY

V43648Y04V(C)TG-75 Rev. 1.1 June 2000

Features

JEDEC-standard 144 pin, Small-Outline, Dual in
line Memory Module (SODIMM)

Serial Presence Detect with E

PROM

Fully Synchronous, All Signals Registered on
Positive Edge of System Clock

Single +3.3V (

0.3V) Power Supply

All Device Pins are LVTTL Compatible

4096 Refresh Cycles every 64 ms

Self-Refresh Mode

Internal Pipelined Operation; Column Address
can be changed every System Clock

Programmable Burst Lengths: 1, 2, 4, 8 or Full
Page

Auto Precharge and Precharge all Banks by A10

Data Mask Function by DQM

Mode Register Set Programming

Programmable (CAS Latency: 3 Clocks)

Description

The V43648Y04V(C)TG-75 memory module is

organized 8,388,608 x 64 bits in a 144 pin
SODIMM. The 8M x 64 memory module uses 8
Mosel-Vitelic 4M x 16 SDRAM. The x64 modules
are ideal for use in high performance computer
systems where increased memory density and fast
access times are required.

Part Number

Speed Grade

Configuration

V43648Y04V(C)TG-75

-75 (133 MHz)

8M x 64

V43648Y04V(C)TG-75-01

Pin 2 on Backside

Pin 144 on Backside

143

4M x 16

V43648Y04V(C)TG-75 Rev. 1.1 June 2000

MOSEL VITELIC

V43648Y04V(C)TG-75

Pin Configurations (Front Side/Back Side)

Note:

1. RAS, CAS, WE CASx, CSx are active low signals.

Pin

Front

Pin

Front

Pin

Front

Pin

Back

Pin

Back

Pin

Back

1
2
3
4
5
6
7
8
9

10
11
12
13
14
15
16
17
18
19
20
21
22
23
24

VSS
VSS
DQ0

DQ32

DQ1

DQ33

DQ2

DQ34

DQ3

DQ35

VDD
VDD
DQ4

DQ36

DQ5

DQ37

DQ6

DQ38

DQ7

DQ39

VSS
VSS

DQMB0
DQMB4

25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48

DQMB1
DQMB5

VDD
VDD

A0
A3
A1
A4
A2
A5

VSS
VSS
DQ8

DQ40

DQ9

DQ41
DQ10
DQ42
DQ11
DQ43

VDD
VDD

DQ12
DQ44

49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72

DQ13
DQ45
DQ14
DQ46
DQ15
DQ47

VSS
VSS

NC
NC
NC
NC

CLK0

CKE0

VDD
VDD
RAS
CAS

CKE1

CS0

CS1

73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96

CLK1

VSS
VSS

NC
NC
NC
NC

VDD
VDD

DQ16
DQ48
DQ17
DQ49
DQ18
DQ50
DQ19
DQ51

VSS
VSS

DQ20
DQ52
DQ21
DQ53

97
98
99

100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120

DQ22
DQ54
DQ23
DQ55

VDD
VDD

A6
A7
A8

BA0

VSS
VSS

BA1

A10
A11

VDD
VDD

DQMB2
DQMB6
DQMB3
DQMB7

VSS
VSS

121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144

DQ24
DQ56
DQ25
DQ57
DQ26
DQ58
DQ27
DQ59

VDD
VDD

DQ28
DQ60
DQ29
DQ61
DQ30
DQ62
DQ31
DQ63

VSS
VSS
SDA
SCL

VDD
VDD

Pin Names

A0A11, BA0, BA1

Address, Bank Select

DQ0DQ63

Data Inputs/Outputs

RAS

Row Address Strobes

CAS

Column Address Strobes

Write Enable

CS0, CS1

Chip Select

DQMB0DQMB7

Output Enable

CKE0, CKE1

Clock Enable

CLK0CLK1

Clock

SDA

Serial Input/Output

SCL

Serial Clock

VDD

Power Supply

VSS

Ground

No Connect (Open)

MOSEL VITELIC

V43648Y04V(C)TG-75

V43648Y04V(C)TG-75 Rev. 1.1 June 2000

Part Number Information

Block Diagram

SDRAM

3.3V

V43648Y04V(C)TG-75-02

MOSEL-VITELIC

MANUFACTURED

144 PIN UNBUFFERED

SODIMM x16 COMPONENT

REFRESH
RATE 4K

DEPTH

4 BANKS

WIDTH

LVTTL

TSOP

GOLD

75 (133 MHz)
PC133

COMPONENT REVISION LEVEL
BLANK = REV B
C = REV C

CS0

V43648Y04V(C)TG-75-03

U0U7

A0A11, BA0, BA1

VDD

U0U3

CKE0

U4U7

CKEI

U0U7

U0, U1

CLK0

VSS

U2, U3

SCL

SDA

U4, U5

CLKI

U6, U7

SPD

DQMB4

DQMB5

DQ3239

DQ4047

UDQM

LDQM

DQMB0

DQMB1

DQ07

DQ815

UDQM

LDQM

DQMB6

DQMB7

DQ4354

DQ5563

UDQM

LDQM

DQMB2

DQMB3

DQ1623

DQ2431

UDQM

LDQM

CS1

DQMB4

DQMB5

DQ3239

DQ4047

UDQM

LDQM

DQMB0

DQMB1

DQ07

DQ815

UDQM

LDQM

DQMB6

DQMB7

DQ4354

DQ5563

UDQM

LDQM

DQMB2

DQMB3

DQ1623

DQ2431

UDQM

LDQM

V43648Y04V(C)TG-75 Rev. 1.1 June 2000

MOSEL VITELIC

V43648Y04V(C)TG-75

Serial Presence Detect Information

A serial presence detect storage device -

PROM - is assembled onto the module. Informa-

tion about the module configuration, speed, etc. is

written into the E

PROM device during module pro-

duction using a serial presence detect protocol (I

synchronous 2-wire bus)

SPD-Table for 75 modules:

Byte Number

Function Described

SPD Entry Value

Hex Value

8Mx64

Number of SPD bytes

128

Total bytes in Serial PD

256

Memory Type

SDRAM

Number of Row Addresses (without BS bits)

Number of Column Addresses (for x16 SDRAM)

Number of DIMM Banks

Module Data Width

Module Data Width (continued)

Module Interface Levels

LVTTL

SDRAM Cycle Time at CL=3

7.5 ns

SDRAM Access Time from Clock at CL=3

5.4 ns

Dimm Config (Error Det/Corr.)

none

Refresh Rate/Type

Self-Refresh, 15.6

SDRAM width, Primary

x16

Error Checking SDRAM Data Width

n/a / x8

Minimum Clock Delay from Back to Back Random
Column Address

ccd

= 1 CLK

Burst Length Supported

1, 2, 4, 8 & full Page

Number of SDRAM Banks

Supported CAS Latencies

CL = 3

CS Latencies

CS Latency = 0

WE Latencies

WL = 0

SDRAM DIMM Module Attributes

Non Buffered/Non Reg.

SDRAM Device Attributes: General

Vcc tol

10%

Minimum Clock Cycle Time at CAS Latency = 2

Not Supported

Maximum Data Access Time from Clock for CL = 2

Not Supported

Minimum Clock Cycle Time at CL = 1

Not Supported

Maximum Data Access Time from Clock at CL = 1

Not Supported

Minimum Row Precharge Time

20 ns

Minimum Row Active to Row Active Delay t

RRD

15 ns

Minimum RAS to CAS Delay t

RCD

20 ns

Minimum RAS Pulse Width t

RAS

45 ns

MOSEL VITELIC

V43648Y04V(C)TG-75

DC Characteristics

= 0

C to 70

C; V

= 0 V; V

, V

DDQ

= 3.3V

0.3V

Module Bank Density (Per Bank)

32 Mbyte

SDRAM Input Setup Time

1.5 ns

SDRAM Input Hold Time

0.8 ns

SDRAM Data Input Setup Time

1.5 ns

SDRAM Data Input Hold Time

0.8 ns

62-61

Superset Information (May be used in Future)

SPD Revision

Revision 2

Checksum for Bytes 0 - 62

Manufacturer's JEDEC ID Code

Mosel Vitelic

65-71

Manufacturer's JEDEC ID Code (cont.)

Manufacturing Location

1 = US, 2 = Taiwan

73-90

Module Part Number (ASCII)

V43648Y04V(C)TG-75

91-92

PCB Identification Code

Current PCB Revision

Assembly Manufacturing Date (Year)

Binary Coded year (BCD)

Assembly Manufacturing Date (Week)

Binary Coded week (BCD)

95-98

Assembly Serial Number

byte 95 = LSB, byte 98 = MSB

99-127

Reserved

128+

Unused Storage Location

Symbol

Parameter

Limit Values

Unit

Min.

Max.

Input High Voltage

2.0

+0.3

Input Low Voltage

0.5

0.8

Output High Voltage (I

OUT

= 2.0 mA)

2.4

Output Low Voltage (I

OUT

= 2.0 mA)

0.4

I(L)

Input Leakage Current, any input
(0 V < V

< 3.6 V, all other inputs = 0V)

O(L)

Output leakage current
(DQ is disabled, 0V < V

OUT

< V

)

SPD-Table for 75 modules: (Continued)

Byte Number

Function Described

SPD Entry Value

Hex Value

8Mx64

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