1
V53C104D
MOSEL VITELIC
V53C104D Rev. 1.0 January 1995
HIGH PERFORMANCE V53C104D
60
70
80
Max.
RAS
Access Time, (t
RAC
)
60 ns
70 ns
80 ns
Max. Column Address Access Time, (t
CAA
)
30 ns
35 ns
40 ns
Min. Fast Page Mode Cycle Time, (t
PC
)
40 ns
45 ns
50 ns
Min. Read/Write Cycle Time, (t
RC
)
120 ns
130 ns
150 ns
V53C104D
HIGH PERFORMANCE, LOW POWER
256K X 4 BIT FAST PAGE MODE
CMOS DYNAMIC RAM
PRELIMINARY
Features
s
256K x 4 Organization
s
RAS access time: 60,70,80 ns
s
Low power dissipation for V53C104D-80
Operating Current 75 mA max.
TTL Standby Current 2.0 mA max.
s
Low CMOS Standby Current
V53C104D 1.0 mA max.
s
Read-Modify-Write, RAS-Only Refresh,
CAS
-Before-
RAS
Refresh capability.
s
Common I/O capability
s
Refresh Interval
V53C104D 512 cycles/8ms
s
Fast Page Mode for a sustained data rate
greater than 25 MHz
s
Standard packages are 20 pin Plastic DIP and
26/20 pin SOJ
Description
The V53C104D is a high speed 262,144 x 4 bit
CMOS dynamic random access memory. The
V53C104D offers a combination of features: Fast
Page Mode for high data bandwidth, fast usable
speed, CMOS standby current.
All inputs and outputs are TTL compatible. Input
and output capacitances are significantly lowered to
allow increased system performance. Fast Page
Mode operation allows random access of up to 512
(x4) bits within a row with cycle times as short as 40 ns.
Because of static circuitry, the
CAS
clock is not
in the critical timing path. The flow-through column
address latches allow address pipelining while relax-
ing many critical system timing requirements for fast
usable speed. These features make the V53C104D
ideally suited for graphics, digital signal processing
and high performance computing systems
Device Usage Chart
Operating
Package Outline
Access Time (ns)
Power
Temperature
Temperature
Range
P
K
60
70
80
Std.
Mark
0
C to 70
C
Blank
2
V53C104D
MOSEL VITELIC
V53C104D Rev. 1.0 January 1995
20 Lead Plastic DIP
PIN CONFIGURATION
Top View
26/20 Lead SOJ Package
PIN CONFIGURATION
Top View
V
FAMILY
DEVICE
P
K
(PLASTIC DIP)
(SOJ)
BLANK (0
C to 70
C)
BLANK (NORMAL)
60 (60 ns)
70 (70 ns)
80 (80 ns)
LOW (LOW POWER)
PKG.
SPEED
(t
RAC
)
TEMP.
PWR.
5
3
C
1
0
4
D
Description
Pkg.
Pin Count
Plastic DIP
P
20
SOJ
K
26/20
WE
RAS
NC
I/O1
I/O2
A 0
A 1
A 2
A 3
VDD
1
2
3
4
5
9
10
11
12
13
26
25
24
23
22
18
17
16
15
14
V
I/O
I/O
CAS
OE
A
A
A
A
A
SS
4
3
8
7
6
5
4
V53C104DK
WE
RAS
NC
I/O1
I/O2
A 0
A 1
A 2
A 3
VDD
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
V
I/O
I/O
CAS
OE
A
A
A
A
A
SS
4
3
8
7
6
5
4
V53C104DP
Absolute Maximum Ratings*
Ambient Temperature
Under Bias ............................. 10
C to +80
C
Storage Temperature (plastic) .... 55
C to +125
C
Voltage Relative to V
SS
......................
1.0 V to +7.0 V
Voltage on V
DD
relative to V
SS
.......
1.0 V to +7.0 V
Data Output Current .................................... 50 mA
Power Dissipation ......................................... 1.0 W
*Note: Operation above Absolute Maximum Ratings can
adversely affect device reliability.
* Note: Capacitance is sampled and not 100% tested
Capacitance*
T
A
= 25
C, V
DD
= 5 V
10%, V
SS
= 0 V
Symbol
Parameter
Typ.
Max.
Unit
C
IN1
Address Input
--
6
pF
C
IN2
RAS
,
CAS
,
WE
,
OE
--
7
pF
C
OUT
Data Input/Output
--
6
pF
Pin Names
A
0
A
8
Address Inputs
RAS
Row Address Strobe
CAS
Column Address Strobe
WE
Write Enable
OE
Output Enable
I/O
1
I/O
4
Data Input, Output
V
DD
+5V Supply
V
SS
0V Supply
NC
No Connect
5
V53C104D
MOSEL VITELIC
V53C104D Rev. 1.0 January 1995
AC Characteristics
T
A
= 0
C to 70
C, V
DD
= 5 V
10%, V
SS
= 0V unless otherwise noted
AC Test conditions, input pulse levels 0 to 3V
60
70
80
#
Symbol
Symbol
Parameter
Unit
Notes
Min.
Max.
Min.
Max.
Min. Max.
1
t
RL1RH1
t
RAS
RAS
Pulse Width
60
16K
70
16K
80
16K
ns
2
t
RL2RL2
t
RC
Read or Write Cycle Time
110
130
150
ns
3
t
RH2RL2
t
RP
RAS
Precharge Time
40
50
60
ns
4
t
RL1CH1
t
CSH
CAS
Hold Time
60
70
80
ns
5
t
CL1CH1
t
CAS
CAS
Pulse Width
15
100K
20
100K
20
100K
ns
6
t
RL1CL1
t
RCD
RAS
to
CAS
Delay
20
40
20
50
20
60
ns
4
7
t
WH2CL2
t
RCS
Read Command Setup Time
0
0
0
ns
8
t
AVRL2
t
ASR
Row Address Setup Time
0
0
0
ns
9
t
RL1AX
t
RAH
Row Address Hold Time
10
10
12
ns
10
t
AVCL2
t
ASC
Column Address Setup Time
0
0
0
ns
11
t
CL1AX
t
CAH
Column Address Hold Time
12
15
15
ns
12
t
CL1RH1(R)
t
RSH (R)
RAS
Hold Time (Read Cycle)
20
20
20
ns
13
t
CH2RL2
t
CRP
CAS
to
RAS
Precharge Time
10
10
10
ns
14
t
CH2WX
t
RCH
Read Command Hold Time
0
0
0
ns
5
Referenced to
CAS
15
t
RH2WX
t
RRH
Read Command Hold Time
0
0
0
ns
5
Referenced to
RAS
16
t
OEL1RH2
t
ROH
RAS
Hold Time
15
15
20
ns
Referenced to
OE
17
t
GL1QV
t
OAC
Access Time from
OE
15
15
20
ns
18
t
CL1QV
t
CAC
Access Time from
CAS
20
20
20
ns
6,7
19
t
RL1QV
t
RAC
Access Time from
RAS
60
70
80
ns
6,8,9
20
t
AVQV
t
CAA
Access Time from Column
30
35
40
ns
6,7,
Address
10
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