MOSEL VITELIC
1
V53C16129L
3.3 VOLT 128K x 16
EDO PAGE MODE
CMOS DYNAMIC RAM
PRELIMINARY
V53C16129L Rev. 1.0 May 1997
HIGH PERFORMANCE
60
Max. RAS Access Time, (t
RAC
)
60 ns
Max. Column Address Access Time, (t
CAA
)
30 ns
Min. Extended Data Out Page Mode Cycle Time, (t
PC
)
27 ns
Min. Read/Write Cycle Time, (t
RC
)
110 ns
Features
s
128K x 16-bit organization
s
EDO Page Mode for a sustained data rate
of 37 MHz
s
RAS access time: 60 ns
s
Dual CAS Input
s
Low power dissipation
s
Read-Modify-Write, RAS-Only Refresh,
CAS-Before-RAS Refresh
s
Refresh Interval 512 cycles/8 ms
s
Available in 40-pin 400 mil SOJ and 40/44L-pin
400 mil TSOP-II packages
s
Single +3.3
0.3V Power Supply
s
TTL Interface
Description
The V53C16129L is a high speed 131,072 x 16
bit high performance CMOS dynamic random
access memory. The V53C16129L offers a
combination of unique features including: EDO
Page Mode operation for higher sustained
bandwidth with Page Mode cycle times as short as
27ns. All inputs are TTL compatible. Input and
output capicatance is significantly lowered to
increase performance and minimize loading. These
features make the V53C16129L ideally suited for a
wide variety of high performance portable computer
systems and peripheral applications.
Device Usage Chart
Operating
Temperature
Range
Package Outline
Access Time (ns)
Power
Temperature
Mark
K
T
60
Std.
0
C to 70
C
Blank
2
V53C16129L Rev. 1.0 May 1997
MOSEL VITELIC
V53C16129L
FAMILY
DEVICE
PKG
( t
RAC
)
SPEED
PWR.
V
5
3
C
1
2
9
60 (60 ns)
TEMP.
BLANK (0
C to 70
C)
BLANK (NORMAL)
L (LOW POWER)
K (SOJ)
T (TSOP-II)
L
16
16129L-01
5
6
7
8
9
10
11
12
Vcc
I/O0
I/O1
I/O2
I/O3
Vcc
I/O4
I/O5
I/O6
I/O7
NC
NC
WE
RAS
NC
A0
A1
A2
A3
Vcc
1
2
3
4
16129L-02
39
38
37
36
35
34
33
32
31
30
29
13
14
15
16
17
18
19
20
28
27
26
25
24
23
22
21
Vss
I/O15
I/O14
I/O13
I/O12
Vss
I/O11
I/O10
I/O9
I/O8
NC
LCAS
UCAS
OE
A8
A7
A6
A5
A4
Vss
5
6
7
8
9
10
Vcc
I/O1
I/O2
I/O3
I/O4
Vcc
I/O5
I/O6
I/O7
I/O8
NC
NC
WE
RAS
NC
A0
A1
A2
A3
Vcc
1
2
3
4
16129L-03
43
44
42
41
40
39
38
37
36
35
13
14
15
16
17
18
19
20
21
22
32
31
30
29
28
27
26
25
24
23
Vss
I/O16
I/O15
I/O14
I/O13
Vss
I/O12
I/O11
I/O10
I/O9
NC
LCAS
UCAS
OE
A8
A7
A6
A5
A4
Vss
Description
Pkg.
Pin Count
SOJ
K
40
TSOP-II
T
40/44L
40-Pin Plastic SOJ
PIN CONFIGURATION
Top View
40/44L-Pin Plastic TSOP-II
PIN CONFIGURATION
Top View
Pin Names
A
0
A
8
Address Inputs
RAS
Row Address Strobe
UCAS
Column Address Strobe/Upper Byte Control
LCAS
Column Address Strobe/Lower Byte Control
WE
Write Enable
OE
Output Enable
I/O
0
I/O
15
Data Input, Output
V
CC
+5V Supply
V
SS
0V Supply
NC
No Connect
MOSEL VITELIC
V53C16129L
3
V53C16129L Rev. 1.0 May 1997
Absolute Maximum Ratings*
Ambient Temperature
Under Bias ................................ 10
C to +80
C
Storage Temperature (plastic) ..... 55
C to +125
C
Voltage Relative to V
SS
.................1.0 V to +5.5 V
Data Output Current ..................................... 50 mA
Power Dissipation .......................................... 1.0 W
*Note:
Operation above Absolute Maximum Ratings can
adversely affect device reliability.
Capacitance*
T
A
= 25
C, V
CC
= 3.3V, f = 1 MHz
*Note:
Capacitance is sampled and not 100% tested
Symbol
Parameter Typ.
Max.
Unit
C
IN1
Address Input
3
4
pF
C
IN2
RAS, UCAS, LCAS,
WE, OE
4
5
pF
C
OUT
Data Input/Output
5
7
pF
Block Diagram
A 0
A 1
A7
A8
SENSE AMPLIFIERS
REFRESH
COUNTER
VCC
VSS
9
I/O 1
ADDRESS BUFFERS
AND PREDECODERS
ROW
DECODERS
MEMORY
ARRAY
1024 x 1024 x 16
COLUMN DECODERS
DATA I/O BUS
Y0Y8
256 x 16
512
X0 X7
I/O
BUFFER
I/O2
I/O3
I/O4
OE CLOCK
GENERATOR
WE CLOCK
GENERATOR
CAS CLOCK
GENERATOR
RAS CLOCK
GENERATOR
OE
WE
LCAS
RAS
16129L-04
I/O 5
I/O6
I/O7
I/O8
I/O 9
I/O10
I/O11
I/O12
I/O 13
I/O14
I/O15
I/O16
UCAS
128K x 16
4
V53C16129L Rev. 1.0 May 1997
MOSEL VITELIC
V53C16129L
DC and Operating Characteristics
(1-2)
T
A
= 0
C to 70
C, V
CC
= 3.3 V
0.3V, V
SS
= 0 V, unless otherwise specified.
Symbol
Parameter
Access
Time
V53C16129L
Unit
Test Conditions
Notes
Min.
Typ.
Max.
I
LI
Input Leakage Current
(any input pin)
10
10
A
V
SS
V
IN
V
CC
I
LO
Output Leakage Current
(for High-Z State)
10
10
A
V
SS
V
OUT
V
CC
RAS, CAS at V
IH
I
CC1
V
CC
Supply Current,
Operating
60
120
mA
t
RC
= t
RC
(min.)
1, 2
I
CC2
V
CC
Supply Current,
TTL Standby
2
mA
RAS, CAS at V
IH
,
other inputs
V
SS
I
CC3
V
CC
Supply Current,
RAS-Only Refresh
60
120
mA
t
RC
= t
RC
(min.)
2
I
CC4
V
CC
Supply Current,
Fast Page Mode Operation
60
110
mA
Minimum Cycle
1, 2
I
CC5
V
CC
Supply Current,
Standby, Output Enabled
2.0
mA
RAS = V
IH
, CAS = V
IL
,
other inputs
V
SS
1
I
CC6
V
CC
Supply Current,
CMOS Standby
2.0
mA
RAS
V
CC
0.2 V,
CAS
V
CC
0.2 V,
All other inputs
V
SS
V
IL
Input Low Voltage
1
0.8
V
3
V
IH
Input High Voltage
2.4
V
CC
+ 1
V
3
V
OL
Output Low Voltage
0.4
V
I
OL
= 2 mA
V
OH
Output High Voltage
2.4
V
I
OH
= 2 mA
MOSEL VITELIC
V53C16129L
5
V53C16129L Rev. 1.0 May 1997
AC Characteristics
T
A
= 0
C to 70
C, V
CC
= 3.3 V
0.3V, V
SS
= 0V unless otherwise noted
AC Test conditions, input pulse levels 0 to 3V
#
JEDEC
Symbol
Symbol
Parameter
60
Unit
Notes
Min.
Max.
1
t
RL1RH1
t
RAS
RAS Pulse Width
60
75K
ns
2
t
RL2RL2
t
RC
Read or Write Cycle Time
110
ns
3
t
RH2RL2
t
RP
RAS Precharge Time
40
ns
4
t
RL1CH1
t
CSH
CAS Hold Time
60
ns
5
t
CL1CH1
t
CAS
CAS Pulse Width
15
ns
6
t
RL1CL1
t
RCD
RAS to CAS Delay
20
45
ns
7
t
WH2CL2
t
RCS
Read Command Setup Time
0
ns
4
8
t
AVRL2
t
ASR
Row Address Setup Time
0
ns
9
t
RL1AX
t
RAH
Row Address Hold Time
10
ns
10
t
AVCL2
t
ASC
Column Address Setup Time
0
ns
11
t
CL1AX
t
CAH
Column Address Hold Time
10
ns
12
t
CL1RH1(R)
t
RSH (R)
RAS Hold Time (Read Cycle)
15
ns
13
t
CH2RL2
t
CRP
CAS to RAS Precharge Time
5
ns
14
t
CH2WX
t
RCH
Read Command Hold Time Referenced to CAS
ns
5
15
t
RH2WX
t
RRH
Read Command Hold Time Referenced to RAS
ns
5
16
t
OEL1RH2
t
ROH
RAS Hold Time Referenced to OE
10
ns
17
t
GL1QV
t
OAC
Access Time from OE
15
ns
12
18
t
CL1QV
t
CAC
Access Time from CAS
15
ns
6, 7, 14
19
t
RL1QV
t
RAC
Access Time from RAS
60
ns
6, 8, 9
20
t
AVQV
t
CAA
Access Time from Column Address
30
ns
6, 7, 10
21
t
CL1QX
t
LZ
OE or CAS to Low-Z Output
0
ns
16
22
t
CH2QZ
t
HZ
OE or CAS to High-Z Output
0
10
ns
16
23
t
RL1AX
t
AR
Column Address Hold Time from RAS
50
ns
24
t
RL1AV
t
RAD
RAS to Column Address Delay Time
15
30
ns
11
25
t
CL1RH1(W)
t
RSH (W)
RAS or CAS Hold Time in Write Cycle
15
ns
26
t
WL1CH1
t
CWL
Write Command to CAS Lead Time
15
ns
27
t
WL1CL2
t
WCS
Write Command Setup Time
0
ns
12, 13
28
t
CL1WH1
t
WCH
Write Command Hold Time
10
ns
29
t
WL1WH1
t
WP
Write Pulse Width
10
ns
30
t
RL1WH1
t
WCR
Write Command Hold Time from RAS
50
ns
31
t
WL1RH1
t
RWL
Write Command to RAS Lead Time
15
ns
32
t
DVWL2
t
DS
Data in Setup Time
0
ns
14
33
t
WL1DX
t
DH
Data in Hold Time
10
ns
14
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