MOSEL VITELIC
1
V53C318160A
3.3 VOLT 1M X 16 FAST PAGE MODE
CMOS DYNAMIC RAM
V53C318160A Rev. 1.4 March 1998
HIGH PERFORMANCE 50 60 70
Max. RAS Access Time, (t
RAC
) 50 ns 60 ns 70 ns
Max. Column Address Access Time, (t
CAA
) 25 ns 30 ns 35 ns
Min. Fast Page Mode Cycle Time, (t
PC
) 35 ns 40 ns 45 ns
Min. Read/Write Cycle Time, (t
RC
) 90 ns 104 ns 124 ns
Features
s
1M x 16-bit organization
s
Fast Page Mode for a sustained data rate
of 29 MHz
s
RAS access time: 50, 60, 70 ns
s
Dual CAS Inputs
s
Low power dissipation
s
Read-Modify-Write, RAS-Only Refresh,
CAS-Before-RAS Refresh, Hidden Refresh, and
Self Refresh.
s
Refresh Interval: 1024 cycles/16 ms
1024 cycles/256 ms (L-version)
s
Available in 42-pin 400 mil SOJ and 50/44-pin
400 mil TSOP-II
s
Single +3.3 V
0.3 V Power Supply
s
LVTTL Interface
Description
The V53C318160A is a 1048576 x 16 bit high-
performance CMOS dynamic random access mem-
ory. The V53C318160A offers Fast Page mode op-
eration. The V53C318160A has an symmetric
address, 10-bit row and 10-bit column.
All inputs are LVTTL compatible. Fast Page
Mode operation allows random access up to 1024 x
16 bits, within a page, with cycle times as short as
35 ns.
These features make the V53C318160A ideally
suited for a wide variety of high performance com-
puter systems and peripheral applications.
Device Usage Chart
Operating
Temperature
Range
Package Outline Access Time (ns) Power
Temperature
Mark
K T 50 60 70 Std. L
0
C to 70
C Blank
2
V53C318160A Rev. 1.4 March 1998
MOSEL VITELIC
V53C318160A
42-Pin Plastic SOJ
PIN CONFIGURATION
Top View
50/44-Pin Plastic TSOP-II
PIN CONFIGURATION
Top View
V
CC
I/O
1
I/O
2
I/O
3
I/O
4
V
CC
I/O
5
I/O
6
I/O
7
I/O
8
NC
NC
WE
RAS
NC
NC
A
0
A
1
A
2
A
3
V
CC
V
SS
I/O
16
I/O
15
I/O
14
I/O
13
V
SS
I/O
12
I/O
11
I/O
10
I/O
9
NC
LCAS
UCAS
OE
A
9
A
8
A
7
A
6
A
5
A
4
V
SS
5
6
7
8
9
10
11
12
1
2
3
4
40
39
38
37
36
35
34
33
32
31
30
29
13
14
15
16
17
18
19
20
28
27
26
25
24
23
22
311816500-02
42
21
41
V
CC
I/O
1
I/O
2
I/O
3
I/O
4
V
CC
I/O
5
I/O
6
I/O
7
I/O
8
NC
NC
NC
WE
RAS
NC
NC
A
0
A
1
A
2
A
3
V
CC
V
SS
I/O
16
I/O
15
I/O
14
I/O
13
V
SS
I/O
12
I/O
11
I/O
10
I/O
9
NC
NC
LCAS
UCAS
OE
A
9
A
8
A
7
A
6
A
5
A
4
V
SS
5
6
7
8
9
10
11
1
2
3
4
48
47
46
45
44
43
42
41
40
15
16
17
18
19
20
36
35
34
33
32
31
30
29
28
27
26
311816500-03
50
21
22
23
24
25
49
Description
Pkg.
Pin Count
SOJ
K
42
TSOP-II
T
50
Pin Names
A
0
A
9
Row, Column Address Inputs
RAS
Row Address Strobe
UCAS
Column Address Strobe/Upper Byte Control
LCAS
Column Address Strobe/Lower Byte Control
WE
Write Enable
OE
Output Enable
I/O
1
I/O
16
Data Input, Output
V
CC
+3.3V Supply
V
SS
0V Supply
NC
No Connect
3
V53C318160A Rev. 1.4 March 1998
MOSEL VITELIC
V53C318160A
Block Diagram
A 0
A 1
A8
A9
SENSE AMPLIFIERS
REFRESH
COUNTER
VCC
VSS
10
I/O 1
ADDRESS BUFFERS
AND PREDECODERS
ROW
DECODERS
MEMORY
ARRAY
1024 x 1024 x 16
COLUMN DECODERS
DATA I/O BUS
Y0Y9
1024 x 16
3118165A-04
1024
X0 X9
I/O
BUFFER
I/O2
I/O3
I/O4
OE CLOCK
GENERATOR
WE CLOCK
GENERATOR
CAS CLOCK
GENERATOR
RAS CLOCK
GENERATOR
OE
WE
LCAS
RAS
I/O 5
I/O6
I/O7
I/O8
I/O 9
I/O10
I/O11
I/O12
I/O 13
I/O14
I/O15
I/O16
UCAS
1024 x 16
Absolute Maximum Ratings*
Operating temperature range ..................0 to 70
C
Storage temperature range ............... -55 to 150
C
Soldering temperature ..................................260
C
Soldering time...................................................10 s
Input/output voltage .... -0.5 to min (V
CC
+0.5, 4.6) V
Power supply voltage ........................-0.5V to 4.6 V
Power dissipation .......................................... 1.0 W
Data out current (short circuit) ...................... 50 mA
*
Note:
Operation above Absolute Maximum Ratings can
adversely affect device reliability.
Capacitance*
T
A
= 25
C, V
CC
= 3.3 V
0.3 V, V
SS
= 0 V, f = 1 MHz
*
Note:
Capacitance is sampled and not 100% tested.
Symbol
Parameter
Min.
Max.
Unit
C
IN1
Address Input
--
5
pF
C
IN2
RAS, UCAS, LCAS,
WE, OE
--
7
pF
C
OUT
Data Input/Output
--
7
pF
4
V53C318160A Rev. 1.4 March 1998
MOSEL VITELIC
V53C318160A
DC and Operating Characteristics
(1-2)
T
A
= 0
C to 70
C, V
CC
= 3.3 V
0.3 V, V
SS
= 0 V, t
T
= 2ns, unless otherwise specified.
Symbol
Parameter
Access
Time
V53C318160A
Unit
Test Conditions
Notes
Min.
Typ.
Max.
I
LI
Input Leakage Current
(any input pin)
10
10
m
A
V
SS
V
IN
V
CC
+ 0.3V
1
I
LO
Output Leakage Current
(for High-Z State)
10
10
m
A
V
SS
V
OUT
V
CC
+ 0.3V
RAS, CAS at V
IH
1
I
CC1
V
CC
Supply Current,
Operating
50
200
mA
t
RC
= t
RC
(min.)
2, 3, 4
60
180
70
160
I
CC2
V
CC
Supply Current,
TTL Standby
2
mA
RAS, CAS at V
IH
other inputs
V
SS
I
CC3
V
CC
Supply Current,
RAS-Only Refresh
50
200
mA
t
RC
= t
RC
(min.)
2, 4
60
180
70
160
I
CC4
V
CC
Supply Current,
Fast Page Mode
Operation
50
55
mA
Minimum Cycle
2, 3, 4
60
50
70
45
I
CC5
V
CC
Supply Current,
CMOS Standby
1.0
mA
RAS
V
CC
0.2 V,
CAS
V
CC
0.2 V
1
I
CC6
Average Self Refresh Current
CBR cycle with t
RAS
> t
RASS
min.,
CAS held low, WE = V
CC
0.2V,
Address and D
IN
= V
CC
0.2V
or 0.2V
1.0
250
mA
m
A
L version
I
CC7
V
CC
Supply Current,
during CAS-before-RAS Refresh
50
200
mA
t
RC
= t
RC
(min)
2, 4
60
180
70
160
V
IL
Input Low Voltage
0.5
0.8
V
1
V
IH
Input High Voltage
2
V
CC
+0.5
V
1
V
OL
Output Low Voltage
0.4
V
I
OL
= 2 mA
1
V
OH
Output High Voltage
2.4
V
I
OH
= 2 mA
1
5
V53C318160A Rev. 1.4 March 1998
MOSEL VITELIC
V53C318160A
AC Characteristics
T
A
= 0
C to 70
C, V
CC
= 3.3 V
0.3 V, V
SS
= 0V, t
T
= 2ns unless otherwise noted
#
JEDEC
Symbol Symbol
Parameter
50
60
70
Unit
Notes
Min. Max. Min. Max. Min. Max.
1
t
RL1RH1
t
RAS
RAS Pulse Width
50
10K
60
10K
70
10K
ns
2
t
RL2RL2
t
RC
Read or Write Cycle Time
90
110
130
ns
3
t
RH2RL2
t
RP
RAS Precharge Time
30
40
50
ns
4
t
RL1CH1
t
CSH
CAS Hold Time
50
60
70
ns
5
t
CL1CH1
t
CAS
CAS Pulse Width
13
10K
15
10K
20
10K
ns
6
t
RL1CL1
t
RCD
RAS to CAS Delay
18
37
20
45
20
50
ns
7
t
WH2CL2
t
RCS
Read Command Setup Time
0
0
0
ns
8
t
AVRL2
t
ASR
Row Address Setup Time
0
0
0
ns
9
t
RL1AX
t
RAH
Row Address Hold Time
8
10
10
ns
10
t
AVCL2
t
ASC
Column Address Setup Time
0
0
0
ns
11
t
CL1AX
t
CAH
Column Address Hold Time
10
15
15
ns
12
t
CL1RH1(R)
t
RSH
RAS Hold Time
13
15
20
ns
13
t
CH2RL2
t
CRP
CAS to RAS Precharge Time
5
5
5
ns
14
t
CH2WX
t
RCH
Read Command Hold Time
Referenced to CAS
0
0
0
ns
9
15
t
RH2WX
t
RRH
Read Command Hold Time
Referenced to RAS
0
0
0
ns
9
16
t
CL1
t
COH
Output Hold after CAS LOW
5
5
5
ns
17
t
GL1QV
t
OAC
Access Time from OE
13
15
20
ns
18
t
CL1QV
t
CAC
Access Time from CAS
13
15
20
ns
7, 12
19
t
RL1QV
t
RAC
Access Time from RAS
50
60
70
ns
7, 12
20
t
AVQV
t
CAA
Access Time from Column Address
25
30
35
ns
7, 13
21
t
CL1QX
t
CLZ
CAS to Low-Z Output
0
0
0
ns
7
22
t
CH2QX
t
OFF
Output Buffer Turnoff Delay
0
13
0
15
0
20
ns
23
t
CL1QZ
t
DZC
Data to CAS Low Delay
0
0
0
ns
15
24
t
RL1AV
t
RAD
RAS to Column Address Delay Time
13
25
15
30
15
35
ns
25
t
GL2QZ
t
OEZ
Output Buffer Turnoff Delay from OE
0
13
0
15
0
17
ns
8
26
t
WL1CH1
t
CWL
Write Command to CAS Lead Time
13
15
20
ns
27
t
WL1CL2
t
WCS
Write Command Setup Time
0
0
0
ns
11
28
t
CL1WH1
t
WCH
Write Command Hold Time
8
10
10
ns
29
t
WL1WH1
t
WP
Write Pulse Width
8
10
10
ns
30
t
GL1QZ
t
DEO
Data to OE Delay
0
0
0
ns
15
31
t
WL1RH1
t
RWL
Write Command to RAS Lead Time
13
15
17
ns
32
t
DVWL2
t
DS
Data in Setup Time
0
0
0
ns
10
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