MOSEL VITELIC
1
V53C364165A
3.3 VOLT 4M X 16 EDO PAGE MODE
CMOS DYNAMIC RAM
V53C364165A Rev. 0.2 September 1998
V53C364165A
40
50
60
Max. RAS Access Time, (t
RAC
)
40 ns
50 ns
60 ns
Max. Column Address Access Time, (t
CAA
)
20 ns
25 ns
30 ns
Min. Extended Data Out Page Mode Cycle Time, (t
PC
)
16 ns
20 ns
25 ns
Min. Read/Write Cycle Time, (t
RC
)
69 ns
84 ns
104 ns
Features
s
4M x 16-bit organization
s
EDO Page Mode for a sustained data rate
of 63 MHz
s
RAS access time: 40, 50, 60 ns
s
Dual CAS Inputs
s
Low power dissipation
s
Read-Modify-Write, RAS-Only Refresh,
CAS-Before-RAS Refresh, Hidden Refresh
s
Refresh Interval: 8192 cycles/128 ms
s
Self refresh (L-version only)
s
Available in 50-pin 400 mil TSOP-II
s
Single +3.3 V
0.3 V Power Supply
s
LVTTL Interface
Description
The V53C364165A is a 4,194,304 x 16 bit high-
performance CMOS dynamic random access mem-
ory. The V53C364165A offers Page mode opera-
tion with Extended Data Output. The V53C364165A
has an symmetric address, 13-bit row and 9-bit col-
umn.
All inputs are TTL compatible. EDO Page Mode
operation allows random access up to 512 x 16 bits,
within a page, with cycle times as short as 16 ns.
These features make the V53C364165A ideally
suited for a wide variety of high performance
computer systems and peripheral applications.
Device Usage Chart
Operating
Temperature
Range
Package Outline
Access Time (ns)
Power
Temperature
Mark
T
40
50
60
Std.
L
0
C to 70
C
Blank
2
V53C364165A Rev. 0.2 September 1998
MOSEL VITELIC
V53C364165A
V
CC
I/O
1
I/O
2
I/O
3
I/O
4
V
CC
I/O
5
I/O
6
I/O
7
I/O
8
NC
V
CC
WE
RAS
NC
NC
NC
NC
A
0
A
1
A
2
A
3
A
4
A
5
V
CC
V
SS
I/O
16
I/O
15
I/O
14
I/O
13
V
SS
I/O
12
I/O
11
I/O
10
I/O
9
NC
V
SS
LCAS
UCAS
OE
NC
NC
A
12
A
11
A
10
A
9
A
8
A
7
A
6
V
SS
5
6
7
8
9
10
11
12
1
2
3
4
48
47
46
45
44
43
42
41
40
39
38
37
13
14
15
16
17
18
19
20
21
22
23
24
25
36
35
34
33
32
31
30
29
28
27
26
316516500-02
50
49
Absolute Maximum Ratings*
Operating temperature range ..................0 to 70
C
Storage temperature range ............... -55 to 150
C
Soldering temperature ..................................260
C
Soldering time...................................................10 s
Input/output voltage .... -0.5 to min (V
CC
+0.5, 4.6) V
Power supply voltage ........................-0.5V to 4.6 V
Power dissipation .......................................... 1.0 W
Data out current (short circuit) ...................... 50 mA
*
Note:
Operation above Absolute Maximum Ratings can
adversely affect device reliability.
Capacitance*
T
A
= 25
C, V
CC
= 3.3 V
0.3 V, V
SS
= 0 V, f = 1 Mhz
*
Note:
Capacitance is sampled and not 100% tested.
Symbol
Parameter Min.
Max.
Unit
C
IN1
Address Input
--
5
pF
C
IN2
RAS, UCAS, LCAS,
WE, OE
--
7
pF
C
OUT
Data Input/Output
--
7
pF
50 Pin Plastic TSOP-II
PIN CONFIGURATION
Top View
Description
Pkg.
Pin Count
TSOP-II
T
50
Pin Names
A
0
A
12
Row, Column Address Inputs
RAS
Row Address Strobe
UCAS
Column Address Strobe/Upper Byte Control
LCAS
Column Address Strobe/Lower Byte Control
WE
Write Enable
OE
Output Enable
I/O
1
I/O
16
Data Input, Output
V
CC
+3.3V Supply
V
SS
0V Supply
NC
No Connect
3
V53C364165A Rev. 0.2 September 1998
MOSEL VITELIC
V53C364165A
Block Diagram
No. 2 Clock
Generator
Data In
Buffer
Data Out
Buffer
Column
Address
Buffers (9)
Refresh
Controller
Row
Decoder
Refresh
Counter (13)
No. 1 Clock
Generator
Row
Address
Buffers (13)
9
16
I/O1 I/O2
I/O16
16
OE
13
13
13
16
8192
512
x16
Memory Array
8192 x 512 x 16
Sense Amplifier
I/O Gating
316516500-03
Column
Decoder
A0
UCAS
WE
LCAS
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
RAS
9
4M x 16
4
V53C364165A Rev. 0.2 September 1998
MOSEL VITELIC
V53C364165A
DC and Operating Characteristics
(1-2)
T
A
= 0
C to 70
C, V
CC
= 3.3 V
0.3 V, V
SS
= 0 V, unless otherwise specified.
Symbol
Parameter
Access
Time
V53C364165A
Unit
Test Conditions
Notes
Min.
Typ.
Max.
I
LI
Input Leakage Current
(any input pin)
2
2
m
A
V
SS
V
IN
V
CC
I
LO
Output Leakage Current
(for High-Z State)
2
2
m
A
V
SS
V
OUT
V
CC
RAS, CAS at V
IH
I
CC1
V
CC
Supply Current,
Operating
40
125
mA
t
RC
= t
RC
(min.)
2, 3, 4
50
100
60
84
I
CC2
V
CC
Supply Current,
TTL Standby
1
mA
RAS, CAS at V
IH
other inputs
V
SS
I
CC3
V
CC
Supply Current,
RAS-Only Refresh
40
125
mA
t
RC
= t
RC
(min.)
2, 4
50
100
60
84
I
CC4
V
CC
Supply Current,
EDO Page Mode
Operation
40
140
mA
Minimum Cycle
2, 3, 4
50
105
60
85
I
CC5
V
CC
Supply Current,
CMOS Standby
120
m
A
RAS
V
CC
0.2 V,
CAS
V
CC
0.2 V
I
CC5
V
CC
Supply Current,
CMOS Standby (L-Version)
100
m
A
RAS
V
CC
0.2 V,
CAS
V
CC
0.2 V
I
CC6
Average Self Refresh Current
CBR cycle with t
RAS
> t
RASS
min.,
(L-version only)
CAS held low, WE = V
CC
0.2V,
Address and D
IN
= V
CC
0.2V
or 0.2V
400
m
A
I
CC7
V
CC
Supply Current,
during CAS-before-RAS Refresh
40
170
mA
2, 4
50
140
60
115
V
IL
Input Low Voltage
0.3
0.8
V
1
V
IH
Input High Voltage
2.0
V
CC
+0.3
V
1
V
OL
Output Low Voltage (LVTTL)
0.4
V
I
OL
= 2 mA
1
V
OL
Output Low Voltage (LVCMOS)
0.2
V
I
OL
= 100
m
A
1
V
OH
Output High Voltage (LVTTL)
2.4
V
I
OH
= 2 mA
V
OH
Output High Voltage (LVCMOS)
V
CC
0.2
V
I
OH
= 100
m
A
5
V53C364165A Rev. 0.2 September 1998
MOSEL VITELIC
V53C364165A
Truth Table
Function
RAS
LCAS
UCAS
WE
OE
Row
Addr
Col
Addr
I/O
1
I/O
16
Standby
H
H
X
H
X
X
X
X
X
High Impedance
Read: Word
L
L
H
H
L
ROW
COL
Data Out
Read: Lower Byte
L
L
H
H
L
ROW
COL
Lower Byte: Data Out
Upper Byte: High-Z
Read: Upper Byte
L
H
L
H
L
ROW
COL
Lower Byte: High-Z
Upper Byte: Data Out
Write: Word (Early Write)
L
L
L
L
X
ROW
COL
Data In
Write: Lower Byte (Early Write)
L
L
H
L
X
ROW
COL
Lower Byte: Data Out
Upper Byte: High-Z
Write: Upper Byte (Early Write)
L
H
L
L
X
ROW
COL
Lower Byte: High-Z
Upper Byte: Data Out
Read-Modify-Write
L
L
L
H
L
L
H
ROW
COL
Data Out, Data In
EDO Page Mode Read
1st Cycle
L
H
L
H
L
H
L
ROW
COL
Data Out
2nd Cycle
L
H
L
H
L
H
L
N/A
COL
Data Out
EDO Page Mode Early
Write (Word)
1st Cycle
L
H
L
H
L
L
X
ROW
COL
Data In
2nd Cycle
L
H
L
H
L
L
X
N/A
COL
Data In
EDO Page Mode RMW
1st Cycle
L
H
L
H
L
H
L
L
H
ROW
COL
Data Out, Data In
2nd Cycle
L
H
L
H
L
H
L
L
H
N/A
COL
Data Out, Data In
RAS only refresh
L
H
H
X
X
ROW
N/A
High Impedance
CAS-before-RAS refresh
H
L
L
L
H
X
X
N/A
High Impedance
Test Mode Entry
H
L
L
L
L
X
X
N/A
High Impedance
Hidden Refresh (Read)
L
H
L
L
L
H
L
ROW
COL
Data Out
Hidden Refresh (Write)
L
H
L
L
L
L
X
ROW
COL
Data In
Self Refresh (L-Version)
H
L
L
H
X
X
X
X
High Impedance
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