MOSEL VITELIC
1
V53C364405A
3.3 VOLT 16M X 4 EDO PAGE MODE
CMOS DYNAMIC RAM
V53C364405A Rev. 1.2 June 1998
V53C364405A
40
50
60
Max. RAS Access Time, (t
RAC
)
40 ns
50 ns
60 ns
Max. Column Address Access Time, (t
CAA
)
20 ns
25 ns
30 ns
Min. Extended Data Out Page Mode Cycle Time, (t
PC
)
16 ns
20 ns
25 ns
Min. Read/Write Cycle Time, (t
RC
)
69 ns
84 ns
104 ns
s
16M x 4-bit organization
s
EDO Page Mode for a sustained data rate
of 63 MHz
s
RAS access time: 40, 50, 60 ns
s
Low power dissipation
s
Read-Modify-Write, RAS-Only Refresh,
CAS-Before-RAS Refresh, Hidden Refresh
s
Self Refresh (L-version only)
s
Refresh Interval: 8192 cycles/128 ms
s
Available in 32-pin 400 mil SOJ,
and 32-pin 400 mil TSOP-II
s
Single +3.3 V
0.3 V Power Supply
s
LV-TTL Interface
Description
The V53C364405A is a 16,777,216 x 4 bit high-
performance CMOS dynamic random access mem-
ory. The V53C364405A offers Page mode opera-
tion with Extended Data Output. The V53C364405A
has an address, 13-bit row and 11-bit column.
All inputs are LV-TTL compatible. EDO Page
Mode operation allows random access up to 2048 x
4 bits, within a page, with cycle times as short as 16
ns.
These features make the V53C364405A ideally
suited for a wide variety of high performance
computer systems and peripheral applications.
Device Usage Chart
Operating
Temperature
Range
Package Outline
Access Time (ns)
Power
Temperature
Mark
K
T
40
50
60
Std.
L
0
C to 70
C
Blank
2
V53C364405A Rev. 1.2 June 1998
MOSEL VITELIC
V53C364405A
V
CC
I/O
1
I/O
2
NC
NC
NC
NC
WE
RAS
A
0
A
1
A
2
A
3
A
4
A
5
V
CC
V
SS
I/O
4
I/O
3
NC
NC
NC
CAS
OE
A
12
A
11
A
10
A
9
A
8
A
7
A
6
V
SS
5
6
7
8
9
10
11
12
1
2
3
4
30
29
28
27
26
25
24
23
22
21
20
19
13
14
15
16
18
17
6540500 02
32
31
Pin Names
A
0
A
12
Row, Column Address Inputs
RAS
Row Address Strobe
CAS
Column Address Strobe
WE
Write Enable
OE
Output Enable
I/O
1
I/O
4
Data Input, Output
V
CC
+3.3V Supply
V
SS
0V Supply
NC
No Connect
Description
Pkg.
Pin Count
SOJ
K
32
TSOP-II
T
32
32 Pin Plastic SOJ /TSOP-II
PIN CONFIGURATION
Top View
MOSEL VITELIC
V53C364405A
3
V53C364405A Rev. 1.2 June 1998
No. 2 Clock
Generator
Data In
Buffer
Data Out
Buffer
Column
Address
Buffers (11)
Refresh
Controller
Row
Decoder
Refresh
Counter (13)
No. 1 Clock
Generator
Row
Address
Buffers (13)
11
4
I/O1 I/O2 I/O3 I/O4
4
OE
13
13
13
4
8192
2048
x4
Memory Array
8192 x 2048 x 4
Sense Amplifier
I/O Gating
Column
Decoder
A0
CAS
WE
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
RAS
11
Absolute Maximum Ratings*
Operating temperature range ..................0 to 70
C
Storage temperature range ............... -55 to 150
C
Soldering temperature ..................................260
C
Soldering time...................................................10 s
Input/output voltage .... -0.5 to min (V
CC
+0.5, 4.6) V
Power supply voltage ........................-0.5V to 4.6 V
Power dissipation .......................................... 1.0 W
Data out current (short circuit) ...................... 50 mA
*
Note:
Operation above Absolute Maximum Ratings can
adversely affect device reliability.
Capacitance*
T
A
= 25
C, V
CC
= 3.3 V
0.3 V, V
SS
= 0 V, f = 1 Mhz
*
Note:
Capacitance is sampled and not 100% tested.
Symbol
Parameter Min.
Max.
Unit
C
IN1
Address Input
--
5
pF
C
IN2
RAS, CAS, WE, OE
--
7
pF
C
OUT
Data Input/Output
--
7
pF
Block Diagram
16M x 4
4
V53C364405A Rev. 1.2 June 1998
MOSEL VITELIC
V53C364405A
DC and Operating Characteristics
(1, 2)
T
A
= 0
C to 70
C, V
CC
= 3.3 V
0.3 V, V
SS
= 0 V, unless otherwise specified.
Symbol
Parameter
Access
Time
V53C364405A
Unit
Test Conditions
Notes
Min.
Typ.
Max.
I
LI
Input Leakage Current
(any input pin)
2
2
m
A
V
SS
V
IN
V
CC
I
LO
Output Leakage Current
(for High-Z State)
2
2
m
A
V
SS
V
OUT
V
CC
RAS, CAS at V
IH
I
CC1
V
CC
Supply Current,
Operating
40
125
mA
t
RC
= t
RC
(min.)
2, 3, 4
50
100
60
84
I
CC2
V
CC
Supply Current,
TTL Standby
1
mA
RAS, CAS at V
IH
other inputs
V
SS
I
CC3
V
CC
Supply Current,
RAS-Only Refresh
40
125
mA
t
RC
= t
RC
(min.)
2, 4
50
100
60
84
I
CC4
V
CC
Supply Current,
EDO Page Mode
Operation
40
140
mA
Minimum Cycle
2, 3, 4
50
105
60
85
I
CC5
V
CC
Supply Current,
CMOS Standby
500
m
A
RAS
V
CC
0.2 V,
CAS
V
CC
0.2 V
I
CC5
V
CC
Supply Current,
CMOS Standby
(L-Version)
120
m
A
RAS
V
CC
0.2 V,
CAS
V
CC
0.2 V
I
CC6
Average Self Refresh
Current CBR cycle with
t
RAS
> t
RASS
min.,
(L-version)
CAS held low, WE =
V
CC
0.2V, Address
and D
IN
= V
CC
0.2V
or 0.2V
400
m
A
I
CC7
V
CC
Supply Current,
during CAS-before-RAS
Refresh
40
170
mA
2, 4
50
140
60
115
V
IL
Input Low Voltage
0.3
0.8
V
1
V
IH
Input High Voltage
2.0
V
CC
+0.3 V
1
V
OL
Output Low Voltage
0.4
V
I
OL
= 2 mA
1
V
OH
Output High Voltage
2.4
V
I
OH
= 2 mA
1
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