MOSEL VITELIC
1
V53C365805A
3.3 VOLT 8M X 8 EDO PAGE MODE
CMOS DYNAMIC RAM
V53C365805A Rev. 1.0 January 1998
V53C365805A
40
50
60
Max. RAS Access Time, (t
RAC
)
40 ns
50 ns
60 ns
Max. Column Address Access Time, (t
CAA
)
20 ns
25 ns
30 ns
Min. EDO Page Mode Cycle Time, (t
PC
)
16 ns
20 ns
25 ns
Min. Read/Write Cycle Time, (t
RC
)
69 ns
84 ns
104 ns
Features
s
8M x 8-bit organization
s
EDO Page Mode for a sustained data rate
of 63 MHz
s
RAS access time: 40, 50, 60 ns
s
Low power dissipation
s
Read-Modify-Write, RAS-Only Refresh,
CAS-Before-RAS Refresh, Hidden Refresh
s
Refresh Interval: 4096 cycles/64 ms
s
Available in 32-pin 400 mil SOJ,
and 32-pin 400 mil TSOP-II
s
Single +3.3 V
0.3 V Power Supply
s
TTL Interface
Description
The V53C365805A is a 8,388,608 x 8 bit high-
performance CMOS dynamic random access mem-
ory. The V53C365805A offers Page mode opera-
tion. The V53C365805A has an asymmetric
address, 12-bit row and 11-bit column.
All inputs are TTL compatible. Page Mode opera-
tion allows random access up to 2048 x 8 bits, with-
in a page, with cycle times as short as 16 ns.
These features make the V53C365805A ideally
suited for a wide variety of high performance
computer systems and peripheral applications.
Device Usage Chart
Operating
Temperature
Range
Package Outline
Access Time (ns)
Power
Temperature
Mark
K
T
40
50
60
Std.
0
C to 70
C
Blank
2
V53C365805A Rev. 1.0 January 1998
MOSEL VITELIC
V53C365805A
V
CC
I/O
1
I/O
2
I/O
3
I/O
4
NC
V
CC
WE
RAS
A
0
A
1
A
2
A
3
A
4
A
5
V
CC
V
SS
I/O
8
I/O
7
I/O
6
I/O
5
V
SS
CAS
OE
NC
A
11
A
10
A
9
A
8
A
7
A
6
V
SS
5
6
7
8
9
10
11
12
1
2
3
4
30
29
28
27
26
25
24
23
22
21
20
19
13
14
15
16
18
17
316580500-02
32
31
Pin Names
A
0
A
11
Row, Column Address Inputs
RAS
Row Address Strobe
CAS
Column Address Strobe
WE
Write Enable
OE
Output Enable
I/O
1
I/O
8
Data Input, Output
V
CC
+3.3V Supply
V
SS
0V Supply
NC
No Connect
32 Pin Plastic SOJ /TSOP-II
PIN CONFIGURATION
Top View
MOSEL VITELIC
V53C365805A
3
V53C365805A Rev. 1.0 January 1998
No. 2 Clock
Generator
Data In
Buffer
Data Out
Buffer
Column
Address
Buffers (11)
Refresh
Controller
Row
Decoder
Refresh
Counter (12)
No. 1 Clock
Generator
Row
Address
Buffers (12)
11
8
I/O1 I/O2
I/O8
8
OE
12
12
12
8
4096
2048
x8
Memory Array
4096 x 2048 x 8
Sense Amplifier
I/O Gating
Column
Decoder
A0
CAS
WE
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
RAS
11
316580500-03
Absolute Maximum Ratings*
Operating temperature range ..................0 to 70
C
Storage temperature range ............... -55 to 150
C
Soldering temperature ..................................260
C
Soldering time...................................................10 s
Input/output voltage .... -0.5 to min (V
CC
+0.5, 4.6) V
Power supply voltage ........................-0.5V to 4.6 V
Power dissipation .......................................... 1.0 W
Data out current (short circuit) ...................... 50 mA
*
Note:
Operation above Absolute Maximum Ratings can
adversely affect device reliability.
Capacitance*
T
A
= 25
C, V
CC
= 3.3 V
0.3 V, V
SS
= 0 V, f = 1 Mhz
*
Note:
Capacitance is sampled and not 100% tested.
Symbol
Parameter Min.
Max.
Unit
C
IN1
Address Input
--
5
pF
C
IN2
RAS, CAS, WE, OE
--
7
pF
C
OUT
Data Input/Output
--
7
pF
Block Diagram
8M x 8
4
V53C365805A Rev. 1.0 January 1998
MOSEL VITELIC
V53C365805A
DC and Operating Characteristics
(1, 2)
T
A
= 0
C to 70
C, V
CC
= 3.3 V
0.3 V, V
SS
= 0 V, unless otherwise specified.
Symbol Parameter
Access
Time
V53C365805A
Unit Test Conditions Notes
Min. Typ. Max.
I
LI
Input Leakage Current
(any input pin)
2 2
A
V
SS
V
IN
V
CC
I
LO
Output Leakage Current
(for High-Z State)
2 2
A
V
SS
V
OUT
V
CC
RAS, CAS at V
IH
I
CC1
V
CC
Supply Current,
Operating
40 155 mA t
RC
= t
RC
(min.) 2, 3, 4
50 130
60 105
I
CC2
V
CC
Supply Current,
TTL Standby
2 mA RAS, CAS at V
IH
other inputs
V
SS
I
CC3
V
CC
Supply Current,
RAS-Only Refresh
40 155 mA t
RC
= t
RC
(min.) 2, 4
50 130
60 105
I
CC4
V
CC
Supply Current,
EDO Page Mode
Operation
40 70 mA Minimum Cycle 2, 3, 4
50 60
60 50
I
CC5
V
CC
Supply Current,
CMOS Standby
500
A RAS
V
CC
0.2 V,
CAS
V
CC
0.2 V
I
CC6
V
CC
Supply Current,
during CAS-before-RAS Refresh
40 155 mA 2, 4
50 130
60 105
V
IL
Input Low Voltage 0.3 0.8 V 1
V
IH
Input High Voltage 2.0 V
CC
+0.3 V 1
V
OL
Output Low Voltage (LVTTL) 0.4 V I
OL
= 2 mA 1
V
OH
Output High Voltage (LVTTL) 2.4 V I
OH
= 2 mA 1
V
OL
Output Low Voltage (LVCMOS) 0.2 V I
OL
= 100
A
1
V
OH
Output High Voltage (LVCMOS) V
CC
0.2 V I
OH
= 100
A
1
5
V53C365805A Rev. 1.0 January 1998
MOSEL VITELIC
V53C365805A
Truth Table
FUNCTION
RAS
CAS
WE
OE
ROW
ADDR
COL
ADDR
I/O1-I/O4
Standby
H
H
X
X
X
X
X
High Impedance
Read
L
L
H
L
ROW
COL
Data Out
Early-Write
L
L
L
X
ROW
COL
Data In
Delayed-Write
L L
H
L
H
ROW
COL
Data In
Read-Modify-Write
L
L
H
L
L
H
ROW
COL
Data Out, Data In
EDO Page Mode Read
1st Cycle
L
H
L
H
L
ROW
COL
Data Out
2nd Cycle
L
H
L
H
L
N/A
COL
Data Out
EDO Page Mode Early Write
1st Cycle
L
H
L
L
X
ROW
COL
Data In
2nd Cycle
L
H
L
L
X
N/A
COL
Data In
EDO Page Mode RMW
1st Cycle
L
H
L
H
L
L
H
ROW
COL
Data Out, Data In
2nd Cycle
L
H
L
H
L
L
H
N/A
COL
Data Out, Data In
RAS only refresh
L
H
X
X
ROW
N/A
High Impedance
CAS-before-RAS refresh
H
L
L
H
X
X
N/A
High Impedance
Test Mode Entry
H
L
L
L
X
X
N/A
High Impedance
Hidden Refresh
READ
L
H
L
L
H
L
ROW
COL
Data Out
WRITE
L
H
L
L
L
X
ROW
COL
Data In
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