MOSEL VITELIC
1
V53C664H
64K X 16 FAST PAGE MODE
BYTE WRITE CMOS DYNAMIC RAM
PRELIMINARY
V53C664H Rev. 1.5 February 1998
HIGH PERFORMANCE
30
35
40
45
50
Max. RAS Access Time, (t
RAC
)
30 ns
35 ns
40 ns
45 ns
50 ns
Max. Column Address Access Time, (t
CAA
)
16 ns
18 ns
20 ns
22 ns
24 ns
Min. Fast Page Mode Cycle Time, (t
PC
)
19 ns
21 ns
23 ns
25 ns
28 ns
Min. Read/Write Cycle Time, (t
RC
)
65 ns
70 ns
75 ns
80 ns
90 ns
Features
s
64K by 16-bit organization
s
Fast Page Mode for a sustained data rate
of 53 MHz
s
RAS Access time: 30, 35, 40, 45, 50 ns
s
Dual WE Inputs
s
Low power dissipation
s
Read-Modify-Write, RAS-Only Refresh,
CAS-Before-RAS refresh
s
Refresh Interval: 256 cycles/4ms
s
Available in 40-pin 400 mil SOJ and 40/44L-pin
400 mil TSOP-II packages
s
Single +5V
10% Power Supply
s
TTL Interface
Description
The V53C664H is a high speed 65,536 x 16 bit
high performance CMOS dynamic random access
memory. The V53C664H offers a combination of
unique features including: Fast Page Mode opera-
tion for sustained high bandwidth with Page Mode
cycle times as short as 19ns. All inputs are TTL
compatible. Input and output capacitance is signifi-
cantly lowered to increase performance and mini-
mize loading.
The addition of Byte Write control, of upper and
lower byte, makes the V53C664H ideally suited for
use in 16- and 32-bit wide data bus systems.
Device Usage Chart
Operating
Temperature
Range
Package Outline
Access Time (ns)
Power
Temperature
Mark
K
T
30
35
40
45
50
Std.
0
C to 70
C
Blank
2
V53C664H Rev. 1.5 February 1998
MOSEL VITELIC
V53C664H
5
6
7
8
9
10
Vcc
I/O1
I/O2
I/O3
I/O4
I/O5
I/O6
I/O7
I/O8
NC
Vcc
UWE
LWE
RAS
A0
A1
A2
A3
A4
Vcc
1
2
3
4
664H-03
43
44
42
41
40
39
38
37
36
35
13
14
15
16
17
18
19
20
21
22
32
31
30
29
28
27
26
25
24
23
Vss
I/O16
I/O15
I/O14
I/O13
I/O12
I/O11
I/O10
I/O9
NC
Vss
CAS
OE
NC
NC
NC
A7
A6
A5
Vss
5
6
7
8
9
10
11
12
Vcc
I/O1
I/O2
I/O3
I/O4
I/O5
I/O6
I/O7
I/O8
NC
Vcc
UWE
LWE
RAS
A0
A1
A2
A3
A4
Vcc
1
2
3
4
664H-02
39
40
38
37
36
35
34
33
32
31
30
29
13
14
15
16
17
18
19
20
28
27
26
25
24
23
22
21
Vss
I/O16
I/O15
I/O14
I/O13
I/O12
I/O11
I/O10
I/O9
NC
Vss
CAS
OE
NC
NC
NC
A7
A6
A5
Vss
Pin Names
Symbol
Name
A0A7
Address Inputs
RAS
Row Address Strobe
CAS
Column Address Strobe
UWE
Read/Upper Byte Write Input
LWE
Read/Lower Byte Write Input
OE
Output Enable
I/O1I/O16
Data Input/Output
V
CC
+5V Supply
V
SS
0V Supply
NC
No Connect
40-Pin Plastic SOJ
PIN CONFIGURATION
Top View
40/44L-Pin Plastic TSOP-II
PIN CONFIGURATION
Top View
MOSEL VITELIC
V53C664H
3
V53C664H Rev. 1.5 February 1998
Absolute Maximum Ratings*
Ambient Temperature
Under Bias .................................. 10
C to +80
C
Storage Temperature (plastic) ..... 55
C to +125
C
Voltage Relative to V
SS
.................... 1.0 to +7.0 V
Data Out Current .......................................... 50 mA
Power Dissipation .......................................... 1.0 W
*Note:
Operation above Absolute Maximum Ratings can ad-
versely affect device reliability.
Capacitance*
V
CC
= 5V
10%, V
SS
= 0V
*Note:
Capacitance is sampled and not 100% tested
Symbol
Parameter
Min.
Max.
Unit
C
IN1
Address Input
(A0A7)
3
4
pF
C
IN2
Address Input (RAS, CAS,
UWE, LWE, OE)
4
5
pF
C
OUT
Data Input/Output
(I/O1I/O16)
5
7
pF
Block Diagam
COLUMN
ADDRESS
BUFFER (8)
8
664H-04
REFRESH
CONTROLLER
REFRESH
COUNTER (8)
ROW
ADDRESS
BUFFER (8)
8
8
A
0
A
1
A
2
A
3
A
4
A
5
A
6
A
7
NO. 1 CLOCK
GENERATOR
NO. 2 CLOCK
GENERATOR
UWE
LWE
CAS
RAS
8
8
R
O
W
DECODER
256
MEMORY
ARRAY
256 x 256 x 16
COLUMN
DECODER
SENSE AMP.
I/O GATE
256 x 16
16
DATA OUT
BUFFER
DATA IN
BUFFER
V
CC
V
SS
16
16
16
16
OE
I/O
1
CAS
I/O
2
I/O
3
I/O
4
I/O
5
I/O
6
I/O
7
I/O
8
I/O
9
I/O
10
I/O
11
I/O
12
I/O
13
I/O
14
I/O
15
I/O
16
4
V53C664H Rev. 1.5 February 1998
MOSEL VITELIC
V53C664H
DC and Operating Characteristics
(1-2)
T
A
= 0
C to 70
C, V
CC
= 5 V
10%, V
SS
= 0 V, unless otherwise specified.
Symbol
Parameter
Access
Time
V53C664H
Unit
Test Conditions
Notes
Min.
Typ.
Max.
I
LI
Input Leakage Current
(any input pin)
10
10
A
V
SS
V
IN
V
CC
I
LO
Output Leakage Current
(for High-Z State)
10
10
A
V
SS
V
OUT
V
CC
RAS, CAS at V
IH
I
CC1
V
CC
Supply Current,
Operating
30
200
mA
t
RC
= t
RC
(min.)
1, 2
35
190
40
180
45
170
50
160
I
CC2
V
CC
Supply Current,
TTL Standby
2
mA
RAS, CAS at V
IH
,
other inputs
V
SS
I
CC3
V
CC
Supply Current,
RAS-Only Refresh
30
200
mA
t
RC
= t
RC
(min.)
2
35
190
40
180
45
170
50
160
I
CC4
V
CC
Supply Current,
Fast Page Mode Operation
30
190
mA
Minimum Cycle
1, 2
35
180
40
170
45
160
50
150
I
CC5
V
CC
Supply Current,
Standby Output Enable
other inputs
V
SS
2
mA
RAS = V
IH
CAS = V
IL
1
I
CC6
V
CC
Supply Current,
CMOS Standby
1
mA
RAS
V
CC
0.2 V,
CAS
V
CC
0.2 V,
All other inputs
V
SS
V
CC
Supply Voltage
4.5
5.0
5.5
V
V
IL
Input Low Voltage
1
0.8
V
3
V
IH
Input High Voltage
2.4
V
CC
+ 1
V
3
V
OL
Output Low Voltage
0.4
V
I
OL
= 4.2 mA
V
OH
Output High Voltage
2.4
V
I
OH
= 5 mA
5
V53C664H Rev. 1.5 February 1998
MOSEL VITELIC
V53C664H
AC Characteristics
T
A
= 0
C to 70
C, V
CC
= 5 V
10%, V
SS
= 0V unless otherwise noted
AC Test conditions, input pulse levels 0 to 3V
#
Symbol
Parameter
30
35
40
45
50
Unit Notes
Min.
Max.
Min.
Max.
Min.
Max.
Min.
Max.
Min.
Max.
1
t
RAS
RAS Pulse Width
30
75K
35
75K
40
75K
45
75K
50
75K
ns
2
t
RC
Read or Write Cycle Time
65
70
75
80
90
ns
3
t
RP
RAS Precharge Time
25
25
25
25
30
ns
4
t
CSH
CAS Hold Time
30
35
40
45
50
ns
5
t
CAS
CAS Pulse Width
5
6
7
8
9
ns
6
t
RCD
RAS to CAS Delay
15
20
16
24
17
28
18
32
19
36
ns
7
t
RCS
Read Command Setup Time
0
0
0
0
0
ns
4
8
t
ASR
Row Address Setup Time
0
0
0
0
0
ns
9
t
RAH
Row Address Hold Time
5
6
7
8
9
ns
10
t
ASC
Column Address Setup Time
0
0
0
0
0
ns
11
t
CAH
Column Address Hold Time
5
5
5
6
7
ns
12
t
RSH (R)
RAS Hold Time (Read Cycle)
10
10
10
10
10
ns
13
t
CRP
CAS to RAS Precharge Time
5
5
5
5
5
ns
14
t
RCH
Read Command Hold Time
Referenced to CAS
0
0
0
0
0
ns
5
15
t
RRH
Read Command Hold Time
Referenced to RAS
0
0
0
0
0
ns
5
16
t
ROH
RAS Hold Time
Referenced to OE
6
7
8
9
10
ns
17
t
OAC
Access Time from OE
10
11
12
13
14
ns
12
18
t
CAC
Access Time from CAS
10
11
12
13
14
ns
6,7,14
19
t
RAC
Access Time from RAS
30
35
40
45
50
ns
6, 8, 9
20
t
CAA
Access Time from Column
Address
16
18
20
22
24
ns
6,7,10
21
t
LZ
OE or CAS to Low-Z Output
0
0
0
0
0
ns
16
22
t
HZ
OE or CAS to High-Z Output
0
5
0
6
0
6
0
7
0
8
ns
16
23
t
AR
Column Address Hold Time from
RAS
26
28
30
35
40
ns
24
t
RAD
RAS to Column Address
Delay Time
10
14
11
17
12
20
13
23
14
26
ns
11
25
t
RSH (W)
RAS or CAS Hold Time in
Write Cycle
10
10
10
10
10
ns
26
t
CWL
Write Command to CAS
Lead Time
10
11
12
13
14
ns
27
t
WCS
Write Command Setup Time
0
0
0
0
0
ns
12, 13
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