MOSEL VITELIC
1
V53C8129H
ULTRA-HIGH PERFORMANCE,
128K X 8 EDO PAGE MODE
CMOS DYNAMIC RAM
PRELIMINARY
V53C8129H Rev. 1.3 July 1997
HIGH PERFORMANCE
35
40
45
50
Max. RAS Access Time, (t
RAC
)
35 ns
40 ns
45 ns
50 ns
Max. Column Address Access Time, (t
CAA
)
18 ns
20 ns
22 ns
24 ns
Min. Fast Page Mode With EDO Cycle Time, (t
PC
)
14 ns
15 ns
17 ns
19 ns
Min. Read/Write Cycle Time, (t
RC
)
70 ns
75 ns
80 ns
90 ns
Features
s
128K x 8-bit organization
s
RAS access time: 35, 40, 45, 50 ns
s
EDO Page Mode supports sustained I/O data
rates up to 71.5 MHz
s
Low power dissipation
V53C8129H-50
-- Operating Current: 135 mA max
-- TTL Standby Current: 2.0 mA max
s
Low CMOS Standby Current: 1.0 mA max
s
Read-Modify-Write, RAS-Only Refresh,
CAS-Before-RAS Refresh capability
s
Refresh Interval: 512 cycles/8 ms
s
Available in 26/24 pin 300 mil SOJ package
Description
The V53C8129H is a high speed 131,072 x 8 bit
CMOS dynamic random access memory. The
V53C8129H offers a combination of features: EDO
Page Mode for high data bandwidth, fast usable
speed, CMOS standby current.
All inputs and outputs are TTL compatible. Input
and output capacitances are significantly lowered to
allow increased system performance. Page Mode
with extended data out operation allows random ac-
cess of up to 256 columns (x8) bits within a row with
cycle times as short as 14 ns. Because of static cir-
cuitry, the CAS clock is not in the critical timing path.
The flow-through column address latches allow ad-
dress pipelining while relaxing many critical system
timing requirements for fast usable speed. These
features make the V53C8129H ideally suited for
graphics, digital signal processing and high perfor-
mance peripherals.
Device Usage Chart
Operating
Temperature
Range
Package Outline
Access Time (ns)
Power
Temperature
Mark
K
35
40
45
50
Std.
0
C to 70
C
Blank
2
V53C8129H Rev. 1.3 July 1997
MOSEL VITELIC
V53C8129H
FAMILY
DEVICE
PKG
.
( t
RAC
)
SPEED
PWR.
V
5
3
C
1
2
9
35 (35 ns)
40 (40 ns)
45 (45 ns)
50 (50 ns)
TEMP.
BLANK (0
C to 70
C)
BLANK (NORMAL)
(SOJ)
8129H-01
K
H
8
Description
Pkg.
Pin Count
SOJ
K
26/24
26/24 Lead SOJ
PIN CONFIGURATION
Top View
Pin Names
8129H-02
1
2
3
4
5
6
8
9
10
11
12
13
26
25
24
23
22
21
19
18
17
16
15
14
VSS
I/O1
I/O2
I/O3
I/O4
WE
RAS
A0
A1
A2
A3
VCC
VSS
I/O8
I/O7
I/O6
I/O5
CAS
OE
A8 (Column Add. only)
A7
A6
A5
A4
A
0
A
8
Address Inputs (A
8
: Column Address only)
RAS
Row Address Strobe
CAS
Column Address Strobe
WE
Write Enable
OE
Output Enable
I/O
1
I/O
8
Data Input, Output
V
CC
+5V Supply
V
SS
0V Supply
Absolute Maximum Ratings*
Ambient Temperature
Under Bias .............................. 10
C to +80
C
Storage Temperature (plastic) ..... 55
C to +125
C
Voltage Relative to V
SS
.................1.0 V to +7.0 V
Data Output Current ..................................... 50 mA
Power Dissipation .......................................... 1.0 W
*Note:
Operation above Absolute Maximum Ratings can
adversely affect device reliability.
Capacitance*
T
A
= 25
C, V
CC
= 5 V
10%, V
SS
= 0 V
* Note:
Capacitance is sampled and not 100% tested
Symbol
Parameter Typ.
Max.
Unit
C
IN1
Address Input
3
4
pF
C
IN2
RAS, CAS, WE, OE
4
5
pF
C
OUT
Data Input/Output
5
7
pF
3
MOSEL VITELIC
V53C8129H
V53C8129H Rev. 1.3 July 1997
Block Diagram
A 0
A 1
A7
A8
SENSE AMPLIFIERS
REFRESH
COUNTER
VCC
VSS
9
I/O 1
ADDRESS BUFFERS
AND PREDECODERS
ROW
DECODERS
256
MEMORY
ARRAY
COLUMN DECODERS
DATA I/O BUS
Y0Y8
X0X7
512 x 8
I/O
BUFFER
I/O2
I/O3
I/O4
OE CLOCK
GENERATOR
WE CLOCK
GENERATOR
CAS CLOCK
GENERATOR
RAS CLOCK
GENERATOR
OE
8129H-03
128K x 8
WE
CAS
RAS
I/O 5
I/O6
I/O7
I/O8
4
V53C8129H Rev. 1.3 July 1997
MOSEL VITELIC
V53C8129H
DC and Operating Characteristics
(1-2)
T
A
= 0
C to 70
C, V
CC
= 5 V
10%, V
SS
= 0 V, unless otherwise specified.
Symbol
Parameter
Access
Time
V53C8129H
Unit
Test Conditions
Notes
Min.
Typ.
Max..
I
LI
Input Leakage Current
(any input pin)
10
10
A
V
SS
V
IN
V
CC
I
LO
Output Leakage Current
(for High-Z State)
10
10
A
V
SS
V
OUT
V
CC
RAS, CAS at V
IH
I
CC1
V
CC
Supply Current,
Operating
35
160
mA
t
RC
= t
RC
(min.)
1, 2
40
150
45
145
50
135
I
CC2
V
CC
Supply Current,
TTL Standby
4
mA
RAS, CAS at V
IH
other inputs
V
SS
I
CC3
V
CC
Supply Current,
RAS-Only Refresh
35
160
mA
t
RC
= t
RC
(min.)
2
40
150
45
145
50
135
I
CC4
V
CC
Supply Current,
EDO Page Mode Operation
35
95
mA
Minimum cycle
1, 2
40
90
45
85
50
80
I
CC5
V
CC
Supply Current,
Standby, Output Enabled
2
mA
RAS = V
IH
, CAS = V
IL
other inputs
V
SS
1
I
CC6
V
CC
Supply Current,
CMOS Standby
1
mA
RAS
V
CC
0.2 V,
CAS
V
CC
0.2 V,
All other inputs
V
SS
V
IL
Input Low Voltage
1
0.8
V
3
V
IH
Input High Voltage
2.4
V
CC
+ 1
V
3
V
OL
Output Low Voltage
0.4
V
I
OL
= 4.2 mA
V
OH
Output High Voltage
2.4
V
I
OH
= 5 mA
5
MOSEL VITELIC
V53C8129H
V53C8129H Rev. 1.3 July 1997
AC Characteristics
T
A
= 0
C to 70
C, V
CC
= 5 V
10%, V
SS
= 0V unless otherwise noted
AC Test conditions, input pulse levels 0 to 3V
#
JEDEC
Symbol
Symbol Parameter
35
40
45
50
Unit
Notes
Min. Max. Min. Max. Min. Max. Min. Max.
1
t
RL1RH1
t
RAS
RAS Pulse Width
35
75K
40
75K
45
75K
50
75K
ns
2
t
RL2RL2
t
RC
Read or Write Cycle Time
70
75
80
90
ns
3
t
RH2RL2
t
RP
RAS Precharge Time
25
25
25
30
ns
4
t
RL1CH1
t
CSH
CAS Hold Time
35
40
45
50
ns
5
t
CL1CH1
t
CAS
CAS Pulse Width
7
8
9
9
ns
6
t
RL1CL1
t
RCD
RAS to CAS Delay
16
23
17
28
18
32
19
36
ns
7
t
WH2CL2
t
RCS
Read Command Setup Time
0
0
0
0
ns
4
8
t
AVRL2
t
ASR
Row Address Setup Time
0
0
0
0
ns
9
t
RL1AX
t
RAH
Row Address Hold Time
6
7
8
9
ns
10
t
AVCL2
t
ASC
Column Address Setup Time
0
0
0
0
ns
11
t
CL1AX
t
CAH
Column Address Hold Time
4
5
6
7
ns
12
t
CL1RH1(R)
t
RSH (R)
RAS Hold Time (Read Cycle)
14
14
15
15
ns
13
t
CH2RL2
t
CRP
CAS to RAS Precharge Time
5
5
5
5
ns
14
t
CH2WX
t
RCH
Read Command Hold Time Referenced
to CAS
0
0
0
0
ns
5
15
t
RH2WX
t
RRH
Read Command Hold Time Referenced
to RAS
0
0
0
0
ns
5
16
t
OEL1RH2
t
ROH
RAS Hold Time Referenced to OE
8
9
10
10
ns
17
t
GL1QV
t
OAC
Access Time from OE
12
12
13
14
ns
18
t
CL1QV
t
CAC
Access Time from CAS (EDO)
12
12
13
14
ns
6, 7
19
t
RL1QV
t
RAC
Access Time from RAS
35
40
45
50
ns
6, 8, 9
20
t
AVQV
t
CAA
Access Time from Column Address
18
20
22
24
ns
6, 7, 10
21
t
CL1QX
t
LZ
CAS to Low-Z Output
0
0
0
0
ns
16
22
t
CH2QZ
t
HZ
Output buffer turn-off delay time
0
6
0
6
0
7
0
8
ns
16
23
t
RL1AX
t
AR
Column Address Hold Time from RAS
28
30
35
40
ns
24
t
RL1AV
t
RAD
RAS to Column Address Delay Time
11
17
12
20
13
23
14
26
ns
11
25
t
CL1RH1(W)
t
RSH (W)
RAS or CAS Hold Time in Write Cycle
12
12
13
14
ns
26
t
WL1CH1
t
CWL
Write Command to CAS Lead Time
12
12
13
14
ns
27
t
WL1CL2
t
WCS
Write Command Setup Time
0
0
0
0
ns
12, 13
28
t
CL1WH1
t
WCH
Write Command Hold Time
5
5
6
7
ns
29
t
WL1WH1
t
WP
Write Pulse Width
5
5
6
7
ns
30
t
RL1WH1
t
WCR
Write Command Hold Time from RAS
28
30
35
40
ns
31
t
WL1RH1
t
RWL
Write Command to RAS Lead Time
12
12
13
14
ns
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