MOSEL VITELIC
1
V53C8256H
ULTRA-HIGH SPEED,
256K x 8 FAST PAGE MODE
CMOS DYNAMIC RAM
PRELIMINARY
V53C8256H Rev. 1.2 July 1997
HIGH PERFORMANCE
35
40
45
50
Max. RAS Access Time, (t
RAC
)
35 ns
40 ns
45 ns
50 ns
Max. Column Address Access Time, (t
CAA
)
18 ns
20 ns
22 ns
24 ns
Min. Fast Page Mode Cycle Time, (t
PC
)
21 ns
23 ns
25 ns
28 ns
Min. Read/Write Cycle Time, (t
RC
)
70 ns
75 ns
80 ns
90 ns
Features
s
256K x 8-bit organization
s
Fast Page Mode for a sustained data rate
of 47 MHz
s
RAS access time: 35, 40, 45, 50 ns
s
Low power dissipation
s
Read-Modify-Write, RAS-Only Refresh,
CAS-Before-RAS Refresh capability
s
Refresh Interval: 512 cycles/8 ms
s
Single 5V
10% Power Supply
s
Available in 24-pin 300 mil Plastic DIP,
26/24-pin 300 mil SOJ, and 28-pin TSOP-I
packages
Description
The V53C8256H is a high speed 262,144 x 8 bit
CMOS dynamic random access memory. The
V53C8256H offers a combination of features: Fast
Page Mode for high data bandwidth, fast usable
speed, CMOS standby current.
All inputs and outputs are TTL compatible. Input
and output capacitances are significantly lowered to
allow increased system performance. Fast Page
Mode operation allows random access of up to 512
(x8) bits within a row with cycle times as short as 21
ns. Because of static circuitry, the CAS clock is not
in the critical timing path. The flow-through column
address latches allow address pipelining while re-
laxing many critical system timing requirements for
fast usable speed. These features make the
V53C8256H ideally suited for graphics, digital sig-
nal processing and high performance computing
systems.
Device Usage Chart
Operating
Temperature
Range
Package Outline
Access Time (ns)
Power
Temperature
Mark
P
K
T
50
60
70
Std.
0
C to 70
C
Blank
2
MOSEL VITELIC
V53C8256H
V53C8256H Rev. 1.2 July 1997
FAMILY
DEVICE
PKG
( t
RAC
)
SPEED
PWR.
V
5
3
C
2
5
6
35 (35 ns)
40 (40 ns)
45 (45 ns)
50 (50 ns)
TEMP.
BLANK (0
C to 70
C)
BLANK (NORMAL)
K (SOJ)
T (TSOP-I)
8256H-01
P (PLASTIC DIP)
H
8
24-Pin Plastic DIP
PIN CONFIGURATION
Top View
28-Pin TSOP-I
PIN CONFIGURATION
Top View
26/24-Pin SOJ
PIN CONFIGURATION
Top View
Pin Names
VSS
I/O1
I/O2
I/O3
I/O4
WE
RAS
A0
A1
A2
VSS
I/O8
I/O7
I/O6
I/O5
CAS
OE
A8
A7
A6
8256H-02
1
2
3
4
5
6
7
8
9
10
24
23
22
21
20
19
18
17
16
15
A3
VDD
A5
A4
11
12
14
13
A
0
A
8
Address Inputs
RAS
Row Address Strobe
CAS
Column Address Strobe
WE
Write Enable
OE
Output Enable
I/O
1
I/O
8
Data Input, Output
V
DD
+5V Supply
V
SS
0V Supply
NC
No Connect
VSS
I/O1
I/O2
I/O3
I/O4
WE
RAS
A0
A1
A2
VSS
I/O8
I/O7
I/O6
I/O5
CAS
OE
A8
A7
A6
8256H-03
1
2
3
4
5
6
8
9
10
11
27
26
24
23
22
21
19
18
17
16
A3
VDD
A5
A4
12
13
15
14
Description
Pkg.
Pin Count
Plastic DIP
P
24
SOJ
K
26/24
TSOP-I
T
28
MOSEL VITELIC
V53C8256H
3
V53C8256H Rev. 1.2 July 1997
Absolute Maximum Ratings*
Ambient Temperature
Under Bias .............................. 10
C to +80
C
Storage Temperature (plastic) ...... -55
C to +125
C
Voltage Relative to V
SS
...................1.0V to +7.0V
Data Output Current ..................................... 50 mA
Power Dissipation .......................................... 1.0 W
*
Note:
Operation above Absolute Maximum Ratings can
adversely affect device reliability.
Capacitance*
T
A
= 25
C, V
DD
= 5 V
10%, V
SS
= 0 V
*Note:
Capacitance is sampled and not 100% tested.
Symbol
Parameter Min.
Max.
Unit
C
IN1
Address Input
3
4
pF
C
IN2
RAS, CAS, WE, OE
4
5
pF
C
OUT
Data Input/Output
5
7
pF
Block Diagram
A0
A1
A
7
A8
SENSE AMPLIFIERS
REFRESH
COUNTER
VDD
VSS
9
8256H-05
I/O 1
ADDRESS B
UFFERS
AND PREDECODERS
X 0 -X
RO
W
DECODERS
512
MEMORY
ARRAY
COLUMN DECODERS
DATA I/O BUS
Y0 -Y8
512 x 8
I/O
BUFFER
I/O2
I/O3
I/O4
OE CLOCK
GENERATOR
WE CLOCK
GENERATOR
CAS CLOCK
GENERATOR
256K x 8
RAS CLOCK
GENERATOR
OE
WE
CAS
RAS
8
I/O 5
I/O6
I/O7
I/O8
4
V53C8256H Rev. 1.2 July 1997
MOSEL VITELIC
V53C8256H
DC and Operating Characteristics
(1-2)
T
A
= 0
C to 70
C, V
CC
= 5 V
10%, V
SS
= 0 V, unless otherwise specified.
Symbol
Parameter
Access
Time
V53C8256H
Unit
Test Conditions
Notes
Min.
Typ.
Max.
I
LI
Input Leakage Current
(any input pin)
10
10
A
V
SS
V
IN
V
CC
I
LO
Output Leakage Current
(for High-Z State)
10
10
A
V
SS
V
OUT
V
CC
RAS, CAS at V
IH
I
CC1
V
CC
Supply Current,
Operating
35
160
mA
t
RC
= t
RC
(min.)
1, 2
40
150
45
145
50
135
I
CC2
V
CC
Supply Current,
TTL Standby
4
mA
RAS, CAS at V
IH
other inputs
V
SS
I
CC3
V
CC
Supply Current,
RAS-Only Refresh
35
160
mA
t
RC
= t
RC
(min.)
2
40
150
45
145
50
135
I
CC4
V
CC
Supply Current,
Fast Page Mode
Operation
35
95
mA
Minimum Cycle
1, 2
40
90
45
85
50
80
I
CC5
V
CC
Supply Current,
Standby, Output Enabled
2
mA
RAS = V
IH
, CAS = V
IL
,
other inputs
V
SS
1
I
CC6
VCC Supply Current,
CMOS Standby
1
mA
RAS
V
CC
0.2 V,
CAS
V
CC
0.2 V,
All other inputs
V
SS
V
IL
Input Low Voltage
1
0.8
V
3
V
IH
Input High Voltage
2.4
V
CC
+ 1
V
3
V
OL
Output Low Voltage
0.4
V
I
OL
= 4.2 mA
V
OH
Output High Voltage
2.4
V
I
OH
= 5 mA
5
MOSEL VITELIC
V53C8256H
V53C8256H Rev. 1.2 July 1997
AC Characteristics
T
A
= 0
C to 70
C, V
CC
= 5 V
10%, V
SS
= 0V unless otherwise noted
AC Test conditions, input pulse levels 0 to 3V
#
JEDEC
Symbol
Symbol
Parameter
35
40
45
50
Unit
Notes
Min. Max. Min. Max. Min. Max. Min. Max.
1
t
RL1RH1
t
RAS
RAS Pulse Width
35
75K
40
75K
45
75K
50
75K
ns
2
t
RL2RL2
t
RC
Read or Write Cycle Time
70
75
80
90
ns
3
t
RH2RL2
t
RP
RAS Precharge Time
25
25
25
30
ns
4
t
RL1CH1
t
CSH
CAS Hold Time
35
40
45
50
ns
5
t
CL1CH1
t
CAS
CAS Pulse Width
12
12
13
14
ns
6
t
RL1CL1
t
RCD
RAS to CAS Delay
16
23
17
28
18
32
19
36
ns
7
t
WH2CL2
t
RCS
Read Command Setup Time
0
0
0
0
ns
4
8
t
AVRL2
t
ASR
Row Address Setup Time
0
0
0
0
ns
9
t
RL1AX
t
RAH
Row Address Hold Time
6
7
8
9
ns
10
t
AVCL2
t
ASC
Column Address Setup Time
0
0
0
0
ns
11
t
CL1AX
t
CAH
Column Address Hold Time
4
5
6
7
ns
12
t
CL1RH1(R)
t
RSH (R)
RAS Hold Time (Read Cycle)
12
12
13
14
ns
13
t
CH2RL2
t
CRP
CAS to RAS Precharge Time
5
5
5
5
ns
14
t
CH2WX
t
RCH
Read Command Hold Time
Referenced to CAS
0
0
0
0
ns
5
15
t
RH2WX
t
RRH
Read Command Hold Time
Referenced to RAS
0
0
0
0
ns
5
16
t
OEL1RH2
t
ROH
RAS Hold Time Referenced
to OE
8
8
9
10
ns
17
t
GL1QV
t
OAC
Access Time from OE
12
12
13
14
ns
18
t
CL1QV
t
CAC
Access Time from CAS
12
12
13
14
ns
6, 7
19
t
RL1QV
t
RAC
Access Time from RAS
35
40
45
50
ns
6, 8, 9
20
t
AVQV
t
CAA
Access Time from Column
Address
18
20
22
24
ns
6, 7, 10
21
t
CL1QX
t
LZ
OE or CAS to Low-Z Output
0
0
0
0
ns
16
22
t
CH2QZ
t
HZ
OE or CAS to High-Z Output
0
6
0
6
0
7
0
8
ns
16
23
t
RL1AX
t
AR
Column Address Hold Time
from RAS
28
30
35
40
ns
24
t
RL1AV
t
RAD
RAS to Column Address
Delay Time
11
17
12
20
13
23
14
26
ns
11
25
t
CL1RH1(W)
t
RSH (W)
RAS or CAS Hold Time in
Write Cycle
12
12
13
14
ns
26
t
WL1CH1
t
CWL
Write Command to CAS Lead
Time
12
12
13
14
ns
27
t
WL1CL2
t
WCS
Write Command Setup Time
0
0
0
0
ns
12, 13
28
t
CL1WH1
t
WCH
Write Command Hold Time
5
5
6
7
ns
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