1
MOSEL VITELIC
V53C8258H
V53C8258H Rev. 1.4 February 1997
PRELIMINARY
HIGH PERFORMANCE
35
40
45
50
Max.
RAS
Access Time, (t
RAC
)
35 ns
40 ns
45 ns
50 ns
Max. Column Address Access Time, (t
CAA
)
18 ns
20 ns
22 ns
24 ns
Min. Extended Data Out Page Mode Cycle Time, (t
PC
)
14 ns
15 ns
17 ns
19 ns
Min. Read/Write Cycle Time, (t
RC
)
70 ns
75 ns
80 ns
90 ns
Features
s
256K x 8-bit organization
s
EDO Page Mode for a sustained data rate
of 71 MHz
s
RAS
access time: 35, 40, 45, 50 ns
s
Low power dissipation
s
Read-Modify-Write,
RAS
-Only Refresh,
CAS
-Before-
RAS
Refresh capability
s
Refresh Interval: 512 cycles/8 ms
s
Available in 24 pin 300 mil Plastic DIP,
26/24 pin 300 mil SOJ and 28-pin 300 mil
TSOP-I packages
s
Single 5V
10% Power Supply
s
TTL Interface
Description
The V53C8258H is a high speed 262,144 x 8 bit
CMOS dynamic random access memory.
The V53C8258H offers a combination of features:
Page Mode with Extended Data Output for high
data bandwidth, and Low CMOS standby current.
All inputs and outputs are TTL compatible. Input
and output capacitances are significantly lowered to
allow increased system performance. Page Mode
with Extended Data Output operation allows
random access of up to 512 (x8) bits within a row
with cycle times as fast as 14 ns. Because of static
circuitry, the
CAS
clock is not in the critical timing
path. The flow-through column address latches
allow address pipelining while relaxing many critical
system timing requirements. The V53C8258H is
ideally suited for graphics, digital signal processing
and high-performance computing systems.
V53C8258H
HIGH PERFORMANCE
256K X 8 EDO PAGE MODE
CMOS DYNAMIC RAM
Device Usage Chart
Operating
Package Outline
Access Time (ns)
Power
Temperature
Temperature
Range
P
K
T
35
40
45
50
Std.
Mark
0
C to 70
C
Blank
2
MOSEL VITELIC
V53C8258H
V53C8258H Rev. 1.4 February 1997
Pin Names
A
0
A
8
Address Inputs
RAS
Row Address Strobe
CAS
Column Address Strobe
WE
Write Enable
OE
Output Enable
I/O
1
I/O
8
Data Input, Output
V
CC
+5V Supply
V
SS
0V Supply
NC
No Connect
FAMILY
DEVICE
PKG
( t
RAC
)
SPEED
PWR.
V
5
3
C
2
5
8
35ns
TEMP.
BLANK (0
C to 70
C)
BLANK (NORMAL)
P (PLASTIC DIP)
K (SOJ)
T (TSOP-I)
H
40ns
45ns
50ns
8
8258H-01
Description
Pkg.
Pin Count
Plastic DIP
P
24
SOJ
K
26/24
TSOP-I
T
28
26/24 Lead SOJ
PIN CONFIGURATION
Top View
24 Lead Plastic DIP
PIN CONFIGURATION
Top View
26
300 mil
V
SS
25
I/O
8
24
I/O
7
23
I/O
6
22
I/O
5
21
CAS
19
8258H-02
OE
18
A
8
16
A
7
16
A
6
15
A
5
14
V
SS
I/O
1
I/O
2
I/O
3
I/O
4
WE
RAS
A
0
A
1
A
2
A
3
V
CC
A
4
1
2
3
4
5
6
8
9
10
11
12
13
24
300 mil
V
SS
23
I/O
8
22
I/O
7
21
I/O
6
20
I/O
5
19
CAS
18
8258H-03
OE
17
A
8
16
A
7
15
A
6
14
A
5
13
V
SS
I/O
1
I/O
2
I/O
3
I/O
4
WE
RAS
A
0
A
1
A
2
A
3
V
CC
A
4
1
2
3
4
5
6
7
8
9
10
11
12
CAS
I/O5
I/O6
I/O7
I/O8
VSS
VSS
NC
I/O1
I/O2
I/O3
I/O4
NC
WE
OE
A8
A7
A6
A5
A4
NC
VCC
NC
A3
A2
A1
A0
RAS
28
27
26
25
24
23
22
21
20
19
18
17
16
15
8258H-04
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28 Lead TSOP-I
PIN CONFIGURATION
Top View
Absolute Maximum Ratings*
Ambient Temperature
Under Bias ............................. 10
C to +80
C
Storage Temperature (plastic) ... 55
C to +125
C
Voltage Relative to V
SS ....................
1.0 V to +7.0 V
Data Output Current .................................... 50 mA
Power Dissipation ........................................ 1.0 W
*Note: Operation above Absolute Maximum Ratings can
adversely affect device reliability.
Capacitance*
T
A
= 25
C, V
CC
= 5 V
10%, V
SS
= 0 V
Symbol
Parameter
Typ. Max.
Unit
C
IN1
Address Input
3
4
pF
C
IN2
RAS
,
CAS
,
OE
,
WE
4
5
pF
C
OUT
Data Input/Output
5
7
pF
* Note: Capacitance is sampled and not 100% tested
4
MOSEL VITELIC
V53C8258H
V53C8258H Rev. 1.4 February 1997
DC and Operating Characteristics (1-2)
T
A
= 0
C to 70
C, V
CC
= 5 V
10%, V
SS
= 0 V, unless otherwise specified.
V53C8258H
Time
Min.
Typ. Max..
Unit
Test Conditions
Notes
I
LI
Input Leakage Current
10
10
A
V
SS
V
IN
V
CC
(any input pin)
I
LO
Output Leakage Current
10
10
A
V
SS
V
OUT
V
CC
(for High-Z State)
RAS
,
CAS
at V
IH
35
160
40
150
mA
t
RC
= t
RC
(min.)
1, 2
45
145
50
135
I
CC2
V
CC
Supply Current,
RAS
,
CAS
at V
IH
TTL Standby
2
mA
other inputs
V
SS
35
160
I
CC3
40
150
mA
t
RC
= t
RC
(min.)
2
45
145
50
135
I
CC4
35
95
40
90
mA
Minimum cycle
1, 2
45
85
50
80
I
CC5
V
CC
Supply Current,
2.0
mA
RAS
=V
IH
,
CAS
=V
IL
1
Standby, Output Enabled
other inputs
V
SS
I
CC6
V
CC
Supply Current,
RAS
V
CC
0.2 V,
CMOS Standby
1.0
mA
CAS
V
CC
0.2 V,
All other inputs
V
SS
V
IL
Input Low Voltage
1
0.8
V
3
V
IH
Input High Voltage
2.0
V
CC
+1
V
3
V
OL
Output Low Voltage
0.4
V
I
OL
= 4.2 mA
V
OH
Output High Voltage
2.4
V
I
OH
= 5 mA
Access
I
CC1
V
CC
Supply Current,
Operating
V
CC
Supply Current,
EDO Page Mode
Operation
V
CC
Supply Current,
RAS
-Only Refresh
Symbol
Parameter
5
MOSEL VITELIC
V53C8258H
V53C8258H Rev. 1.4 February 1997
AC Characteristics
T
A
= 0
C to 70
C, V
CC
= 5 V
10%, V
SS
= 0V unless otherwise noted
AC Test conditions, input pulse levels 0 to 3V
35
40
45
50
#
Symbol
Symbol
Parameter
Min. Max. Min. Max. Min. Max. Min. Max.
Unit
Notes
1
t
RL1RH1
t
RAS
RAS
Pulse Width
35
75K
40
75K
45
75K
50
75K
ns
2
t
RL2RL2
t
RC
Read or Write Cycle Time
70
75
80
90
ns
3
t
RH2RL2
t
RP
RAS
Precharge Time
25
25
25
30
ns
4
t
RL1CH1
t
CSH
CAS
Hold Time
35
40
45
50
ns
5
t
CL1CH1
t
CAS
CAS
Pulse Width
7
8
9
9
ns
6
t
RL1CL1
t
RCD
RAS
to
CAS
Delay
16
23
17
28
18
32
19
36
ns
7
t
WH2CL2
t
RCS
Read Command Setup Time
0
0
0
0
ns
4
8
t
AVRL2
t
ASR
Row Address Setup Time
0
0
0
0
ns
9
t
RL1AX
t
RAH
Row Address Hold Time
6
7
8
9
ns
10
t
AVCL2
t
ASC
Column Address Setup Time
0
0
0
0
ns
11
t
CL1AX
t
CAH
Column Address Hold Time
4
5
6
7
ns
12
t
CL1RH1(R)
t
RSH (R)
RAS
Hold Time (Read Cycle)
12
12
13
14
ns
13
t
CH2RL2
t
CRP
CAS
to
RAS
Precharge Time
5
5
5
5
ns
14
t
CH2WX
t
RCH
Read Command Hold Time
0
0
0
0
ns
5
Referenced to
CAS
15
t
RH2WX
t
RRH
Read Command Hold Time
0
0
0
0
ns
5
Referenced to
RAS
16
t
OEL1RH2
t
ROH
RAS
Hold Time
8
8
9
10
ns
Referenced to
OE
17
t
GL1QV
t
OAC
Access Time from
OE
12
12
13
14
ns
18
t
CL1QV
t
CAC
Access Time from
CAS
(EDO)
12
12
13
14
ns
6, 7
19
t
RL1QV
t
RAC
Access Time from
RAS
35
40
45
50
ns
6, 8, 9
20
t
AVQV
t
CAA
Access Time from Column
18
20
22
24
ns
6, 7, 10
Address
21
t
CL1QX
t
LZ
CAS
to Low-Z Output
0
0
0
0
ns
16
22
t
CH2QZ
t
HZ
Output buffer turn-off delay time
0
6
0
6
0
7
0
8
ns
16
23
t
RL1AX
t
AR
Column Address Hold Time
28
30
35
40
ns
from
RAS
24
t
RL1AV
t
RAD
RAS
to Column Address
11
17
12
20
13
23
14
26
ns
11
Delay Time
25
t
CL1RH1(W)
t
RSH (W)
RAS
or
CAS
Hold Time
12
12
13
14
ns
in Write Cycle
26
t
WL1CH1
t
CWL
Write Command to
CAS
12
12
13
14
ns
Lead Time
JEDEC
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