MOSEL VITELIC
1
V53C832L
HIGH PERFORMANCE
3.3 VOLT 256K X 32 EDO PAGE MODE
CMOS DYNAMIC RAM
PRELIMINARY
V53C832L Rev. 1.6 August 1999
HIGH PERFORMANCE
30
35
40
Max. RAS Access Time, (t
RAC
)
30 ns
35 ns
40 ns
Max. Column Address Access Time, (t
CAA
)
16 ns
18 ns
20 ns
Min. Extended Data Out Page Mode Cycle Time, (t
PC
)
12 ns
14 ns
15 ns
Min. Read/Write Cycle Time, (t
RC
)
65 ns
70 ns
75 ns
Features
s
256K x 32-bit organization
s
EDO Page Mode for a sustained data rate of
83 MHz
s
RAS access time: 30, 35, 40 ns
s
Four CAS Inputs for Byte Read and Byte Write
Control
s
Low power dissipation
s
Read-Modify-Write, RAS-Only Refresh,
CAS-Before-RAS Refresh
s
Refresh Interval: 512 cycles/8 ms
s
Available in 100-pin PQFP and 100-pin LQFP
packages
s
Single +3.3V
0.3V Power Supply
s
TTL Interface
Description
The V53C832L is a high speed 262,144 x 32 bit
high performance CMOS dynamic random access
memory. The V53C832L offers a combination of
unique features including: EDO Page Mode opera-
tion for higher sustained bandwidth with Page Mode
cycle times as short as 12ns. All inputs are TTL
compatible. Input and output capacitance is signifi-
cantly lowered to increase performance and mini-
mize loading. These features make the V53C832L
ideally suited for a wide variety of high performance
computer systems and peripheral applications.
Device Usage Chart
Operating
Temperature
Range
Package Outline
Access Time (ns)
Power
Temperature
Mark
Q
TQ
30
35
40
Std.
0
C to 70
C
Blank
2
V53C832L Rev. 1.6 August 1999
MOSEL VITELIC
V53C832L
FAMILY
DEVICE
PKG
( t
RAC
)
SPEED
PWR.
V
5
3
C
3
2
30 (30 ns)
35 (35 ns)
40 (40 ns)
TEMP.
BLANK (0
C to 70
C)
BLANK (NORMAL)
Q (PQFP)
TQ (TQFP)
L
8
832L-01
Pin Table
A
0
A
8
Address Inputs
RAS
Row Address Strobe
CAS0
Column Address Strobe for First
Byte (I/O
1
I/O
8
)
CAS1
Column Address Strobe for Second
Byte (I/O
9
I/O
16
)
CAS2
Column Address Strobe for Third
Byte (I/O
17
I/O
24
)
CAS3
Column Address Strobe for Fourth
Byte (I/O
25
I/O
32
)
WE
Write Enable
OE
Output Enable
I/O
1
I/O
32
Data Input, Output
V
CC
+3.3V Supply
V
SS
0V Supply
NC
No Connect
Description
Pkg.
Pin Count
PQFP
Q
100
TQFP
TQ
100
100-Pin PQFP/TQFP
PIN CONFIGURATION
Top View
5
6
7
8
9
10
11
12
I/O4
VCC
I/O5
I/O6
VSS
I/O7
I/O8
VCC
I/O17
I/O18
VSS
I/O19
I/O20
VCC
VCC
VSS
I/O21
I/O22
VSS
I/O23
I/O24
VCC
CAS0
CAS2
WE
NC
NC
RAS
NC
NC
I/O29
VCC
I/O28
I/O27
VSS
I/O26
I/O25
VCC
I/O16
I/O15
VSS
I/O14
I/O13
VCC
VSS
VCC
I/O12
I/O11
VSS
I/O10
I/O9
VCC
NC
CAS3
CAS1
NC
NC
OE
NC
A8
A0
A1
A2
A3
VCC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
VSS
A4
A5
A6
A7
I/O3
VSS
I/O2
I/O1
VCC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
VSS
I/O32
I/O31
VSS
I/O30
1
2
3
4
832H-02
13
14
15
16
17
18
19
20
35
36
37
38
39
40
41
42
31
32
33
34
43
44
45
46
47
48
49
50
96
95
94
93
92
91
90
89
100
99
98
97
88
87
86
85
84
83
82
81
21
22
23
24
25
26
27
28
29
30
76
75
74
73
72
71
70
69
80
79
78
77
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
3
V53C832L Rev. 1.6 August 1999
MOSEL VITELIC
V53C832L
Absolute Maximum Ratings*
Ambient Temperature
Under Bias ................................. 10
C to +80
C
Storage Temperature (plastic) ..... 55
C to +125
C
Voltage Relative to V
SS
..................1.0 V to +4.6V
Data Output Current ..................................... 50 mA
Power Dissipation .......................................... 1.0 W
*Note:
Operation above Absolute Maximum Ratings can
adversely affect device reliability.
Capacitance*
T
A
= 25
C, V
CC
= 3.3V
0.3V, V
SS
= 0 V
*Note:
Capacitance is sampled and not 100% tested.
Symbol
Parameter
Typ.
Max.
Unit
C
IN1
Address Input
3
4
pF
C
IN2
RAS, CAS, WE, OE
4
5
pF
C
OUT
Data Input/Output
5
7
pF
Block Diagram
A0
A1
A 7
A 8
SENSE AMPLIFIERS
REFRESH
COUNTER
VCC
VSS
9
I/O
1
ADDRESS BUFFERS
AND PREDECODERS
X0 -X
ROW
DECODERS
512
MEMORY
ARRAY
512 x 512 x 32
COLUMN DECODERS
DATA I/O BUS
Y0 -Y8
512 x 32
832L-03
I/O
BUFFER
OE
CLOCK
GENERATOR
WE
CLOCK
GENERATOR
256K x 32
CAS
CLOCK
GENERATOR
RAS
CLOCK
GENERATOR
I/O
2
I/O
3
I/O
4
I/O
5
I/O
6
I/O
7
I/O
8
I/O
9
I/O
10
I/O
11
I/O
12
I/O
13
I/O
14
I/O
15
I/O
16
I/O
17
I/O
18
I/O
19
I/O
20
I/O
21
I/O
22
I/O
23
I/O
24
I/O
25
I/O
26
I/O
27
I/O
28
I/O
29
I/O
30
I/O
31
I/O
32
OE
WE
CAS
2
CAS
3
RAS
8
CAS
1
CAS
0
4
V53C832L Rev. 1.6 August 1999
MOSEL VITELIC
V53C832L
DC and Operating Characteristics
(1-2)
T
A
= 0
C to 70
C, V
CC
= 3.3V
0.3V, V
SS
= 0 V, unless otherwise specified.
Symbol
Parameter
Time
V53C832L
Unit
Test Conditions
Notes
Min.
Typ.
Max.
I
LI
Input Leakage Current
(any input pin)
10
10
A
V
SS
V
IN
V
CC
I
LO
Output Leakage Current
(for High-Z State)
10
10
A
V
SS
V
OUT
V
CC
RAS, CAS at V
IH
I
CC1
V
CC
Supply Current,
Operating
30
130
mA
t
RC
= t
RC
(min.)
1, 2
35
120
40
110
I
CC2
V
CC
Supply Current,
TTL Standby
4
mA
RAS, CAS at V
IH
other inputs
V
SS
I
CC3
V
CC
Supply Current,
RAS-Only Refresh
30
130
mA
t
RC
= t
RC
(min.)
2
35
120
40
110
I
CC4
V
CC
Supply Current,
EDO Page Mode Operation
30
120
mA
Minimum Cycle
1, 2
35
110
40
100
I
CC5
V
CC
Supply Current,
Standby, Output Enabled
2.0
mA
RAS=V
IH
, CAS=V
IL
1
I
CC6
V
CC
Supply Current,
CMOS Standby
2.0
mA
RAS
V
CC
0.2 V,
CAS
V
CC
0.2 V,
All other inputs
V
SS
V
CC
Supply Voltage
3.0
3.3
3.6
V
V
IL
Input Low Voltage
1
0.8
V
3
V
IH
Input High Voltage
2.4
V
CC
+1
V
3
V
OL
Output Low Voltage
0.4
V
I
OL
= 2 mA
V
OH
Output High Voltage
2.4
V
I
OH
= 2 mA
5
V53C832L Rev. 1.6 August 1999
MOSEL VITELIC
V53C832L
AC Characteristics
T
A
= 0
C to 70
C, V
CC
= 3.3V
0.3V, V
SS
= 0V unless otherwise noted
AC Test conditions, input pulse levels 0 to 3V
#
Symbol
Parameter
30
35
40
Unit
Notes
Min. Max. Min. Max. Min. Max.
1
t
RAS
RAS Pulse Width
30
75K
35
75K
40
75K
ns
2
t
RC
Read or Write Cycle Time
65
70
75
ns
3
t
RP
RAS Precharge Time
25
25
25
ns
4
t
CSH
CAS Hold Time
30
35
40
ns
5
t
CAS
CAS Pulse Width
5
6
7
ns
6
t
RCD
RAS to CAS Delay
15
20
16
24
17
28
ns
7
t
RCS
Read Command Setup Time
0
0
0
ns
4
8
t
ASR
Row Address Setup Time
0
0
0
ns
9
t
RAH
Row Address Hold Time
5
6
7
ns
10
t
ASC
Column Address Setup Time
0
0
0
ns
11
t
CAH
Column Address Hold Time
5
5
5
ns
12
t
RSH (R)
RAS Hold Time (Read Cycle)
10
10
10
ns
13
t
CRP
CAS to RAS Precharge Time
5
5
5
ns
14
t
RCH
Read Command Hold Time
Referenced to CAS
0
0
0
ns
5
15
t
RRH
Read Command Hold Time Referenced to RAS
0
0
0
ns
5
16
t
ROH
RAS Hold Time Referenced to OE
6
7
8
ns
17
t
OAC
Access Time from OE
10
11
12
ns
12
18
t
CAC
Access Time from CAS
10
11
12
ns
6,7,14
19
t
RAC
Access Time from RAS
30
35
40
ns
6, 8, 9
20
t
CAA
Access Time from Column Address
16
18
20
ns
6,7,10
21
t
LZ
OE or CAS to Low-Z Output
0
0
0
ns
16
22
t
HZ
OE or CAS to High-Z Output
0
5
0
6
0
6
ns
16
23
t
AR
Column Address Hold Time fromRAS
26
28
30
ns
24
t
RAD
RAS to Column Address Delay Time
10
14
11
17
12
20
ns
11
25
t
RSH (W)
RAS or CAS Hold Time in Write Cycle
10
10
10
ns
26
t
CWL
Write Command to CAS Lead Time
10
11
12
ns
27
t
WCS
Write Command Setup Time
0
0
0
ns
12, 13
28
t
WCH
Write Command Hold Time
5
5
5
ns
29
t
WP
Write Pulse Width
5
5
5
ns
30
t
WCR
Write Command Hold Time from RAS
26
28
30
ns
31
t
RWL
Write Command to RAS Lead Time
10
11
12
ns
32
t
DS
Data in Setup Time
0
0
0
ns
14
33
t
DH
Data in Hold Time
5
5
5
ns
14
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