MOSEL VITELIC
1
V54C3128(16/80/40)4V(T/S)
128Mbit SDRAM
3.3 VOLT, TSOP II / SOC PACKAGE
8M X 16, 16M X 8, 32M X 4
V54C3128(16/80/40)4V(T/S) Rev. 1.5 March 2003
PRELIMINARY
6
7PC
7
8PC
System Frequency (f
CK
)
166 MHz
143 MHz
143 MHz
125 MHz
Clock Cycle Time (t
CK3
)
6 ns
7 ns
7 ns
8 ns
Clock Access Time (t
AC3
) CAS Latency = 3
5.4 ns
5.4 ns
5.4 ns
6 ns
Clock Access Time (t
AC2
) CAS Latency = 2
5.4 ns
5.4 ns
6 ns
6 ns
Features
4 banks x 2Mbit x 16 organization
4 banks x 4Mbit x 8 organization
4 banks x 8Mbit x 4 organization
High speed data transfer rates up to 166 MHz
Full Synchronous Dynamic RAM, with all signals
referenced to clock rising edge
Single Pulsed RAS Interface
Data Mask for Read/Write Control
Four Banks controlled by BA0 & BA1
Programmable CAS Latency: 2, 3
Programmable Wrap Sequence: Sequential or
Interleave
Programmable Burst Length:
1, 2, 4, 8 for Sequential Type
1, 2, 4, 8 for Interleave Type
Multiple Burst Read with Single Write Operation
Automatic and Controlled Precharge Command
Random Column Address every CLK (1-N Rule)
Power Down Mode
Auto Refresh and Self Refresh
Refresh Interval: 4096 cycles/64 ms
Available in 60-ball SOC BGA and 54 Pin
TSOPII
LVTTL Interface
Single +3.3 V
0.3 V Power Supply
Description
The V54C3128(16/80/40)4V(T/S) is a four bank
Synchronous DRAM organized as 4 banks x 2Mbit
x 16, 4 banks x 4Mbit x 8, or 4 banks x 8Mbit x 4.
The V54C3128(16/80/40)4V(T/S) achieves high
speed data transfer rates up to 166 MHz by employ-
ing a chip architecture that prefetches multiple bits
and then synchronizes the output data to a system
clock
All of the control, address, data input and output
circuits are synchronized with the positive edge of
an externally supplied clock.
Operating the four memory banks in an inter-
leaved fashion allows random access operation to
occur at higher rate than is possible with standard
DRAMs. A sequential and gapless data rate of up to
166 MHz is possible depending on burst length,
CAS latency and speed grade of the device.
Device Usage Chart
Operating
Temperature
Range
Package Outline
Access Time (ns)
Power
Temperature
Mark
T/S
6
7PC
7
8PC
Std.
L
0
C to 70
C
Blank
3
V54C3128(16/80/40)4V(T/S) Rev. 1.5 March 2003
MOSEL VITELIC
V54C3128(16/80/40)4V(T/S)
54 Pin Plastic TSOP-II
PIN CONFIGURATION
Top View
Pin Names
V
CC
I/O
1
V
CCQ
I/O
2
I/O
3
V
SSQ
I/O
4
I/O
5
V
CCQ
I/O
6
I/O
7
V
SSQ
I/O
8
V
CC
LDQM
WE
CAS
RAS
CS
BA0
BA1
A
10
A
0
A
1
A
2
A
3
V
CC
V
SS
I/O
16
V
SSQ
I/O
15
I/O
14
V
CCQ
I/O
13
I/O
12
V
SSQ
I/O
11
I/O
10
V
CCQ
I/O
9
V
SS
NC
UDQM
CLK
CKE
NC
A
11
A
9
A
8
A
7
A
6
A
5
A
4
V
SS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
CLK
Clock Input
CKE
Clock Enable
CS
Chip Select
RAS
Row Address Strobe
CAS
Column Address Strobe
WE
Write Enable
A
0
A
11
Address Inputs
BA0, BA1
Bank Select
I/O
1
I/O
16
Data Input/Output
LDQM, UDQM
Data Mask
V
CC
Power (+3.3V)
V
SS
Ground
V
CCQ
Power for I/O's (+3.3V)
V
SSQ
Ground for I/O's
NC
Not connected
V 54 C 3 12816 4 V A L T
Mosel Vitelic
Manufactured
SYNCHRONOUS
DRAM FAMILY
C=CMOS Family
3.3V, LVTTL INTERFACE
8Mx16(4K Refresh)
4 Banks
V=LVTTL
Component Rev Level
Special
Feature
L=Low Power
Component
Package
Speed
6 ns
7 ns
8 ns
Device
Number
Description
Pkg.
Pin Count
TSOP-II
T
54
4
V54C3128(16/80/40)4V(T/S) Rev.1.5 March 2003
MOSEL VITELIC
V54C3128(16/80/40)4V(T/S)
54 Pin Plastic TSOP-II
PIN CONFIGURATION
Top View
Pin Names
V
CC
I/O
1
V
CCQ
NC
I/O
2
V
SSQ
NC
I/O
3
V
CCQ
NC
I/O
4
V
SSQ
NC
V
CC
NC
WE
CAS
RAS
CS
BA0
BA1
A
10
A
0
A
1
A
2
A
3
V
CC
V
SS
I/O
8
V
SSQ
NC
I/O
7
V
CCQ
NC
I/O
6
V
SSQ
NC
I/O
5
V
CCQ
NC
V
SS
NC
DQM
CLK
CKE
NC
A
11
A
9
A
8
A
7
A
6
A
5
A
4
V
SS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
CLK
Clock Input
CKE
Clock Enable
CS
Chip Select
RAS
Row Address Strobe
CAS
Column Address Strobe
WE
Write Enable
A
0
A
11
Address Inputs
BA0, BA1
Bank Select
I/O
1
I/O
8
Data Input/Output
DQM
Data Mask
V
CC
Power (+3.3V)
V
SS
Ground
V
CCQ
Power for I/O's (+3.3V)
V
SSQ
Ground for I/O's
NC
Not connected
V 54 C 3 12880 4 V A L T
Mosel Vitelic
Manufactured
SYNCHRONOUS
DRAM FAMILY
C=CMOS Family
3.3V, LVTTL INTERFACE
16Mx8(4K Refresh)
4 Banks
V=LVTTL
Component Rev Level
Special
Feature
L=Low Power
Component
Package
Speed
6 ns
7 ns
8 ns
Device
Number
Description
Pkg.
Pin Count
TSOP-II
T
54
5
V54C3128(16/80/40)4V(T/S) Rev. 1.5 March 2003
MOSEL VITELIC
V54C3128(16/80/40)4V(T/S)
54 Pin Plastic TSOP-II
PIN CONFIGURATION
Top View
Pin Names
V
CC
NC
V
CCQ
NC
I/O
1
V
SSQ
NC
NC
V
CCQ
NC
I/O
2
V
SSQ
NC
V
CC
NC
WE
CAS
RAS
CS
BA0
BA1
A
10
A
0
A
1
A
2
A
3
V
CC
V
SS
NC
V
SSQ
NC
I/O
4
V
CCQ
NC
NC
V
SSQ
NC
I/O
3
V
CCQ
NC
V
SS
NC
DQM
CLK
CKE
NC
A
11
A
9
A
8
A
7
A
6
A
5
A
4
V
SS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
CLK
Clock Input
CKE
Clock Enable
CS
Chip Select
RAS
Row Address Strobe
CAS
Column Address Strobe
WE
Write Enable
A
0
A
11
Address Inputs
BA0, BA1
Bank Select
I/O
1
I/O
4
Data Input/Output
DQM
Data Mask
V
CC
Power (+3.3V)
V
SS
Ground
V
CCQ
Power for I/O's (+3.3V)
V
SSQ
Ground for I/O's
NC
Not connected
V 54 C 3 12840 4 V A L T
Mosel Vitelic
Manufactured
SYNCHRONOUS
DRAM FAMILY
C=CMOS Family
3.3V, LVTTL INTERFACE
32Mx4(4K Refresh)
4 Banks
V=LVTTL
Component Rev Level
Special
Feature
L=Low Power
Component
Package
Speed
6 ns
7 ns
8 ns
Device
Number
Description
Pkg.
Pin Count
TSOP-II
T
54
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