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MOSEL VITELIC

V54C3256(16/80/40)4V(T/S/B)
256Mbit SDRAM
3.3 VOLT, TSOP II / SOC BGA / WBGA
PACKAGE 16M X 16, 32M X 8, 64M X 4

V54C3256(16/80/40)4V(T/S/B) Rev. 1.6 September 2002

PRELIMINARY

7PC

8PC

System Frequency (f

)

166 MHz

143 MHz

125 MHz

Clock Cycle Time (t

CK3

)

6 ns

7 ns

8 ns

Clock Access Time (t

AC3

) CAS Latency = 3

5.4 ns

6 ns

Clock Access Time (t

AC2

) CAS Latency = 2

5.4 ns

6 ns

Features

4 banks x 4Mbit x 16 organization

4 banks x 8Mbit x 8 organization

4 banks x16Mbit x 4 organization

High speed data transfer rates up to 166 MHz

Full Synchronous Dynamic RAM, with all signals
referenced to clock rising edge

Single Pulsed RAS Interface

Data Mask for Read/Write Control

Four Banks controlled by BA0 & BA1

Programmable CAS Latency: 2, 3

Programmable Wrap Sequence: Sequential or
Interleave

Programmable Burst Length:
1, 2, 4, 8 for Sequential Type
1, 2, 4, 8 for Interleave Type

Multiple Burst Read with Single Write Operation

Automatic and Controlled Precharge Command

Random Column Address every CLK (1-N Rule)

Power Down Mode

Auto Refresh and Self Refresh

Refresh Interval: 8192 cycles/64 ms

Available in 54 Pin TSOP II, 60 Ball WBGA and
SOC BGA

LVTTL Interface

Single +3.3 V

0.3 V Power Supply

Description

The V54C3256(16/80/40)4V(T/S/B) is a four

bank Synchronous DRAM organized as 4 banks x
4Mbit x 16, 4 banks x 8Mbit x 8, or 4 banks x 16Mbit
x 4. The V54C3256(16/80/40)4V(T/S/B) achieves
high speed data transfer rates up to 166 MHz by
employing a chip architecture that prefetches multi-
ple bits and then synchronizes the output data to a
system clock

All of the control, address, data input and output

circuits are synchronized with the positive edge of
an externally supplied clock.

Operating the four memory banks in an inter-

leaved fashion allows random access operation to
occur at higher rate than is possible with standard
DRAMs. A sequential and gapless data rate of up to
166 MHz is possible depending on burst length,
CAS latency and speed grade of the device.

Device Usage Chart

Operating

Temperature

Range

Package Outline

Access Time (ns)

Power

Temperature

Mark

T/S/B

7PC

8PC

Std.

C to 70

Blank

V54C3256(16/80/40)4V(T/S/B) Rev. 1.6 September 2002

MOSEL VITELIC

V54C3256(16/80/40)4V(T/S/B)

54 Pin Plastic TSOP-II
PIN CONFIGURATION

Top View

Pin Names

CLK

Clock Input

CKE

Clock Enable

Chip Select

RAS

Row Address Strobe

CAS

Column Address Strobe

Write Enable

Address Inputs

BA0, BA1

Bank Select

I/O

Data Input/Output

LDQM, UDQM

Data Mask

Power (+3.3V)

Ground

CCQ

Power for I/O's (+3.3V)

SSQ

Ground for I/O's

Not connected

V 54 C 3 25616 4 V A L T

Mosel Vitelic
Manufactured

SYNCHRONOUS
DRAM FAMILY

C=CMOS Family

3.3V, LVTTL INTERFACE

16Mx16(8K Refresh)

4 Banks

V=LVTTL

Component Rev Level A=0.17um

Special
Feature

L=Low Power

TSOP Component
Package

Speed
6 ns
7 ns
8 ns

Device
Number

B=0.14um

Description

Pkg.

Pin Count

TSOP-II

I/O

CCQ

I/O

SSQ

I/O

CCQ

I/O

SSQ

I/O

LDQM

CAS
RAS

BA0
BA1

I/O

SSQ

I/O

CCQ

I/O

SSQ

I/O

CCQ

I/O

NC
UDQM
CLK
CKE
A

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27

54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28

356164V-01

V54C3256(16/80/40)4V(T/S/B) Rev. 1.6 September 2002

MOSEL VITELIC

V54C3256(16/80/40)4V(T/S/B)

54 Pin Plastic TSOP-II
PIN CONFIGURATION

Top View

Pin Names

CLK

Clock Input

CKE

Clock Enable

Chip Select

RAS

Row Address Strobe

CAS

Column Address Strobe

Write Enable

Address Inputs

BA0, BA1

Bank Select

I/O

Data Input/Output

DQM

Data Mask

Power (+3.3V)

Ground

CCQ

Power for I/O's (+3.3V)

SSQ

Ground for I/O's

Not connected

V 54 C 3 25680 4 V A L T

Mosel Vitelic
Manufactured

SYNCHRONOUS
DRAM FAMILY

C=CMOS Family

3.3V, LVTTL INTERFACE

32Mx8(8K Refresh)

4 Banks

V=LVTTL

Component Rev Level A=0.17um

Special
Feature

L=Low Power

TSOP Component
Package

Speed
6 ns
7 ns
8 ns

Device
Number

B=0.14um

Description

Pkg.

Pin Count

TSOP-II

I/O

CCQ

I/O

SSQ

I/O

CCQ

I/O

SSQ

CAS
RAS

BA0
BA1

I/O

SSQ

NC
I/O

CCQ

NC
I/O

SSQ

NC
I/O

CCQ

NC
V

NC
DQM
CLK
CKE
A

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27

54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28

356804V-01

V54C3256(16/80/40)4V(T/S/B) Rev. 1.6 September 2002

MOSEL VITELIC

V54C3256(16/80/40)4V(T/S/B)

54 Pin Plastic TSOP-II
PIN CONFIGURATION

Top View

Pin Names

CCQ

I/O

SSQ

NC
NC

CCQ

I/O

SSQ

CAS
RAS

BA0
BA1

NC
V

SSQ

NC
I/O

CCQ

NC
NC
V

SSQ

NC
I/O

CCQ

NC
V

NC
DQM
CLK
CKE
A

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27

54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28

356404V-01

CLK

Clock Input

CKE

Clock Enable

Chip Select

RAS

Row Address Strobe

CAS

Column Address Strobe

Write Enable

Address Inputs

BA0, BA1

Bank Select

I/O

Data Input/Output

DQM

Data Mask

Power (+3.3V)

Ground

CCQ

Power for I/O's (+3.3V)

SSQ

Ground for I/O's

Not connected

V 54 C 3 25640 4 V A L T

Mosel Vitelic
Manufactured

SYNCHRONOUS
DRAM FAMILY

C=CMOS Family

3.3V, LVTTL INTERFACE

64Mx4(8K Refresh)

4 Banks

V=LVTTL

Component Rev Level A=0.17um

Special
Feature

L=Low Power

TSOP Component
Package

Speed
6 ns
7 ns
8 ns

Device
Number

B=0.14um

Description

Pkg.

Pin Count

TSOP-II

V54C3256(16/80/40)4V(T/S/B) Rev. 1.6 September 2002

MOSEL VITELIC

V54C3256(16/80/40)4V(T/S/B)

V 54 C 3 256XX 4 V B L S

Mosel Vitelic
Manufactured

SYNCHRONOUS
DRAM FAMILY

C=CMOS Family

3.3V, LVTTL INTERFACE

256Mb(8K Refresh)

4 Banks

V=LVTTL

Component Rev Level A=0.17um

Special
Feature

L=Low Power

SOC BGA

Device
Number

Speed
6 ns
7 ns
8 ns

B=0.14um

for 0.14um only

Component Package

Description

Pkg.

Pin Count

SOC BGA

DQ10

VDDQ

A12

A11

VDDQ

DQ11

VSSQ

DQ9

DQ8

VSS

DQMH

CLK

CKE

VSSQ

DQ13

DQ12

VSS

DQ14

DQ15

VSS

VDDQ

A12

A11

VDDQ

DQ5

VSSQ

DQ4

VSS

DQM

CLK

CKE

VSSQ

DQ6

VSS

DQ7

VSS

X16

VDDQ

A12

A11

VDDQ

VSSQ

DQ2

VSS

DQM

CLK

CKE

VSSQ

DQ3

VSS

VDDQ

DQ1

VDD

WE#

RAS#

BA1

DQ0

VDD

VSSQ

CAS#

CS#

BA0

VSSQ

A10

VDDQ

VDD

VDDQ

DQ3

VDD

WE#

RAS#

BA1

DQ1

VDD

VSSQ

CAS#

CS#

BA0

VSSQ

DQ2

A10

VDDQ

VDD

DQ0

VDDQ

DQ6

DQ7

VDD

WE#

RAS#

BA1

DQ2

DQ3

VDD

DQ5

VSSQ

DQML

CAS#

CS#

BA0

DQ1

VSSQ

DQ4

A10

VDDQ

VDD

DQ0

X16

TOP VIEW

(See Ball through the Package)

(60-Ball SOC BGA)

256 Mb SDRAM Ball Assignment

PIN A1 INDEX

MOSEL VITELIC

V54C3256(16/80/40)4V(T/S/B)

V54C3256(16/80/40)4V(T/S/B) Rev1.6 September

Capacitance*

= 0 to 70

C, V

= 3.3 V

0.3 V, f = 1 Mhz

Note:

Capacitance is sampled and not 100% tested.

Absolute Maximum Ratings*

Operating temperature range .................. 0 to 70 °C
Storage temperature range ................-55 to 150 °C
Input/output voltage.................. -0.3 to (V

+0.3) V

Power supply voltage .......................... -0.3 to 4.6 V
Power dissipation ..............................................1 W
Data out current (short circuit).......................50 mA

*Note:

Stresses above those listed under "Absolute Maximum
Ratings" may cause permanent damage of the device.
Exposure to absolute maximum rating conditions for
extended periods may affect device reliability.

Symbol

Parameter

Max. Unit

Input Capacitance (A0 to A12)

Input Capacitance

RAS, CAS, WE, CS, CLK, CKE, DQM

Output Capacitance (I/O)

6.5

CLK

Input Capacitance (CLK)

Block Diagram

Row decoder

Memory array

Bank 0

8192 x 512

x 16 bit

l
u

dec

oder

ens

ampl

i
f
i
e

r
&

)
bus

Row decoder

Memory array

Bank 1

8192 x 512

x16 bit

l
u

mn d

der

ampl

i
f
i
e

r
&

)

bus

Row decoder

Memory array

Bank 2

8192 x 512

x 16 bit

l
u

ens

ampl

i
f
i
e

r
&

)
bus

Row decoder

Memory array

Bank 3

8192 x 512

x 16 bit

l
u

ens

e ampl

i
f
i
e

r
&

(
O

)
bus

Input buffer

Output buffer

I/O

-I/O

Column address

counter

Column address

buffer

Row address

buffer

Refresh Counter

A0 - A12, BA0, BA1

A0 - A8, AP, BA0, BA1

Control logic & timing generator

Row Addresses

Column Addresses

UDQM

x16 Configuration

V54C3256(16/80/40)4V(T/S/B) Rev. 1.6 September 2002

MOSEL VITELIC

V54C3256(16/80/40)4V(T/S/B)

Block Diagram

x8 Configuration

Row decoder

Memory array

Bank 0

8192 x 1024

x 8 bit

l
u

dec

ode

ens

e am

i
f
i
e

r
&

)
bus

Row decoder

Memory array

Bank 1

8192 x 1024

x 8 bit

l
u

dec

oder

ens

e amp

l
i
f
i
e

r
&

)
bus

Row decoder

Memory array

Bank 2

8192 x 1024

x 8 bit

l
u

dec

oder

ens

e am

i
f
i
e

r
&

)
bus

Row decoder

Memory array

Bank 3

8192 x 1024

x 8 bit

l
u

mn dec

der

ens

e am

i
f
i
e

r
&

)
bus

Input buffer

Output buffer

I/O

-I/O

Column address

counter

Column address

buffer

Row address

buffer

Refresh Counter

A0 - A12, BA0, BA1

A0 - A9, AP, BA0, BA1

Control logic & timing generator

DQM

Row Addresses

Column Addresses

V54C3256(16/80/40)4V(T/S/B) Rev. 1.6 September 2002

MOSEL VITELIC

V54C3256(16/80/40)4V(T/S/B)

Block Diagram

x4 Configuration

Row decoder

Memory array

Bank 0

8192 x 2048

x 4 bit

l
u

ens

e am

i
f
i
e

r
&

)
bus

Row decoder

Memory array

Bank 1

8192 x 2048

x 4 bit

l
u

dec

oder

ens

e am

i
f
i
e

r
&

)
bus

Row decoder

Memory array

Bank 2

8192 x 2048

x 4 bit

l
u

dec

oder

ens

e am

i
f
i
e

r
&

)
bus

Row decoder

Memory array

Bank 3

8192 x 2048

x 4 bit

l
u

dec

oder

ens

e a

i
f
i
e

r
&

)
bu

Input buffer

Output buffer

I/O

-I/O

Column address

counter

Column address

buffer

Row address

buffer

Refresh Counter

A0 - A12, BA0, BA1

A0 - A9, A11, AP, BA0, BA1

Control logic & timing generator

DQM

Row Addresses

Column Addresses

V54C3256(16/80/40)4V(T/S/B) Rev. 1.6 September 2002

MOSEL VITELIC

V54C3256(16/80/40)4V(T/S/B)

Signal Pin Description

Pin

Type

Signal

Polarity

Function

CLK

Input

Pulse

Positive

Edge

The system clock input. All of the SDRAM inputs are sampled on the rising edge of the
clock.

CKE

Input

Level

Active High Activates the CLK signal when high and deactivates the CLK signal when low, thereby

initiates either the Power Down mode or the Self Refresh mode.

Input

Pulse

Active Low CS enables the command decoder when low and disables the command decoder when

high. When the command decoder is disabled, new commands are ignored but previous

operations continue.

RAS, CAS

Input

Pulse

Active Low When sampled at the positive rising edge of the clock, CAS, RAS, and WE define the

command to be executed by the SDRAM.

A0 - A11

Input

Level

During a Bank Activate command cycle, A0-A12 defines the row address (RA0-RA12)

when sampled at the rising clock edge.

During a Read or Write command cycle, A0-An defines the column address (CA0-CAn)

when sampled at the rising clock edge.CAn depends from the SDRAM organization:
· 64M x 4 SDRAM CA0CA9, CA11.

· 32M x 8 SDRAM CA0CA9.

· 16M x 16 SDRAM CA0CA8.

In addition to the column address, A10(=AP) is used to invoke autoprecharge operation

at the end of the burst read or write cycle. If A10 is high, autoprecharge is selected and
BA0, BA1 defines the bank to be precharged. If A10 is low, autoprecharge is disabled.

During a Precharge command cycle, A10(=AP) is used in conjunction with BA0 and BA1

to control which bank(s) to precharge. If A10 is high, all four banks will BA0 and BA1 are

used to define which bank to precharge.

BA0,

BA1

Input

Level

Selects which bank is to be active.

DQx

Input

Output

Level

Data Input/Output pins operate in the same manner as on conventional DRAMs.

LDQM

UDQM

Input

Pulse

Active High The Data Input/Output mask places the DQ buffers in a high impedance state when sam-

pled high. In Read mode, DQM has a latency of two clock cycles and controls the output

buffers like an output enable. In Write mode, DQM has a latency of zero and operates as

a word mask by allowing input data to be written if it is low but blocks the write operation
if DQM is high.

VCC, VSS

Supply

Power and ground for the input buffers and the core logic.

VCCQ

VSSQ

Supply

Isolated power supply and ground for the output buffers to provide improved noise

immunity.

V54C3256(16/80/40)4V(T/S/B) Rev. 1.6 September 2002

MOSEL VITELIC

V54C3256(16/80/40)4V(T/S/B)

Operation Definition

All of SDRAM operations are defined by states of control signals CS, RAS, CAS, WE, and DQM at the

positive edge of the clock. The following list shows the thruth table for the operation commands.

Notes:

V = Valid , x = Don't Care, L = Low Level, H = High Level

CKEn signal is input level when commands are provided, CKEn-1 signal is input level one clock before the commands
are provided.

These are state of bank designated by BS0, BS1 signals.

Power Down Mode can not entry in the burst cycle.

Operation

Device

State

CKE

n-1

CKE

RAS

CAS

DQM

A0-9,

A11,

A12

A10

BS0
BS1

Row Activate

Idle

Read

Active

Read w/Autoprecharge

Active

Write Active

Write with Autoprecharge

Active

Row Precharge

Any

Precharge All

Any

Mode Register Set

Idle

No Operation

Any

Device Deselect

Any

Auto Refresh

Idle

Self Refresh Entry

Idle

Self Refresh Exit

Idle

(Self Refr.)

Power Down Entry

Idle

Active

Power Down Exit

Any

(Power

Down)

Data Write/Output Enable

Active

Data Write/Output Disable

Active

V54C3256(16/80/40)4V(T/S/B) Rev. 1.6 September 2002

MOSEL VITELIC

V54C3256(16/80/40)4V(T/S/B)

Power On and Initialization

The default power on state of the mode register is

supplier specific and may be undefined. The
following power on and initialization sequence
guarantees the device is preconditioned to each
users specific needs. Like a conventional DRAM,
the Synchronous DRAM must be powered up and
initialized in a predefined manner. During power on,
all VCC and VCCQ pins must be built up
simultaneously to the specified voltage when the
input signals are held in the "NOP" state. The power
on voltage must not exceed VCC+0.3V on any of
the input pins or VCC supplies. The CLK signal
must be started at the same time. After power on,
an initial pause of 200

s is required followed by a

precharge of both banks using the precharge
command. To prevent data contention on the DQ
bus during power on, it is required that the DQM and
CKE pins be held high during the initial pause
period. Once all banks have been precharged, the
Mode Register Set Command must be issued to
initialize the Mode Register. A minimum of eight
Auto Refresh cycles (CBR) are also required.These
may be done before or after programming the Mode
Register. Failure to follow these steps may lead to
unpredictable start-up modes.

Programming the Mode Register

The Mode register designates the operation

mode at the read or write cycle. This register is di-
vided into 4 fields. A Burst Length Field to set the
length of the burst, an Addressing Selection bit to
program the column access sequence in a burst cy-
cle (interleaved or sequential), a CAS Latency Field
to set the access time at clock cycle and a Opera-
tion mode field to differentiate between normal op-
eration (Burst read and burst Write) and a special
Burst Read and Single Write mode. The mode set

operation must be done before any activate com-
mand after the initial power up. Any content of the
mode register can be altered by re-executing the
mode set command. All banks must be in pre-
charged state and CKE must be high at least one
clock before the mode set operation. After the mode
register is set, a Standby or NOP command is re-
quired. Low signals of RAS, CAS, and WE at the
positive edge of the clock activate the mode set op-
eration. Address input data at this timing defines pa-
rameters to be set as shown in the previous table.

Read and Write Operation

When RAS is low and both CAS and WE are high

at the positive edge of the clock, a RAS cycle starts.
According to address data, a word line of the select-
ed bank is activated and all of sense amplifiers as-
sociated to the wordline are set. A CAS cycle is
triggered by setting RAS high and CAS low at a
clock timing after a necessary delay, t

RCD

, from the

RAS timing. WE is used to define either a read
(WE = H) or a write (WE = L) at this stage.

SDRAM provides a wide variety of fast access

modes. In a single CAS cycle, serial data read or
write operations are allowed at up to a 125 MHz
data rate. The numbers of serial data bits are the
burst length programmed at the mode set operation,
i.e., one of 1, 2, 4, 8. Column addresses are seg-
mented by the burst length and serial data accesses
are done within this boundary. The first column ad-
dress to be accessed is supplied at the CAS timing
and the subsequent addresses are generated auto-
matically by the programmed burst length and its
sequence. For example, in a burst length of 8 with
interleave sequence, if the first address is `2', then
the rest of the burst sequence is 3, 0, 1, 6, 7, 4, and
5.

MOSEL VITELIC

V54C3256(16/80/40)4V(T/S/B)

V54C3256(16/80/40)4V(T/S/B) Rev1.6 September

Address Input for Mode Set (Mode Register Operation)

Similar to the page mode of conventional

DRAM's, burst read or write accesses on any col-
umn address are possible once the RAS cycle
latches the sense amplifiers. The maximum t

RAS

the refresh interval time limits the number of random
column accesses. A new burst access can be done
even before the previous burst ends. The interrupt
operation at every clock cycles is supported. When
the previous burst is interrupted, the remaining ad-
dresses are overridden by the new address with the
full burst length. An interrupt which accompanies

with an operation change from a read to a write is
possible by exploiting DQM to avoid bus contention.

When two or more banks are activated

sequentially, interleaved bank read or write
operations are possible. With the programmed
burst length, alternate access and precharge
operations on two or more banks can realize fast
serial data access modes among many different
pages. Once two or more banks are activated,
column to column interleave operation can be done
between different pages.

A11

A10 A9

Address Bus (Ax)

Burst Length

CAS Latency

Mode Register

CAS Latency

Latency

Reserve

Burst Length

Length

Sequential

Interleave

Reserve

Burst

Type

Type

Sequential

Interleave

Operation Mode

BA1 BA0 A11 A10 A9 A8 A7

Mode

Burst Read/Burst

Write

Burst Read/Single

Write

Operation Mode

BA0

BA1

V54C3256(16/80/40)4V(T/S/B) Rev. 1.6 September 2002

MOSEL VITELIC

V54C3256(16/80/40)4V(T/S/B)

Burst Length and Sequence:

Refresh Mode

SDRAM has two refresh modes, Auto Refresh

and Self Refresh. Auto Refresh is similar to the CAS
-before-RAS refresh of conventional DRAMs. All of
banks must be precharged before applying any re-
fresh mode. An on-chip address counter increments
the word and the bank addresses and no bank infor-
mation is required for both refresh modes.

The chip enters the Auto Refresh mode, when

RAS and CAS are held low and CKE and WE are
held high at a clock timing. The mode restores word
line after the refresh and no external precharge
command is necessary. A minimum tRC time is re-
quired between two automatic refreshes in a burst
refresh mode. The same rule applies to any access
command after the automatic refresh operation.

The chip has an on-chip timer and the Self Re-

fresh mode is available. It enters the mode when
RAS, CAS, and CKE are low and WE is high at a
clock timing. All of external control signals including
the clock are disabled. Returning CKE to high en-
ables the clock and initiates the refresh exit opera-
tion. After the exit command, at least one t

delay

is required prior to any access command.

DQM Function

DQM has two functions for data I/O read and

write operations. During reads, when it turns to
"high" at a clock timing, data outputs are disabled
and become high impedance after two clock delay
(DQM Data Disable Latency t

DQZ

). It also provides

a data mask function for writes. When DQM is acti-
vated, the write operation at the next clock is prohib-
ited (DQM Write Mask Latency t

DQW

= zero clocks).

Power Down

In order to reduce standby power consumption, a

power down mode is available. All banks must be
precharged and the necessary Precharge delay
(trp) must occur before the SDRAM can enter the
Power Down mode. Once the Power Down mode is
initiated by holding CKE low, all of the receiver cir-
cuits except CLK and CKE are gated off. The Power
Down mode does not perform any refresh opera-
tions, therefore the device can't remain in Power
Down mode longer than the Refresh period (tref) of
the device. Exit from this mode is performed by tak-
ing CKE "high". One clock delay is required for
mode entry and exit.

Auto Precharge

Two methods are available to precharge

SDRAMs. In an automatic precharge mode, the
CAS timing accepts one extra address, CA10, to
determine whether the chip restores or not after the
operation. If CA10 is high when a Read Command
is issued, the Read with Auto-Precharge function
is initiated. The SDRAM automatically enters the
precharge operation one clock before the last data
out for CAS latencies 2, two clocks for CAS laten-
cies 3 and three clocks for CAS latencies 4. If CA10
is high when a Write Command is issued, the Write

Burst

Length

Starting Address

(A2 A1 A0)

Sequential Burst Addressing
(decimal)

Interleave Burst Addressing
(decimal)

xx0
xx1

0, 1
1, 0

x00

x01
x10
x11

0, 1, 2, 3
1, 2, 3, 0
2, 3, 0, 1
3, 0, 1, 2

0, 1, 2, 3
1, 0, 3, 2
2, 3, 0, 1
3, 2, 1, 0

000
001
010
011
100
101
110
111

0 1 2 3 4 5 6 7
1 2 3 4 5 6 7 0
2 3 4 5 6 7 0 1
3 4 5 6 7 0 1 2
4 5 6 7 0 1 2 3
5 6 7 0 1 2 3 4
6 7 0 1 2 3 4 5
7 0 1 2 3 4 5 6

0 1 2 3 4 5 6 7
1 0 3 2 5 4 7 6
2 3 0 1 6 7 4 5
3 2 1 0 7 6 5 4
4 5 6 7 0 1 2 3
5 4 7 6 1 0 3 2
6 7 4 5 2 3 0 1
7 6 5 4 3 2 1 0

MOSEL VITELIC

V54C3256(16/80/40)4V(T/S/B)

V54C3256(16/80/40)4V(T/S/B) Rev1.6 September

with Auto-Precharge function is initiated. The
SDRAM automatically enters the precharge opera-
tion a time delay equal to t

(Write recovery time)

after the last data in.

Precharge Command

There is also a separate precharge command

available. When RAS and WE are low and CAS is
high at a clock timing, it triggers the precharge
operation. Three address bits, BA0, BA1 and A10
are used to define banks as shown in the following
list. The precharge command can be imposed one
clock before the last data out for CAS latency = 2,
two clocks before the last data out for CAS latency
= 3. Writes require a time delay twr from the last
data out to apply the precharge command.

Bank Selection by Address Bits:

Burst Termination

Once a burst read or write operation has been ini-

tiated, there are several methods in which to termi-
nate the burst operation prematurely. These
methods include using another Read or Write Com-
mand to interrupt an existing burst operation, use a
Precharge Command to interrupt a burst cycle and
close the active bank, or using the Burst Stop Com-
mand to terminate the existing burst operation but
leave the bank open for future Read or Write Com-
mands to the same page of the active bank. When
interrupting a burst with another Read or Write
Command care must be taken to avoid I/O conten-
tion. The Burst Stop Command, however, has the
fewest restrictions making it the easiest method to
use when terminating a burst operation before it has
been completed. If a Burst Stop command is issued
during a burst write operation, then any residual
data from the burst write cycle will be ignored. Data
that is presented on the I/O pins before the Burst
Stop Command is registered will be written to the
memory.

A10

BA0

BA1

Bank 0

Bank 1

Bank 2

Bank 3

all Banks

Recommended Operation and Characteristics for LV-TTL

= 0 to 70

C; V

= 0 V; V

CCQ

= 3.3 V

0.3 V

Note:
1.

All voltages are referenced to V

may overshoot to V

+ 2.0 V for pulse width of < 4ns with 3.3V. V

may undershoot to -2.0 V for pulse width < 4.0 ns with

3.3V. Pulse width measured at 50% points with amplitude measured peak to DC reference.

Parameter

Symbol

Limit Values

Unit

Notes

min.

max.

Input high voltage

2.0

Vcc+0.3

1, 2

Input low voltage

0.3

0.8

1, 2

Output high voltage (I

OUT

= 4.0 mA)

2.4

Output low voltage (I

OUT

= 4.0 mA)

0.4

Input leakage current, any input

(0 V < V

< 3.6 V, all other inputs = 0 V)

I(L)

Output leakage current

(DQ is disabled, 0 V < V

OUT

< V

)

O(L)

V54C3256(16/80/40)4V(T/S/B) Rev. 1.6 September 2002

MOSEL VITELIC

V54C3256(16/80/40)4V(T/S/B)

Operating Currents

= 0 to 70

C, V

= 3.3V

0.3V)

(Recommended Operating Conditions unless otherwise noted)

Notes:

These parameters depend on the cycle rate and these values are measured by the cycle rate under the minimum value of t

and

. Input signals are changed one time during t

These parameter depend on output loading. Specified values are obtained with output open.

Symbol

Parameter & Test Condition

Max.

Unit

Note

-6

-7 / -7PC

-8PC

ICC1

Operating Current
t

= t

RCMIN.

, t

= t

CKMIN

Active-precharge command cycling,

without Burst Operation

1 bank operation

250

230

210

ICC2P

Precharge Standby Current

in Power Down Mode

CS =V

, CKE

IL(max)

= min.

ICC2PS

= Infinity

ICC2N

Precharge Standby Current

in Non-Power Down Mode

CS =V

, CKE

IL(max)

= min.

ICC2NS

= Infinity

ICC3N

No Operating Current

= min, CS = V

IH(min)

bank ; active state ( 4 banks)

CKE

IH(MIN.)

ICC3P

CKE

IL(MAX.)

(Power down mode)

ICC4

Burst Operating Current

= min

Read/Write command cycling

170

150

120

7,8

ICC5

Auto Refresh Current

= min

Auto Refresh command cycling

270

240

220

ICC6

Self Refresh Current
Self Refresh Mode, CKE

0.2V

L-version

(A component rev)

1.7

L-version

(B component rev)

1.0

V54C3256(16/80/40)4V(T/S/B) Rev. 1.6 September 2002

MOSEL VITELIC

V54C3256(16/80/40)4V(T/S/B)

AC Characteristics

1,2, 3

= 0 to 70 °C; V

= 0 V; V

= 3.3 V ± 0.3 V, t

= 1 ns

Symbol

Parameter

Limit Values

Unit

Note

-6

-7PC

-7

-8PC

Min. Max. Min. Max. Min. Max. Min. Max.

Clock and Clock Enable

Clock Cycle Time

CAS Latency = 3

CAS Latency = 2

7.5

Clock Frequency
CAS Latency = 3

CAS Latency = 2

166

133

143

133

143

100

125

100

MHz

Access Time from Clock

CAS Latency = 3

CAS Latency = 2

5.4

2, 4

Clock High Pulse Width

2.5

Clock Low Pulse Width

2.5

Transition Tim

0.3

1.2

0.3

1.2

0.3

1.2

0.5

Setup and Hold Times

Input Setup Time

1.5

Input Hold Time

0.8

CKS

Input Setup Time

1.5

CKH

CKE Hold Time

0.8

RSC

Mode Register Set-up Time

Power Down Mode Entry Time

Common Parameters

RCD

Row to Column Delay Time

Row Precharge Time

RAS

Row Active Time

100K

100k

Row Cycle Time

RRD

Activate(a) to Activate(b) Command Period

CCD

CAS(a) to CAS(b) Command Period

CLK

Refresh Cycle

REF

Refresh Period (8192 cycles)

SREX

Self Refresh Exit Time

CLK

V54C3256(16/80/40)4V(T/S/B) Rev. 1.6 September 2002

MOSEL VITELIC

V54C3256(16/80/40)4V(T/S/B)

Notes for AC Parameters:

For proper power-up see the operation section of this data sheet.

AC timing tests have V

= 0.8V and V

= 2.0V with the timing referenced to the 1.4 V crossover point. The transition

time is measured between V

and V

. All AC measurements assume t

= 1ns with the AC output load circuit shown

in Figure 1.

If clock rising time is longer than 1 ns, a time (t

/2 0.5) ns has to be added to this parameter.

If t

is longer than 1 ns, a time (t

1) ns has to be added to this parameter.

These parameter account for the number of clock cycle and depend on the operating frequency of the clock, as
follows:

the number of clock cycle = specified value of timing period (counted in fractions as a whole number)

Self Refresh Exit is a synchronous operation and begins on the 2nd positive clock edge after CKE returns high.
Self Refresh Exit is not complete until a time period equal to tRC is satisfied once the Self Refresh Exit command
is registered.

Referenced to the time which the output achieves the open circuit condition, not to output voltage levels

Read Cycle

Data Out Hold Time

Data Out to Low Impedance Time

Data Out to High Impedance Time

DQZ

DQM Data Out Disable Latency

CLK

Write Cycle

Write Recovery Time

CLK

DQW

DQM Write Mask Latency

CLK

Symbol

Parameter

Limit Values

Unit

Note

-6

-7PC

-7

-8PC

Min. Max. Min. Max. Min. Max. Min. Max.

1.4V

tCS

tCH

tAC

tLZ

tOH

tHZ

CLK

COMMAND

OUTPUT

50 pF

I/O

Z=50 Ohm

+ 1.4 V

50 Ohm

VIH

VIL

Figure 1.

tCK

AC Characteristics

(Cont'd)

V54C3256(16/80/40)4V(T/S/B) Rev. 1.6 September 2002

MOSEL VITELIC

V54C3256(16/80/40)4V(T/S/B)

Timing Diagrams

1. Bank Activate Command Cycle

2. Burst Read Operation

3. Read Interrupted by a Read

4. Read to Write Interval

4.1 Read to Write Interval

4.2 Minimum Read to Write Interval

4.3 Non-Minimum Read to Write Interval

5. Burst Write Operation

6. Write and Read Interrupt

6.1 Write Interrupted by a Write

6.2 Write Interrupted by Read

7. Burst Write & Read with Auto-Precharge

7.1 Burst Write with Auto-Precharge

7.2 Burst Read with Auto-Precharge

8. Burst Termination

8.1 Termination of a Burst Write Operation

8.2 Termination of a Burst Write Operation

9. AC- Parameters

9.1 AC Parameters for a Write Timing

9.2 AC Parameters for a Read Timing

10. Mode Register Set

11. Power on Sequence and Auto Refresh (CBR)

12. Power Down Mode

13. Self Refresh (Entry and Exit)

14. Auto Refresh (CBR)

V54C3256(16/80/40)4V(T/S/B) Rev. 1.6 September 2002

MOSEL VITELIC

V54C3256(16/80/40)4V(T/S/B)

1. Bank Activate Command Cycle

(CAS latency = 3)

2. Burst Read Operation

(Burst Length = 4, CAS latency = 2, 3)

ADDRESS

CLK

COMMAND

NOP

Bank A

Row Addr.

Bank A

Activate

Write A

with Auto

Bank A

Col. Addr.

. . . . . . . . . .

Bank B

Activate

Bank A

Row Addr.

Bank A

Activate

RCD

: "H" or "L"

Precharge

RRD

Bank B

Row Addr.

COMMAND

READ A

NOP

DOUT A

CAS latency = 2

CK3,

I/O's

CAS latency = 3

DOUT A

NOP

CLK

CK2,

I/O's

DOUT A

V54C3256(16/80/40)4V(T/S/B) Rev. 1.6 September 2002

MOSEL VITELIC

V54C3256(16/80/40)4V(T/S/B)

3. Read Interrupted by a Read

(Burst Length = 4, CAS latency = 2, 3)

4.1 Read to Write Interval

(Burst Length = 4, CAS latency = 3)

COMMAND

READ A

READ B

NOP

CK2,

I/O's

CAS latency = 2

CK3,

I/O's

CAS latency = 3

NOP

CLK

DOUT B

DOUT A

DOUT B

DOUT A

COMMAND

NOP

READ A

NOP

WRITE B

NOP

DQM

DOUT A0

DIN B0

DIN B1

DIN B2

Must be Hi-Z before
the Write Command

I/O's

Minimum delay between the Read and Write Commands = 4+1 = 5 cycles

CLK

DQZ

DQW

: "H" or "L"

V54C3256(16/80/40)4V(T/S/B) Rev. 1.6 September 2002

MOSEL VITELIC

V54C3256(16/80/40)4V(T/S/B)

4.2 Minimum Read to Write Interval

(Burst Length = 4, CAS latency = 2)

4.3 Non-Minimum Read to Write Interval

(Burst Length = 4, CAS latency = 2, 3)

COMMAND

NOP

BANK A

NOP

READ A

WRITE A

NOP

DQM

DIN A0

DIN A1

DIN A2

DIN A3

Must be Hi-Z before
the Write Command

CK2,

I/O's

CAS latency = 2

CLK

NOP

ACTIVATE

1 Clk Interval

DQZ

DQW

: "H" or "L"

NOP

READ A

NOP

READ A

NOP

WRITE B

NOP

DQM

DIN B0

DIN B1

DIN B2

CK1,

I/O's

CAS latency = 2

CK2,

I/O's

CAS latency = 3

CLK

DOUT A0

COMMAND

DIN B0

DIN B1

DIN B2

DOUT A1

DOUT A0

Must be Hi-Z before

the Write Command

DQZ

DQW

: "H" or "L"

V54C3256(16/80/40)4V(T/S/B) Rev. 1.6 September 2002

MOSEL VITELIC

V54C3256(16/80/40)4V(T/S/B)

6.2 Write Interrupted by a Read

(Burst Length = 4, CAS latency = 2, 3)

7. Burst Write with Auto-Precharge

Burst Length = 2, CAS latency = 2, 3)

COMMAND

NOP

WRITE A

READ B

NOP

CK2,

I/O's

CAS latency = 2

DIN A0

CK3,

I/O's

CAS latency = 3

DIN A0

CLK

DOUT B3

DOUT B0

DOUT B1

DOUT B2

DOUT B3

don't care

DOUT B0

DOUT B1

DOUT B2

Input data must be removed from the I/O's at least one clock
cycle before the Read dataAPpears on the outputs to avoid
data contention.

COMMAND

NOP

WRITE A

Auto-Precharge

CLK

NOP

BANK A
ACTIVE

NOP

DIN A0

DIN A1

I/O's

CAS latency = 3

I/O's

CAS latency = 2

Begin Autoprecharge

Bank can be reactivated after trp

DIN A0

DIN A1

NOP

V54C3256(16/80/40)4V(T/S/B) Rev. 1.6 September 2002

MOSEL VITELIC

V54C3256(16/80/40)4V(T/S/B)

CLK

CKE

RAS

CAS

DQM

.
1

t
e

r

W

r
it

i
n

-
Z

Bur

t
L

engt

= 4,

CAS

t
enc

mma

i
t
h

to P

r
ec

har

and

ank

mman

ank

i
t
h

r
ec

har

and

ank

and

ank

mma

r
g

and

ank

t
i
v

t
e

and

egi

n A

to P

r
ec

har

ank

i
n

t
o

r
g

and

ank

CAx

V54C3256(16/80/40)4V(T/S/B) Rev. 1.6 September 2002

MOSEL VITELIC

V54C3256(16/80/40)4V(T/S/B)

CLK

CKE

I/O

RAS

CAS

DQM

Param

t
e

f
o

r R

e
ad T

i
m

i
n

-
Z

Bur

t
Leng

t
h

= 2,

CAS

Lat

cy = 2

RRD

mmand

ank

mmand

ank

and

ank

r
ec

har

and

ank

ead

mman

ead w

i
th

t
o

r
g

mmand

ank

egi

n A

r
g

ank

V54C3256(16/80/40)4V(T/S/B) Rev. 1.6 September 2002

MOSEL VITELIC

V54C3256(16/80/40)4V(T/S/B)

)

dom

Colum

(

i
t
h

i
n

)
(

)

Bur

t
Len

CAS

Lat

ency

= 2

CLK

CKE

I/O

RAS

CAS

DQM

T11

T12

T13

T14

T10

T16

T17

T18

T19

T15

T22

T20

T21

Hi-Z

Addr

Activate

Command

Bank A

CAx

Read

Command

Bank A

CAy

Read

Command

Bank A

Aw0

Aw1

Aw2

Aw3

Ax0

Ax1

Ay0

Ay1

Az0

Az1

Az2

Az3

Ay2

Ay3

CAw

Read

Command

Bank A

RAw

Precharge

Command

Bank A

Activate

Command

Bank A

CAz

Read

Command

Bank A

RAz

CK2

V54C3256(16/80/40)4V(T/S/B) Rev. 1.6 September 2002

MOSEL VITELIC

V54C3256(16/80/40)4V(T/S/B)

)

ndom

Colum

(

i
t
h

i
n

)
(

)

Bur

t
L

engt

= 4,

CAS

t
enc

CLK

CKE

I/O

RAS

CAS

T11

T12

T13

T14

T10

T16

T17

T18

T19

T15

T22

T20

T21

Hi-Z

Addr

Activate

Command

Bank A

CAx

Read

Command

Bank A

CAy

Read

Command

Bank A

Aw0

Aw1

Aw2

Aw3

Ax0

Ax1

Ay0

Ay1

Ay2

Ay3

CAw

Read

Command

Bank A

RAw

Precharge

Command

Bank A

Activate

Command

Bank A

CAz

Read

Command

Bank A

RAz

CK3

V54C3256(16/80/40)4V(T/S/B) Rev. 1.6 September 2002

MOSEL VITELIC

V54C3256(16/80/40)4V(T/S/B)

)

ndom

Colum

(
P

i
t
h

in s

)
(

)

Bur

t
L

engt

= 4,

CAS

t
enc

CLK

CKE

I/O

RAS

CAS

DQM

T11

T12

T13

T14

T10

T16

T17

T18

T19

T15

T22

T20

T21

Hi-Z

Addr

CBx

Write

Command

Bank B

CBy

Write

Command

Bank B

Precharge

Command

Bank B

DBw0

DBw3

DBw2

DBw1

DBx1

DBx0

DBy0

DBy3

DBy2

DBy1

DBz0

DBz3

DBz2

DBz1

CK2

Activate

Command

Bank B

CAx

Write

Command

Bank B

RAw

Activate

Command

Bank B

CBz

Write

Command

Bank B

RBz

Activate

Command

Bank B

CBz

Write

Command

Bank B

RBz

V54C3256(16/80/40)4V(T/S/B) Rev. 1.6 September 2002

MOSEL VITELIC

V54C3256(16/80/40)4V(T/S/B)

)

ndom

Colum

(
P

i
t
h

in s

)
(

)

Bur

t
L

engt

= 4,

CAS

t
enc

CLK

CKE

I/O

RAS

CAS

DQM

T11

T12

T13

T14

T10

T16

T17

T18

T19

T15

T22

T20

T21

Hi-Z

Addr

CBx

Write

Command

Bank B

CBy

Write

Command

Bank B

Precharge

Command

Bank B

DBw0

DBw3

DBw2

DBw1

DBx1

DBx0

DBy0

DBy3

DBy2

DBy1

DBz0

DBz1

CK3

Activate

Command

Bank B

CBz

Write

Command

Bank B

RBz

Activate

Command

Bank B

CBz

Write

Command

Bank B

RBz

V54C3256(16/80/40)4V(T/S/B) Rev. 1.6 September 2002

MOSEL VITELIC

V54C3256(16/80/40)4V(T/S/B)

.
1

ndom

Row

(

I
nt

r
l
e

i
ng Ba

)

(
1

)

Bur

t
Le

ngt

h =

CAS

Lat

enc

y =

CLK

CKE

I/O

RAS

CAS

A11(BS)

DQM

T11

T12

T13

T14

T10

T16

T17

T18

T19

T15

T22

T20

T21

Hi-Z

A10

A0 - A9

CBy

Read

Command

Bank B

Read

Command

Bank A

Bx0

Bx1

Bx2

Bx3

Bx4

Bx5

Bx6

Bx7

By0

By1

CK2

High

RCD

AC2

CAx

Precharge

Command

Bank B

Ax0

Ax1

Ax2

Ax3

Ax4

Ax5

Ax6

Ax7

Activate

Command

Bank B

RBx

Activate

Command

Bank A

RAx

CBx

Read

Command

Bank B

Activate

Command

Bank B

RBy

V54C3256(16/80/40)4V(T/S/B) Rev. 1.6 September 2002

MOSEL VITELIC

V54C3256(16/80/40)4V(T/S/B)

17.

2 R

t
e

r
l
e

avi

s) (2

f
2)

Bur

t
Le

ngt

h =

CAS

Lat

enc

y =

CLK

CKE

I/O

RAS

CAS

11(BS)

DQM

T11

T12

T13

T14

T10

T16

T17

T18

T19

T15

T22

T20

T21

Hi-Z

A10

A0 - A9

CBy

Read

Command

Bank B

By0

CK3

High

AC3

Activate

Command

Bank B

RBx

Activate

Command

Bank A

RAx

CBx

Read

Command

Bank B

Activate

Command

Bank B

RBy

RCD

Precharge

Command

Bank B

CAx

Read

Command

Bank A

Bx0

Bx1

Bx2

Bx3

Bx4

Bx5

Bx6

Bx7

Ax0

Ax1

Ax2

Ax3

Ax4

Ax5

Ax6

Ax7

Precharge

Command

Bank A

V54C3256(16/80/40)4V(T/S/B) Rev. 1.6 September 2002

MOSEL VITELIC

V54C3256(16/80/40)4V(T/S/B)

ndom

Row

Wri

t
e

(

I
nt

r
le

ing Ba

)
(

)

r
s

t
Lengt

h =

CAS

CLK

CKE

I/O

RAS

CAS

11(BS)

DQM

T11

T12

T13

T14

T10

T16

T17

T18

T19

T15

T22

T20

T21

Hi-Z

A10

A0 - A9

CK2

High

RCD

Write

Command

Bank A

CAy

DAx0

DAx3

DAx2

DAx1

DAx4

DAx7

DAx6

DAx5

DBx0

DBx3

DBx2

DBx1

DBx4

DBx7

DBx6

DBx5

DAy0

DAy3

DAy2

DAy1

DPL

Write

Command

Bank A

CAX

Activate

Command

Bank A

RAx

Activate

Command

Bank B

RBx

CBx

Precharge

Command

Bank A

Write

Command

Bank B

Activate

Command

Bank A

RAy

CAy

Precharge

Command

Bank B

Write

Command

Bank A

DAy4

DPL

V54C3256(16/80/40)4V(T/S/B) Rev. 1.6 September 2002

MOSEL VITELIC

V54C3256(16/80/40)4V(T/S/B)

ndom

Row

Wri

t
e

(

I
nt

r
le

ing Ba

)
(

)

r
s

t
Lengt

h =

CAS

CLK

CKE

I/O

RAS

CAS

A11(BS)

DQM

T11

T12

T13

T14

T10

T16

T17

T18

T19

T15

T22

T20

T21

Hi-Z

A10

A0 - A9

CK3

High

DAx0

DAx3

DAx2

DAx1

DAx4

DAx7

DAx6

DAx5

DBx0

DBx3

DBx2

DBx1

DBx4

DBx7

DBx6

DBx5

DAy2

DAy1

DAy0

Write

Command

Bank A

CAX

Activate

Command

Bank B

RBx

Activate

Command

Bank A

RAy

DAy3

DPL

CBx

Write

Command

Bank B

Precharge

Command

Bank A

Write

Command

Bank A

CAy

Precharge

Command

Bank B

DPL

RCD

Activate

Command

Bank A

RAx

V54C3256(16/80/40)4V(T/S/B) Rev. 1.6 September 2002

MOSEL VITELIC

V54C3256(16/80/40)4V(T/S/B)

r
e

r
ge

r
m

ina

t
ion of

Burs

t
(

)

Bur

t
L

engt

h =

S Lat

enc

= 2

CLK

CKE

I/O

RAS

CAS

DQM

T11

T12

T13

T14

T10

T16

T17

T18

T19

T15

T22

T20

T21

Hi-Z

Addr

CK2

Precharge

Command

Bank A

DAx0

DAx3

DAx2

DAx1

Precharge Termination

of a Write Burst. Write

data is masked.

Ay0

Ay1

Ay2

Precharge Termination

of a Read Burst.

Precharge

Command

Bank A

Activate

Command

Bank A

RAx

Write

Command

Bank A

CAx

CAy

Read

Command

Bank A

High

Activate

Command

Bank A

RAy

Activate

Command

Bank A

RAz

CAz

Read

Command

Bank A

Az0

Az1

Az2

Precharge

Command

Bank A

V54C3256(16/80/40)4V(T/S/B) Rev. 1.6 September 2002

MOSEL VITELIC

V54C3256(16/80/40)4V(T/S/B)

r
e

r
ge

r
m

ina

t
ion of

Burs

t
(

)

Bur

t
Leng

t
h

= 4,

CAS Lat

ency

= 3

CLK

CKE

I/O

RAS

CAS

T11

T12

T13

T14

T10

T16

T17

T18

T19

T15

T22

T20

T21

Hi-Z

Addr

CK3

Precharge

Command

Bank A

DAx0

Precharge Termination

of a Write Burst.

Write Data

is masked

Ay0

Ay1

Ay2

Precharge Termination

Precharge

Command

Bank A

Activate

Command

Bank A

RAx

Write

Command

Bank A

CAx

CAy

Read

Command

Bank A

High

Activate

Command

Bank A

RAy

Activate

Command

Bank A

RAz

of a Read Burst.

V54C3256(16/80/40)4V(T/S/B) Rev. 1.6 September 2002

MOSEL VITELIC

V54C3256(16/80/40)4V(T/S/B)

Complete List of Operation Commands

SDRAM Function Truth Table

CURRENT

STATE

RAS

CAS

Addr

ACTION

Idle

L
L

H
H

H
L

BS
BS

Op-

RA
AP

Code

NOP or Power Down

NOP

ILLEGAL

Row (&Bank) Active; Latch Row Address
NOP

Auto-Refresh or Self-Refresh

Mode reg. Access

Row Active

L
L

H
H

L
L

H
L

BS
BS

CA,AP
CA,AP

NOP

Begin Read; Latch CA; DetermineAP
Begin Write; Latch CA; DetermineAP

ILLEGAL

Precharge

ILLEGAL

Read

L
L

H
H

H
L

X
BS

X
X

CA,AP

NOP (Continue Burst to End;>Row Active)

NOP (Continue Burst to End;>Row Active)
Burst Stop Command > Row Active

Term Burst, New Read, DetermineAP

Term Burst, Start Write, DetermineAP

ILLEGAL

Term Burst, Precharge

ILLEGAL

Write

L
L

H
H

H
L

BS
BS

CA,AP

X
AP

NOP (Continue Burst to End;>Row Active)

Burst Stop Command > Row Active

Term Burst, Start Read, DetermineAP

Term Burst, New Write, DetermineAP

ILLEGAL

Term Burst, Precharge

ILLEGAL

Read

with

Auto

Precharge

L
L

H
H

L
L

H
L

BS
X

X
X

NOP (Continue Burst to End;> Precharge)

ILLEGAL

V54C3256(16/80/40)4V(T/S/B) Rev. 1.6 September 2002

MOSEL VITELIC

V54C3256(16/80/40)4V(T/S/B)

SDRAM FUNCTION TRUTH TABLE(continued)

CURRENT

STATE

RAS

CAS

Addr

ACTION

Write

with
Auto

Precharge

L
L

H
H

H
L

X
BS

X
X

NOP (Continue Burst to End;> Precharge)

NOP (Continue Burst to End;> Precharge)
ILLEGAL

ILLEGAL

Precharging

L
L

H
L

L
X

BS
X

AP
X

NOP;> Idle after tRP

ILLEGAL

NOP

ILLEGAL

Row

Activating

L
L

H
H

H
L

BS
BS

X
AP

NOP;> Row Active after tRCD

ILLEGAL

Write

Recovering

L
L

H
L

L
H

X
H

BS
BS

X
X

NOP

ILLEGAL

Refreshing

L
L

H
H

H
L

L
X

X
X

NOP;> Idle after tRC

ILLEGAL
ILLEGAL

ILLEGAL

Mode

Accessing

L
L

H
H

H
L

L
X

X
X

NOP

ILLEGAL
ILLEGAL

ILLEGAL

V54C3256(16/80/40)4V(T/S/B) Rev. 1.6 September 2002

MOSEL VITELIC

V54C3256(16/80/40)4V(T/S/B)

Clock Enable (CKE) Truth Table:

Abbreviations:

RA = Row Address BS = Bank Address

CA = Column Address AP = Auto Precharge

Notes for SDRAM function truth table:

1. Current State is state of the bank determined by BS. All entries assume that CKE was active (HIGH) during the preceding clock cycle.
2. Illegal to bank in specified state; Function may be legal in the bank indicated by BS, depending on the state of that bank.
3. Must satisfy bus contention, bus turn around, and/or write recovery requirements.
4. NOP to bank precharging or in Idle state. May precharge bank(s) indicated by BS (andAP).
5. Illegal if any bank is not Idle.
6. CKE Low to High transition will re-enable CLK and other inputs asynchronously. A minimum setup time must be satisfied before any

command other than EXIT.

7. Power-Down and Self-Refresh can be entered only from the All Banks Idle State.
8. Must be legal command as defined in the SDRAM function truth table.

STATE(n)

CKE

n-1

CKE

RAS

CAS

Addr

ACTION

Self-Refresh

L
L

H
H

L
L

X
X

INVALID

EXIT Self-Refresh, Idle after tRC

ILLEGAL

ILLEGAL
ILLEGAL

NOP (Maintain Self-Refresh)

Power-Down

L
L

H
H

L
L

H
H

L
X

X
X

INVALID

EXIT Power-Down, > Idle.

ILLEGAL
ILLEGAL

ILLEGAL

NOP (Maintain Low-Power Mode)

All. Banks

Idle

H
H

L
L

H
H

X
X

Refer to the function truth table

Enter Power- Down

Enter Power- Down
ILLEGAL

ILLEGAL

Enter Self-Refresh

ILLEGAL

NOP

V54C3256(16/80/40)4V(T/S/B) Rev. 1.6 September 2002

MOSEL VITELIC

V54C3256(16/80/40)4V(T/S/B)

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