MOSEL VITELIC

V54C33316G2V
166/143 MHz 3.3 VOLT
ULTRA HIGH PERFORMANCE
2M X 16 SDRAM 2 BANKS X 1 Mbit X 16

V54C33316G2V Rev. 1.5 September 1999

PRELIMINARY

V54C33316G2V

-6

-7

-8

-10

Unit

Clock Frequency (t

)

166

143

125

100

MHz

Latency

clocks

Cycle Time (t

)

Access Time (t

)

5.4

Features

JEDEC Standard 3.3V Power Supply

The V54C33316G2V is ideally suited for high
performance graphics peripheral applications

Single Pulsed RAS Interface

Programmable CAS Latency: 2, 3

All Inputs are sampled at the positive going edge
of clock

Programmable Wrap Sequence: Sequential or
Interleave

Programmable Burst Length: 1, 2, 4, 8 and Full
Page for Sequential and 1, 2, 4, 8 for Interleave

UDQM and LDQM for byte masking

Auto & Self Refresh

2K Refresh Cycles/32 ms

Burst Read with Single Write Operation

Description

The V54C33316G2V is a 33,554,432 bits syn-

chronous high data rate DRAM organized as 2 x
1,048,576 words by 16 bits. The device is designed
to comply with JEDEC standards set for synchro-
nous DRAM products, both electrically and me-
chanically. Synchronous design allows precise
cycle control with the system clock. The CAS laten-
cy, burst length and burst sequence must be pro-
grammed into device prior to access operation.

V54C33316G2V Rev. 1.5 September 1999

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V54C33316G2V

50 Pin Plastic TSOP-II

PIN CONFIGURATION

Top View

Pin Names

I/O

SSQ

I/O

CCQ

I/O

SSQ

I/O

CCQ

LDQM

CAS
RAS

I/O

SSQ

I/O

CCQ

I/O

SSQ

I/O

CCQ

NC
UDQM
CLK
CKE
A

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25

50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26

V54C33316G2V-01

CLK

Clock Input

CKE

Clock Enable

Chip Select

RAS

Row Address Strobe

CAS

Column Address Strobe

Write Enable

�A

Address Inputs

Bank Select

I/O

�I/O

Data Input/Output

LDQM, UDQM

Data Mask

Power (+3.3V)

Ground

CCQ

Power for I/O's (+3.3V)

SSQ

Ground for I/O's

Not connected

V54C33316G2V Rev. 1.5 September 1999

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V54C33316G2V

Signal Pin Description

Pin

Name

Input Function

CLK

Clock Input

System clock input. Active on the positive rising edge to sample all inptus

CKE

Clock Enable

Activates the CLK signal when high and deactivates the CLK when low.
CKE low initiates the power down mode, suspend mode, or the self re-
fresh mode

Chip Select

Disables or enables device operation by masking or enabling all inputs
except CLK, CKE and DQMi

RAS

Row Address Strobe

Latches row addresses on the positive edge of CLK with RAS low. En-
ables row access & precharge

CAS

Column Address Strobe

Latches column addresses on the positive edge of CLK with CAS low.
Enables column access

Write Enable

Enables write operation

-A

Address

During a bank activate command, A

-A

defines the row address.

|During a read or write command, A

-A

defines the column address. In

addition to the column address A

is used to invoke auto precharge BA

define the bank to be precharged. A

is low, auto precharge is disabled

during a precharge cycle, If A

is high, both bank will be precharged, if

is low, the BA is used to decide which bank to precharge

Bank Select

Selects which bank to activate. BA low select bank A and high selects
bank B

I/O

-I/O

Data Input/Output

Data inputs/output are multiplexed on the same pins

UDQM, LDQM

Data Input/Output Mask

Makes data output Hi-Z. Blocks data input when DQM is active

VDD/VSS

Power Supply/Ground

Power Supply. +3.3V

�

0.3V/ground

VDDQ/VSSQ

Data Output Power/Ground

Provides isolated power/ground to DQs for improved noise immunity

No Connection

V54C33316G2V Rev. 1.5 September 1999

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V54C33316G2V

Address Input for Mode Set (Mode Register Operation)

Power On and Initialization

The default power on state of the mode register is

supplier specific and may be undefined. The
following power on and initialization sequence
guarantees the device is preconditioned to each
users specific needs. Like a conventional DRAM,
the Synchronous DRAM must be powered up and
initialized in a predefined manner. During power on,
all VCC and VCCQ pins must be built up
simultaneously to the specified voltage when the
input signals are held in the "NOP" state. The power
on voltage must not exceed VCC+0.3V on any of
the input pins or VCC supplies. The CLK signal
must be started at the same time. After power on,
an initial pause of 200

�

s is required followed by a

precharge of both banks using the precharge
command. To prevent data contention on the DQ
bus during power on, it is required that the DQM and
CKE pins be held high during the initial pause
period. Once all banks have been precharged, the
Mode Register Set Command must be issued to
initialize the Mode Register. A minimum of eight
Auto Refresh cycles (CBR) are also required.These
may be done before or after programming the Mode
Register. Failure to follow these steps may lead to
unpredictable start-up modes.

Programming the Mode Register

The Mode register designates the operation

mode at the read or write cycle. This register is di-
vided into 4 fields. A Burst Length Field to set the
length of the burst, an Addressing Selection bit to
program the column access sequence in a burst cy-
cle (interleaved or sequential), a CAS

Latency

Field

to set the access time at clock cycle and a Opera-
tion mode field to differentiate between normal op-
eration (Burst read and burst Write) and a special
Burst Read and Single Write mode. The mode set
operation must be done before any activate com-
mand after the initial power up. Any content of the
mode register can be altered by re-executing the
mode set command. All banks must be in pre-
charged state and CKE must be high at least one
clock before the mode set operation. After the mode
register is set, a Standby or NOP command is re-
quired. Low signals of RAS, CAS, and WE and at
the positive edge of the clock activate the mode set
operation. Address input data at this timing defines
parameters to be set as shown in the previous table.

Address Bus (Ax)

Burst Length

CAS Latency

Mode Register

CAS Latency

Latency

Reserve

Burst Length

Length

Sequential

Interleave

Reserve

Full Page

Reserve

Burst

Type

Type

Sequential

Interleave

Operation Mode

Operation Mode

A11

A10

Mode

Burst read/Burst write

Burst read/single write

A10

A11

V54C33316G2V Rev. 1.5 September 1999

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V54C33316G2V

Read and Write Operation

When RAS is low and both CAS and WE are high

at the positive edge of the clock, a RAS cycle starts.
According to address data, a word line of the select-
ed bank is activated and all of sense amplifiers as-
sociated to the wordline are set. A CAS cycle is
triggered by setting RAS high and CAS low at a
clock timing after a necessary delay, t

RCD

, from the

RAS timing. WE is used to define either a read
(WE = H) or a write (WE = L) at this stage.

SDRAM provides a wide variety of fast access

modes. In a single CAS cycle, serial data read or
write operations are allowed at up to a 166 MHz
data rate. The numbers of serial data bits are the
burst length programmed at the mode set opera-
tion, i.e., one of 1, 2, 4, 8 and full page. Column ad-
dresses are segmented by the burst length and
serial data accesses are done within this boundary.
The first column address to be accessed is supplied
at the CAS timing and the subsequent addresses
are generated automatically by the programmed
burst length and its sequence. For example, in a
burst length of 8 with interleave sequence, if the first
address is `2', then the rest of the burst sequence is
3, 0, 1, 6, 7, 4, and 5.

Full page burst operation is only possible using

the sequential burst type and page length is a func-
tion of the I/O organisation and column addressing.
Full page burst operation do not self terminate once
the burst length has been reached. In other words,
unlike burst length of 2, 3 or 8, full page burst con-
tinues until it is terminated using another command.

Similar to the page mode of conventional

DRAM's, burst read or write accesses on any col-
umn address are possible once the RAS cycle
latches the sense amplifiers. The maximum t

RAS

the refresh interval time limits the number of random
column accesses. A new burst access can be done
even before the previous burst ends. The interrupt
operation at every clock cycles is supported. When
the previous burst is interrupted, the remaining ad-
dresses are overridden by the new address with the
full burst length. An interrupt which accompanies
with an operation change from a read to a write is
possible by exploiting DQM to avoid bus contention.

When two or more banks are activated

sequentially, interleaved bank read or write
operations are possible. With the programmed
burst length, alternate access and precharge
operations on two or more banks can realize fast
serial data access modes among many different
pages. Once two or more banks are activated,
column to column interleave operation can be done
between different pages.

Refresh Mode

SDRAM has two refresh modes, Auto Refresh

and Self Refresh. Auto Refresh is similar to the CAS
-before-RAS refresh of conventional DRAMs. All of
banks must be precharged before applying any re-
fresh mode. An on-chip address counter increments
the word and the bank addresses and no bank infor-
mation is required for both refresh modes.

Burst Length and Sequence:

Burst

Length

Starting Address

(A2 A1 A0)

Sequential Burst Addressing
(decimal)

Interleave Burst Addressing
(decimal)

xx0
xx1

0, 1
1, 0

x00

x01
x10
x11

0, 1, 2, 3
1, 2, 3, 0
2, 3, 0, 1
3, 0, 1, 2

0, 1, 2, 3
1, 0, 3, 2
2, 3, 0, 1
3, 2, 1, 0

000
001
010
011
100
101
110
111

0 1 2 3 4 5 6 7
1 2 3 4 5 6 7 0
2 3 4 5 6 7 0 1
3 4 5 6 7 0 1 2
4 5 6 7 0 1 2 3
5 6 7 0 1 2 3 4
6 7 0 1 2 3 4 5
7 0 1 2 3 4 5 6

0 1 2 3 4 5 6 7
1 0 3 2 5 4 7 6
2 3 0 1 6 7 4 5
3 2 1 0 7 6 5 4
4 5 6 7 0 1 2 3
5 4 7 6 1 0 3 2
6 7 4 5 2 3 0 1
7 6 5 4 3 2 1 0

Full

Page

nnn

Cn, Cn+1, Cn+2,.....

not supported

V54C33316G2V Rev. 1.5 September 1999

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V54C33316G2V

The chip enters the Auto Refresh mode, when

RAS and CAS are held low and CKE and WE are
held high at a clock timing. The mode restores word
line after the refresh and no external precharge
command is necessary. A minimum tRC time is re-
quired between two automatic refreshes in a burst
refresh mode. The same rule applies to any access
command after the automatic refresh operation.

The chip has an on-chip timer and the Self Re-

fresh mode is available. It enters the mode when
RAS, CAS, and CKE are low and WE is high at a
clock timing. All of external control signals including
the clock are disabled. Returning CKE to high en-
ables the clock and initiates the refresh exit opera-
tion. After the exit command, at least one t

delay

is required prior to any access command.

DQM Function

DQM has two functions for data I/O read and

write operations. During reads, when it turns to
"high" at a clock timing, data outputs are disabled
and become high impedance after two clock delay
(DQM Data Disable Latency t

DQZ

). It also provides

a data mask function for writes. When DQM is acti-
vated, the write operation at the next clock is prohib-
ited (DQM Write Mask Latency t

DQW

= zero clocks).

DQM is used for device selection, byte selection
and bus control in a memory system. LDQM con-
trols DQ0 to DQ7, UDQM controls DQ8 to DQ15.

Suspend Mode

During normal access mode, CKE is held high en-

abling the clock. When CKE is low, it freezes the in-
ternal clock and extends data read and write
operations. One clock delay is required for mode
entry and exit (Clock Suspend Latency t

CSL

Power Down

In order to reduce standby power consumption, a

power down mode is available. All banks must be
precharged and the necessary Precharge delay
(trp) must occur before the SDRAM can enter the
Power Down mode. Once the Power Down mode is
initiated by holding CKE low, all of the receiver cir-
cuits except CLK and CKE are gated off. The Power
Down mode does not perform any refresh opera-
tions, therefore the device can't remain in Power
Down mode longer than the Refresh period (tref) of
the device. Exit from this mode is performed by tak-
ing CKE "high". One clock delay is required for
mode entry and exit.

Auto Precharge

Two methods are available to precharge

SDRAMs. In an automatic precharge mode, the
CAS timing accepts one extra address, A10, to de-
termine whether the chip restores or not after the
operation. If A10 is high when a Read Command is
issued, the

Read with Auto-Precharge

function is

initiated. The SDRAM automatically enters the pre-
charge operation one clock before the last data out
for CAS latencies 2, two clocks for CAS latencies 3.
If A10 is high when a Write Command is issued, the

Write with Auto-Precharge

function is initiated.

The SDRAM automatically enters the precharge op-
eration a time delay equal to t

(Write recovery

time) after the last data in.

Precharge Command

There is also a separate precharge command

available. When RAS and WE are low and CAS is
high at a clock timing, it triggers the precharge op-
eration. With A9 being low, the BA is used select
bank to precharge. The precharge command can
be imposed one clock before the last data out for
CAS latency = 2, two clocks before the last data out
for CAS latency = 3. Writes require a time delay twr
from the last data out to apply the precharge com-
mand.

Burst Termination

Once a burst read or write operation has been ini-

tiated, there are several methods in which to termi-
nate the burst operation prematurely. These
methods include using another Read or Write Com-
mand to interrupt an existing burst operation, use a
Precharge Command to interrupt a burst cycle and
close the active bank, or using the Burst Stop Com-
mand to terminate the existing burst operation but
leave the bank open for future Read or Write Com-
mands to the same page of the active bank. When
interrupting a burst with another Read or Write
Command care must be taken to avoid I/O conten-
tion. The Burst Stop Command, however, has the
fewest restrictions making it the easiest method to
use when terminating a burst operation before it has
been completed. If a Burst Stop command is issued
during a burst write operation, then any residual
data from the burst write cycle will be ignored. Data
that is presented on the I/O pins before the Burst
Stop Command is registered will be written to the
memory.

MOSEL VITELIC

V54C33316G2V

V54C33316G2V Rev. 1.5 September 1999

Absolute Maximum Ratings*

Operating temperature range ................. 0 to 70

�

Storage temperature range................ -55 to 150

�

Input/output voltage ..................-0.3 to (V

+0.3) V

Power supply voltage...........................-0.3 to 4.6 V
Power dissipation.............................................. 1 W
Data out current (short circuit) ...................... 50 mA

*Note:

Stresses above those listed under "Absolute Maximum
Ratings" may cause permanent damage of the device.
Exposure to absolute maximum rating conditions for
extended periods may affect device reliability.

Recommended Operation and Characteristics

= 0 to 70

�

C; V

= 0 V; V

CCQ

= 3.3 V

�

0.3 V

Note:

All voltages are referenced to V

may overshoot to V

+ 2.0 V for pulse width of < 4ns

with 3.3V. V

may undershoot to -2.0 V for pulse width < 4.0

Parameter

Symbol

Limit Values

Unit

Notes

min.

max.

Input high voltage

2.0

Vcc+0.3

1, 2

Input low voltage

� 0.3

0.8

1, 2

Output high voltage (I

OUT

= � 2.0 mA)

2.4

�

Output low voltage (I

OUT

= 2.0 mA)

�

0.4

Input leakage current, any input
(0 V < V

< 3.6 V, all other inputs = 0 V)

I(L)

� 5

�

Output leakage current
(DQ is disabled, 0 V < V

OUT

< V

)

O(L)

� 5

�

V54C33316G2V Rev. 1.5 September 1999

MOSEL VITELIC

V54C33316G2V

ns with 3.3V. Pulse width measured at 50% points with am-
plitude measured peak to DC reference.

Operating Currents

= 0 to 70

�

C, V

= 3.3V

�

0.3V)

(Recommended Operating Conditions unless otherwise noted)

Notes:

These parameters depend on the cycle rate and these values are measured by the cycle rate under the minimum value of t

and

. Input signals are changed one time during t

These parameter depend on output loading. Specified values are obtained with output open.

Symbol

Parameter & Test Condition

Max.

Unit

Note

-6

-7

-8

-10

ICC1

Operating Current
t

= t

RCMIN.

, t

= t

CKMIN

Active-precharge command cycling,
without Burst Operation

1 bank operation

230

210

190

170

ICC2P

Precharge Standby Current
in Power Down Mode

CS =V

, CKE

IL(max)

= min.

ICC2PS

= Infinity

ICC2N

Precharge Standby Current
in Non-Power Down Mode

CS =V

, CKE

IL(max)

= min.

ICC2NS

= Infinity

ICC3P

Active Standby Current in
Power-down mode

CKE

(max), t

= min

ICC3PS

CKE

(max), t

= infinity

ICC3N

Active Standby Current in
non Power-down mode

CKE

(max), t

= min

ICC3PS

CKE

(max), t

= infinity

ICC4

Burst Operating Current
t

= min

Read/Write command cycling

CL = 3

310

280

250

210

7,8

CL = 2

180

170

ICC5

Auto Refresh Current
t

= min

Auto Refresh command cycling

150

120

110

ICC6

Self Refresh Current
Self Refresh Mode, CKE=0.2V

L-Power

400

�

V54C33316G2V Rev. 1.5 September 1999

MOSEL VITELIC

V54C33316G2V

AC Characteristics

(1,2,3)

= 0 to 70

�

C; V

= 0 V; V

= 3.3 V

�

0.3 V, t

= 1 ns

Symbol

Parameter

Limit Values

Unit

-6

-7

-8

-10

Min. Max. Min. Max. Min. Max. Min. Max.

Clock and Clock Enable

Clock Cycle Time
CAS Latency = 3
CAS Latency = 2

�
�

10
13

�
�

ns
ns

Clock Frequency
CAS Latency = 3
CAS Latency = 2

�
�

166
100

�
�

143
100

�
�

125
100

�
�

100

MHz
MHz

Access Time from Clock
CAS Latency = 3
CAS Latency = 2

�
�

5.4

�
�

5.4

�
�

6
7

�
�

7
9

ns
ns

Clock High Pulse Width

2.5

�

2.5

�

3.5

�

Clock Low Pulse Width

2.5

�

2.5

�

3.5

�

Transition time

Setup and Hold Times

Command Setup Time

�

2.5

�

2.5

�

Address Setup Time

�

2.5

�

2.5

�

Data In Setup Time

�

2.5

�

2.5

�

CKS

CKE Setup Time

�

2.5

�

2.5

�

Command Hold Time

�

Address Hold Time

�

Data In Hold Time

�

CKH

CKE Hold Time

�

Common Parameters

RCD

Row to Column Delay Time

�

RAS

Row Active Time

100K

100k

Row Cycle Time

�

Row Precharge Time

�

RRD

Activate(a) to Activate(b) Command
period

�

CCD

CAS(a) to CAS(b) Command period

�

CLK

RCS

Mode Register Set-up time

�

Power Down Mode Entry Time

�

V54C33316G2V Rev. 1.5 September 1999

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V54C33316G2V

Refresh Cycle

REF

Refresh Period (2048 cycles)

�

SREX

Self Refresh Exit Time

2 CLK + t

Read Cycle

2.5

�

2.5

�

2.5

�

2.5

�

CAS Latency = 3
CAS Latency = 2

�
�

5.4

�
�

5.4

�
�

6
7

�
�

7
8

DQZ

DQM Data Out Disable Latency

�

CLK

Write Cycle

Write Recovery Time
CAS Latency = 3
CAS Latency = 2

�
�

10
13

�
�

ns
ns

DQW

DQM Write Mask Latency

�

CLK

BWC

Block Write Cycle Time

�

CLK

AC Characteristics

(1,2,3)

(Continued)

= 0 to 70

�

C; V

= 0 V; V

= 3.3 V

�

0.3 V, t

= 1 ns

Symbol

Parameter

Limit Values

Unit

-6

-7

-8

-10

Min. Max. Min. Max. Min. Max. Min. Max.

V54C33316G2V Rev. 1.5 September 1999

MOSEL VITELIC

V54C33316G2V

Notes for AC Parameters:

For proper power-up see the operation section of this data sheet.

AC timing tests have V

= 0.8V and V

= 2.0V with the timing referenced to the 1.4 V crossover point. The transition

time is measured between V

and V

. All AC measurements assume t

= 1ns with the AC output load circuit shown

in Figure 1.

If clock rising time is longer than 1 ns, a time (t

/2 � 0.5) ns has to be added to this parameter.

If t

is longer than 1 ns, a time (t

� 1) ns has to be added to this parameter.

These parameter account for the number of clock cycle and depend on the operating frequency of the clock, as
follows:

the number of clock cycle = specified value of timing period (counted in fractions as a whole number)

Self Refresh Exit is a synchronous operation and begins on the 2nd positive clock edge after CKE returns high.
Self Refresh Exit is not complete until a time period equal to tRC is satisfied once the Self Refresh Exit command
is registered.

Referenced to the time which the output achieves the open circuit condition, not to output voltage levels

1.4V

tCS

tCH

tAC

tLZ

tOH

tHZ

CLK

COMMAND

OUTPUT

50 pF

I/O

Z=50 Ohm

+ 1.4 V

50 Ohm

VIH

VIL

Figure 1.

tCK

V54C33316G2V Rev. 1.5 September 1999

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V54C33316G2V

Timing Diagrams

1. Bank Activate Command Cycle

2. Burst Read Operation

3. Read Interrupted by a Read

4. Read to Write Interval

4.1 Read to Write Interval

4.2 Minimum Read to Write Interval

4.3 Non-Minimum Read to Write Interval

5. Burst Write Operation

6. Write and Read Interrupt

6.1 Write Interrupted by a Write

6.2 Write Interrupted by Read

7. Burst Write & Read with Auto-Precharge

7.1 Burst Write with Auto-Precharge

7.2 Burst Read with Auto-Precharge

8. Burst Termination

8.1 Termination of a Full Page Burst Write Operation

8.2 Termination of a Full Page Burst Write Operation

9. AC- Parameters

9.1 AC Parameters for a Write Timing

9.2 AC Parameters for a Read Timing

10. Mode Register Set

11. Power on Sequence and Auto Refresh (CBR)

12. Clock Suspension (using CKE)

12.1 Clock Suspension During Burst Read CAS Latency = 2

12. 2 Clock Suspension During Burst Read CAS Latency = 3

12. 3 Clock Suspension During Burst Write CAS Latency = 2

12. 4 Clock Suspension During Burst Write CAS Latency = 3

13. Power Down Mode and Clock Suspend

14. Self Refresh (Entry and Exit)

15. Auto Refresh (CBR)

V54C33316G2V Rev. 1.5 September 1999

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V54C33316G2V

6.2 Write Interrupted by a Read

(Burst Length = 4, CAS latency = 2, 3)

7. Burst Write with Auto-Precharge

Burst Length = 2, CAS latency = 2, 3)

COMMAND

NOP

WRITE A

READ B

NOP

CK2,

I/O's

CAS latency = 2

DIN A0

CK3,

I/O's

CAS latency = 3

DIN A0

CLK

DOUT B3

DOUT B0

DOUT B1

DOUT B2

DOUT B3

don't care

DOUT B0

DOUT B1

DOUT B2

Input data must be removed from the I/O's at least one clock
cycle before the Read dataAPpears on the outputs to avoid
data contention.

COMMAND

NOP

WRITE A

Auto-Precharge

CLK

NOP

BANK A
ACTIVE

NOP

DIN A

I/O's

CAS latency = 3

Begin Autoprecharge

Bank can be reactivated after trp

DIN A

NOP

I/O's

CAS latency = 2

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WORLDWIDE OFFICES

V54C33316G2V

The information in this document is subject to change without
notice.

MOSEL VITELIC makes no commitment to update or keep cur-
rent the information contained in this document. No part of this
document may be copied or reproduced in any form or by any
means without the prior written consent of MOSEL-VITELIC.

MOSEL VITELIC subjects its products to normal quality control
sampling techniques which are intended to provide an assurance
of high quality products suitable for usual commercial applica-
tions. MOSEL VITELIC does not do testing appropriate to provide
100% product quality assurance and does not assume any liabil-
ity for consequential or incidental arising from any use of its prod-
ucts. If such products are to be used in applications in which
personal injury might occur from failure, purchaser must do its
own quality assurance testing appropriate to such applications.

9/99
Printed in U.S.A.

MOSEL VITELIC

3910 N. First Street, San Jose, CA 95134-1501 Ph: (408) 433-6000 Fax: (408) 433-0952 Tlx: 371-9461

U.S. SALES OFFICES

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3910 NORTH FIRST STREET
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PHONE: 408-433-6000

FAX: 408-433-0952

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PHONE: 408-433-6000

FAX: 408-433-0952

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