MOSEL VITELIC

V58C365164S
64 Mbit DDR SDRAM
4M X 16, 3.3VOLT

V58C365164S Rev. 2.0 January 2003

PRELIMINARY

System Frequency (f

)

275 MHz

250 MHz

200 MHz

Clock Cycle Time (t

CK3

)

3.6 ns

4 ns

5 ns

Clock Cycle Time (t

CK2.5

)

4.3ns

4.8 ns

6 ns

Clock Cycle Time (t

CK2

)

5.4ns

6 ns

7.5 ns

Features

4 banks x 1Mbit x 16 organization

High speed data transfer rates with system
frequency up to 275 MHz

Data Mask for Write Control (DM)

Four Banks controlled by BA0 & BA1

Programmable CAS Latency: 2, 2.5, 3

Programmable Wrap Sequence: Sequential
or Interleave

Programmable Burst Length:
2, 4, 8 for Sequential Type
2, 4, 8 for Interleave Type

Automatic and Controlled Precharge Command

Suspend Mode and Power Down Mode

Auto Refresh and Self Refresh

Refresh Interval: 4096 cycles/64 ms

Available in 66-pin 400 mil TSOP-II

SSTL-2 Compatible I/Os

Double Data Rate (DDR)

Bidirectional Data Strobe (DQs) for input and
output data, active on both edges

On-Chip DLL aligns DQ and DQs transitions with
CLK transitions

Differential clock inputs CLK and CLK

Power supply 3.3V ± 0.3V

VDDQ (I/O) power supply 2.5 + 0.2V

Description

The V58C365164S is a four bank DDR DRAM

organized as 4 banks x 1Mbit x 16. The
V58C365164S achieves high speed data transfer
rates by employing a chip architecture that
prefetches multiple bits and then synchronizes the
output data to a system clock

All of the control, address, circuits are synchro-

nized with the positive edge of an externally sup-
plied clock. I/O transactions are possible on both
edges of DQS.

Operating the four memory banks in an inter-

leaved fashion allows random access operation to
occur at a higher rate than is possible with standard
DRAMs. A sequential and gapless data rate is pos-
sible depending on burst length, CAS latency and
speed grade of the device.

Device Usage Chart

Operating

Temperature

Range

Package Outline

CLK Cycle Time (ns)

Power

Temperature

Mark

JEDEC 66 TSOP II

-36

-4

-5

Std.

0°C to 70°C

Blank

V58C365164S Rev. 2.0 January 2003

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V58C365164S

66 Pin Plastic TSOP-II
PIN CONFIGURATION

Top View

Pin Names

21
22

46
45

43
42

26
27

41
40

32
33

35
34

DDQ

SSQ

DDQ

SSQ

DDQ

LDQS

LDM

CAS

RAS

BA0

BA1

SSQ

DDQ

SSQ

DDQ

SSQ

UDQS

REF

UDM

CLK
CLK

CKE

NC
NC

A11
A9

A10/AP

A1
A2

A6
A5

A4
V

64M

DDR SDRAM

CLK, CLK

Differential Clock Input

CKE

Clock Enable

Chip Select

RAS

Row Address Strobe

CAS

Column Address Strobe

Write Enable

UDQS, LDQS

Data Strobe (Bidirectional)

Address Inputs

BA0, BA1

Bank Select

Data Input/Output

UDM, LDM

Data Mask

Power (+3.3V)

Ground

DDQ

Power for I/O's (+2.5V)

SSQ

Ground for I/O's

Not connected

REF

Reference Voltage for Inputs

V 58 C 3 6516 4 S A T XX

DDRSDRAM

CMOS

3.3V VDD

4MX16, 4K Refresh

4 Banks

COMPONENT

REV LEVEL

COMPONENT

PACKAGE, T = TSOP

SSTL

SPEED

MOSEL VITELIC

MANUFACTURED

4 (250MHZ@CL3)
5 (200MHZ@CL3)

2.5v VDDQ

36 (275MHZ@CL3)

MOSEL VITELIC

V58C365164S

V58C365164S Rev. 2.0 January 2003

Capacitance*

= 0 to 70

C, V

= 3.3 V

0.2 V, f = 1 Mhz

*Note: Capacitance is sampled and not 100% tested.

Absolute Maximum Ratings*

Operating temperature range .................. 0 to 70 °C
Storage temperature range ................-55 to 150 °C
Input/output voltage.................. -0.3 to (V

+0.3) V

Power supply voltage .......................... -0.3 to 4.6 V
Power dissipation ...........................................2.0 W
Data out current (short circuit).......................50 mA

*Note: Stresses above those listed under "Absolute Maximum

Ratings" may cause permanent damage of the device.
Exposure to absolute maximum rating conditions for
extended periods may affect device reliability.

Symbol

Parameter

Max. Unit

Input Capacitance (A0 to A11)

Input Capacitance

RAS, CAS, WE, CS, CKE

Output Capacitance (DQ)

6.5

CLK

Input Capacitance (CCLK, CLK)

Block Diagram

Row decoder

Memory array

Bank 0

4096 x 256

x 16 bit

l
u

dec

oder

ens

ampl

i
f
i
e

r
&

)
bus

Row decoder

Memory array

Bank 1

4096 x 256

x 16 bit

l
u

mn d

der

ampl

i
f
i
e

r
&

)

bus

Row decoder

Memory array

Bank 2

4096 x 256

x 16 bit

l
u

ens

ampl

i
f
i
e

r
&

)
bus

Row decoder

Memory array

Bank 3

4096 x 256

x 16 bit

l
u

ens

e ampl

i
f
i
e

r
&

(
O

)
bus

Input buffer

Output buffer

I/Q

-IQ

Column address

counter

Column address

buffer

Row address

buffer

Refresh Counter

A0 - A11, BA0, BA1

A0 - A7, AP, BA0, BA1

Control logic & timing generator

UDM

Row Addresses

Column Addresses

DLL

Strobe

Gen.

Data Strobe

CLK, CLK

DQS

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V58C365164S

Signal Pin Description

Pin

Type

Signal

Polarity

Function

CLK
CLK

Input

Pulse

Positive

Edge

The system clock input. All inputs except DQs and DMs are sampled on the rising edge
of CLK.

CKE

Input

Level

Active High Activates the CLK signal when high and deactivates the CLK signal when low, thereby

initiates either the Power Down mode, Suspend mode, or the Self Refresh mode.

Input

Pulse

Active Low CS enables the command decoder when low and disables the command decoder when

high. When the command decoder is disabled, new commands are ignored but previous

operations continue.

RAS, CAS

Input

Pulse

Active Low When sampled at the positive rising edge of the clock, CAS, RAS, and WE define the

command to be executed by the SDRAM.

DQS

Input/

Output

Pulse

Active High Active on both edges for data input and output.

Center aligned to input data

Edge aligned to output data

A0 - A11

Input

Level

During a Bank Activate command cycle, A0-A11 defines the row address (RA0-RA11)
when sampled at the rising clock edge.

During a Read or Write command cycle, A0-An defines the column address (CA0-CAn)

when sampled at the rising clock edge.CAn depends from the SDRAM organization:

8M x 8 SDRAM CAn = CA8 (Page Length = 512 bits)

In addition to the column address, A10(=AP) is used to invoke autoprecharge operation
at the end of the burst read or write cycle. If A10 is high, autoprecharge is selected and

BA0, BA1 defines the bank to be precharged. If A10 is low, autoprecharge is disabled.

During a Precharge command cycle, A10(=AP) is used in conjunction with BA0 and BA1

to control which bank(s) to precharge. If A10 is high, all four banks will be precharged

simultaneously regardless of state of BA0 and BA1.

BA0,

BA1

Input

Level

Selects which bank is to be active.

DQx

Input/

Output

Level

Data Input/Output pins operate in the same manner as on conventional DRAMs.

Input

Pulse

Active High In Write mode, DM has a latency of zero and operates as a word mask by allowing input

data to be written if it is low but blocks the write operation if is high.

VDD, VSS

Supply

Power and ground for the input buffers and the core logic.

VDDQ

VSSQ

Supply

Isolated power supply and ground for the output buffers to provide improved noise

immunity.

VREF

Input

Level

SSTL Reference Voltage for Inputs

V58C365164S Rev. 2.0 January 2003

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V58C365164S

Functional Description

Power-Up Sequence
The following sequence is required for POWER UP.

1. Apply power and attempt to maintain CKE at a low state (all other inputs may be undefined.)

- Apply VDD before or at the same time as VDDQ.
- Apply VDDQ before or at the same time as VTT & Vref.

2. Start clock and maintain stable condition for a minimum of 200us.
3. The minimum of 200us after stable power and clock (CLK, CLK), apply NOP & take CKE high.
4. Precharge all banks.
5. Issue EMRS to enable DLL.(To issue "DLL Enable" command, provide "Low" to A0, "High" to BA0

and "Low" to all of the rest address pins, A1~A11 and BA1)

6. Issue a mode register set command for "DLL reset". The additional 200 cycles of clock input is

required to lock the DLL. (To issue DLL reset command, provide "High" to A8 and "Low" to BA0)

7. Issue precharge commands for all banks of the device.
8. Issue 2 or more auto-refresh commands.
9. Issue a mode register set command to initialize device operation.

Note1 Every "DLL enable" command resets DLL. Therefore sequence 6 can be skipped during power up. Instead of it,

the additional 200 cycles of clock input is required to lock the DLL after enabling DLL.

Extended Mode Register Set (EMRS)

The extended mode register stores the data for enabling or disabling DLL. The default value of the extend-

ed mode register is not defined, therefore the extended mode register must be written after power up for en-
abling or disabling DLL. The extended mode register is written by asserting low on CS, RAS, CAS, WE and
high on BA

(The DDR SDRAM should be in all bank precharge with CKE already high prior to writing into

the extended mode register). The state of address pins A

~ A

and BA

in the same cycle as CS, RAS,

CAS and WE low is written in the extended mode register. Two clock cycles are required to complete the
write operation in the extended mode register. The mode register contents can be changed using the same
command and clock cycle requirements during operation as long as all banks are in the idle state. A

is used

for DLL enable or disable. "High" on BA

is used for EMRS. All the other address pins except A

and BA

must be set to low for proper EMRS operation. A

is used at EMRS to indicate I/O strength A

= 0 full strength,

= 1 half strength. Refer to the table for specific codes.

Power up Sequence & Auto Refresh(CBR)

Command

2 Clock min.

precharge

ALL Banks

2nd Auto

Refresh

Mode

Any

Command

RFC

1st Auto
Refresh

RFC

min. 200 Cycle

· ·

CK, CK

· ·

· ·
· ·

EMRS

MRS

2 Clock min.

200

S Power up

to 1st command

DLL Reset

2 Clock min.

precharge
ALL Banks

· ·

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V58C365164S

Mode Register Set (MRS)

The mode register stores the data for controlling the various operating modes of DDR SDRAM. It programs

CAS latency, addressing mode, burst length, test mode, DLL reset and various vendor specific options to
make DDR SDRAM useful for a variety of different applications. The default value of the mode register is not
defined, therefore the mode register must be written after EMRS setting for proper DDR SDRAM operation.
The mode register is written by asserting low on CS, RAS, CAS, WE and BA

(The DDR SDRAM should be

in all bank precharge with CKE already high prior to writing into the mode register). The state of address pins
A

~ A

in the same cycle as CS, RAS, CAS, WE and BA0 low is written in the mode register. Two clock

cycles are required to meet t

MRD

spec. The mode register contents can be changed using the same com-

mand and clock cycle requirements during operation as long as all banks are in the idle state. The mode reg-
ister is divided into various fields depending on functionality. The burst length uses A

~ A

, addressing mode

uses A

, CAS latency (read latency from column address) uses A

~ A

. A

is a Mosel Vitelic specific test

mode during production test. A

is used for DLL reset. A

must be set to low for normal MRS operation. Refer

to the table for specific codes for various burst length, addressing modes and CAS latencies.
1.

MRS can be issued only at all banks precharge state.

Minimum tRP is required to issue MRS command.

Address Bus

CAS Latency

Latency

Reserve

2.5

Reserve

Burst Length

Latency

Sequential

Interleave

Reserve

mode

Normal

Test

Burst Type

Sequential

Interleave

* RFU(Reserved for future use)

should stay "0" during MRS
cycle.

DLL Reset

Yes

Mode Register Set

RFU : Must be set "0"

Extended Mode Register

Mode Register

DLL

I/O

DLL Enable

Enable

Disable

I/O Strength

Full

Half

~ A

(Existing)MRS Cycle

Extended Funtions(EMRS)

Command

CK, CK

MRD

Precharge

All Banks

Mode

Any

Command

CAS Latency

Burst Length

RFU

DLL

MRS

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V58C365164S

Mode Register Set Timing

Burst Mode Operation

Burst Mode Operation is used to provide a constant flow of data to memory locations (Write cycle), or from

memory locations (Read cycle). Two parameters define how the burst mode will operate: burst sequence and
burst length. These parameters are programmable and are determined by address bits A

--A

during the

Mode Register Set command. Burst type defines the sequence in which the burst data will be delivered or
stored to the SDRAM. Two types of burst sequence are supported: sequential and interleave. The burst
length controls the number of bits that will be output after a Read command, or the number of bits to be input
after a Write command. The burst length can be programmed to values of 2, 4, or 8. See the Burst Length
and Sequence table below for programming information.

Burst Length and Sequence

Burst Length

Starting Length (A

, A

)

Sequential Mode

Interleave Mode

xx0

0, 1

xx1

1, 0

x00

0, 1, 2, 3

x01

1, 2, 3, 0

1, 0, 3, 2

x10

2, 3, 0, 1

x11

3, 0, 1, 2

3, 2, 1, 0

000

0,1, 2, 3, 4, 5, 6, 7

001

1, 2, 3, 4, 5, 6, 7, 0

1, 0, 3, 2, 5, 4, 7, 6

010

2, 3, 4, 5, 6, 7, 0, 1

2, 3, 0, 1, 6, 7, 4, 5

011

3, 4, 5, 6, 7, 0, 1, 2

3, 2, 1, 0, 7, 6, 5, 4

100

4, 5, 6, 7, 0, 1, 2, 3

101

5, 6, 7, 0, 1, 2, 3, 4

5, 4, 7, 6, 1, 0, 3, 2

110

6, 7, 0, 1, 2, 3, 4, 5, 6

6, 7, 4, 5, 2, 3, 0, 1

111

7, 0, 1, 2, 3, 4, 5, 6

7, 6, 5, 4, 3, 2, 1, 0

MRD

Pre- All

MRS/EMRS

ANY

Mode Register set (MRS) or Extended Mode Register Set (EMRS) can be issued only when all banks are in the idle state.

CK, CK

Command

If a MRS command is issued to reset the DLL, then an additional 200 clocks must occur prior to issuing any new command

to allow time for the DLL to lock onto the clock.

V58C365164S Rev. 2.0 January 2003

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V58C365164S

Bank Activate Command

The Bank Activate command is issued by holding CAS and WE high with CS and RAS low at the rising

edge of the clock. The DDR SDRAM has four independent banks, so two Bank Select addresses (BA

and

) are supported. The Bank Activate command must be applied before any Read or Write operation can

be executed. The delay from the Bank Activate command to the first Read or Write command must meet or
exceed the minimum RAS to CAS delay time (t

RCD

min). Once a bank has been activated, it must be pre-

charged before another Bank Activate command can be applied to the same bank. The minimum time interval
between interleaved Bank Activate commands (Bank A to Bank B and vice versa) is the Bank to Bank delay
time (t

RRD

min).

Bank Activation Timing

Read Operation

With the DLL enabled, all devices operating at the same frequency within a system are ensured to have

the same timing relationship between DQ and DQS relative to the CK input regardless of device density, pro-
cess variation, or technology generation.

The data strobe signal (DQS) is driven off chip simultaneously with the output data (DQ) during each read

cycle. The same internal clock phase is used to drive both the output data and data strobe signal off chip to
minimize skew between data strobe and output data. This internal clock phase is nominally aligned to the
input differential clock (CK, CK) by the on-chip DLL. Therefore, when the DLL is enabled and the clock fre-
quency is within the specified range for proper DLL operation, the data strobe (DQS), output data (DQ), and
the system clock (CK) are all nominally aligned.

Since the data strobe and output data are tightly coupled in the system, the data strobe signal may be delayed
and used to latch the output data into the receiving device. The tolerance for skew between DQS and DQ
(t

DQSQ

) is tighter than that possible for CK to DQ (t

) or DQS to CK (t

DQSCK

Tn+1

Tn+2

Tn+3

Tn+4

Tn+5

(CAS Latency = 2; Burst Length = Any)

RRD

(min)

RCD

(min)

Begin Precharge Bank A

CK, CK

BA/Address

Command

Bank/Col

Read/A

Bank/Row

Activate/A

Activate/B

Pre/A

Bank/Row

Activate/A

Bank

Bank/Row

RAS

(min)

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V58C365164S

Output Data (DQ) and Data Strobe (DQS) Timing Relative to the Clock (CK)

During Read Cycles

The minimum time during which the output data (DQ) is valid is critical for the receiving device (i.e., a mem-

ory controller device). This also applies to the data strobe during the read cycle since it is tightly coupled to
the output data. The minimum data output valid time (t

) and minimum data strobe valid time (t

DQSV

) are de-

rived from the minimum clock high/low time minus a margin for variation in data access and hold time due to
DLL jitter and power supply noise.

(CAS Latency = 2.5; Burst Length = 4)

NOP

CK, CK

Command

DQS

DQSCK

(max)

DQSCK

(min)

(max)

READ

NOP

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V58C365164S

Output Data and Data Strobe Valid Window for DDR Read Cycles

Read Preamble and Postamble Operation

Prior to a burst of read data and given that the controller is not currently in burst read mode, the data strobe

signal (DQS), must transition from Hi-Z to a valid logic low. The is referred to as the data strobe "read pream-
ble" (t

RPRE

). This transition from Hi-Z to logic low nominally happens one clock cycle prior to the first edge of

valid data.

Once the burst of read data is concluded and given that no subsequent burst read operations are initiated,

the data strobe signal (DQS) transitions from a logic low level back to Hi-Z. This is referred to as the data
strobe "read postamble" (t

RPST

). This transition happens nominally one-half clock period after the last edge of

valid data.

Consecutive or "gapless" burst read operations are possible from the same DDR SDRAM device with no

requirement for a data strobe "read" preamble or postamble in between the groups of burst data. The data
strobe read preamble is required before the DDR device drives the first output data off chip. Similarly, the
data strobe postamble is initiated when the device stops driving DQ data at the termination of read burst cy-
cles.

(CAS Latency = 2; Burst Length = 2)

READ

NOP

Command

DQS

(min)

CK, CK

DQSV

(min)

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V58C365164S

Data Strobe Preamble and Postamble Timings for DDR Read Cycles

Consecutive Burst Read Operation and Effects on the Data Strobe Preamble and Postamble

(CAS Latency = 2; Burst Length = 2)

READ

NOP

CK, CK

Command

DQS

RPRE

(max)

RPST

(min)

RPRE

(min)

RPST

(max)

DQSQ

(max)

DQSQ

(min)

NOP

Read

NOP

Read

NOP

Command

DQS

Burst Read Operation (CAS Latency = 2; Burst Length = 4)

CK, CK

NOP

Read

NOP

Read

NOP

Command

DQS

Burst Read Operation (CAS Latency = 2; Burst Length = 4)

CK, CK

NOP

V58C365164S Rev. 2.0 January 2003

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V58C365164S

Auto Precharge Operation

The Auto Precharge operation can be issued by having column address A

high when a Read or Write

command is issued. If A

is low when a Read or Write command is issued, then normal Read or Write burst

operation is executed and the bank remains active at the completion of the burst sequence. When the Auto
Precharge command is activated, the active bank automatically begins to precharge at the earliest possible
moment during the Read or Write cycle once t

RAS

(min) is satisfied.

Read with Auto Precharge

If a Read with Auto Precharge command is initiated, the DDR SDRAM will enter the precharge operation

N-clock cycles measured from the last data of the burst read cycle where N is equal to the CAS latency pro-
grammed into the device. Once the autoprecharge operation has begun, the bank cannot be reactivated until
the minimum precharge time (t

) has been satisfied.

Read with Autoprecharge Timing

(CAS Latency = 2; Burst Length = 4)

Begin Autoprecharge

NOP

R w/AP

NOP

CK, CK

Command

DQS

RAS

(min)

Earliest Bank A reactivate

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V58C365164S

Precharge Timing During Read Operation

For the earliest possible Precharge command without interrupting a Read burst, the Precharge command

may be issued on the rising clock edge which is CAS latency (CL) clock cycles before the end of the Read
burst. A new Bank Activate (BA) command may be issued to the same bank after the RAS precharge time
(t

). A Precharge command can not be issued until t

RAS

(min) is satisfied.

Read with Precharge Timing as a Function of CAS Latency

NOP

Read

NOP

Pre

NOP

CK, CK

Command

DQS

RAS

(min)

NOP

DQS

CAS Latency=2

CAS Latency=2.5

CAS Latency=3

(CAS Latency = 2, 2.5, 3; Burst Length = 4)

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V58C365164S

Burst Stop Command

The Burst Stop command is valid only during burst read cycles and is initiated by having RAS and CAS

high with CS and WE low at the rising edge of the clock. When the Burst Stop command is issued during a
burst Read cycle, both the output data (DQ) and data strobe (DQS) go to a high impedance state after a delay
(L

BST

) equal to the CAS latency programmed into the device. If the Burst Stop command is issued during a

burst Write cycle, the command will be treated as a NOP command.

Read Terminated by Burst Stop Command Timing

(CAS Latency = 2, 2.5, 3; Burst Length = 4)

BST

NOP

Read

CK, CK

Command

DQS

CAS Latency = 2

CAS Latency = 2.5

CAS Latency = 3

BST

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V58C365164S

Read Interrupted by a Precharge

A Burst Read operation can be interrupted by a precharge of the same bank. The Precharge command to

Output Disable latency is equivalent to the CAS latency.

Read Interrupted by a Precharge Timing

Burst Write Operation

The Burst Write command is issued by having CS, CAS, and WE low while holding RAS high at the rising

edge of the clock. The address inputs determine the starting column address. The memory controller is re-
quired to provide an input data strobe (DQS) to the DDR SDRAM to strobe or latch the input data (DQ) and
data mask (DM) into the device. During Write cycles, the data strobe applied to the DDR SDRAM is required
to be nominally centered within the data (DQ) and data mask (DM) valid windows. The data strobe must be
driven high nominally one clock after the write command has been registered. Timing parameters t

DQSS

(min)

and t

DQSS

(max) define the allowable window when the data strobe must be driven high.

Input data for the first Burst Write cycle must be applied one clock cycle after the Write command is regis-

tered into the device (WL=1). The input data valid window is nominally centered around the midpoint of the
data strobe signal. The data window is defined by DQ to DQS setup time (t

QDQSS

) and DQ to DQS hold time

QDQSH

). All data inputs must be supplied on each rising and falling edge of the data strobe until the burst

length is completed. When the burst has finished, any additional data supplied to the DQ pins will be ignored.

Write Preamble and Postamble Operation

Prior to a burst of write data and given that the controller is not currently in burst write mode, the data strobe

signal (DQS), must transition from Hi-Z to a valid logic low. This is referred to as the data strobe "write preamble".
This transition from Hi-Z to logic low nominally happens on the falling edge of the clock after the write com-
mand has been registered by the device. The preamble is explicitly defined by a setup time (t

WPRES

(min)) and

hold time (t

WPREH

(min)) referenced to the first falling edge of CK after the write command.

NOP

Read

NOP

Pre

NOP

CK, CK

Command

DQS

RAS

(min)

NOP

DQS

CAS Latency=2

CAS Latency=2.5

CAS Latency=3

(CAS Latency = 2, 2.5, 3; Burst Length = 8)

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V58C365164S

Burst Write Timing

Once the burst of write data is concluded and given that no subsequent burst write operations are initiated,

the data strobe signal (DQS) transitions from a logic low level back to Hi-Z. This is referred to as the data
strobe "write postamble". This transition happens nominally one-half clock period after the last data of the
burst cycle is latched into the device.

(CAS Latency = Any; Burst Length = 4)

WRITE

NOP

CK, CK

Command

DQS(nom)

DQ(nom)

WPRES

WPREH

DQSS

WPST

QDQSH

DQS(min)

DQ(min)

DQSS

(min)

DQS(max)

DQ(max)

WPRES

(min)

DQSS

(max)

QDQSS

QDQSH

WPREH

(min)

WPREH

(max)

WPRES

(max)

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MOSEL VITELIC

V58C365164S

Write Interrupted by a Precharge

A Burst Write can be interrupted before completion of the burst by a Precharge command, with the only

restriction being that the interval that separates the commands be at least one clock cycle.

Write Interrupted by a Precharge Timing

Write with Auto Precharge

If A

is high when a Write command is issued, the Write with auto Precharge function is performed. Any

new command to the same bank should not be issued until the internal precharge is completed. The internal
precharge begins after keeping t

(min.).

Write with Auto Precharge Timing

(CAS Latency = 2; Burst Length = 8)

T10

T11

Write

NOP

Pre

NOP

CK, CK

Command

DQS

T12

Data is masked

by Precharge Command

Data is masked

by DM input

DQS input ignored

(CAS Latency = Any; Burst Length = 4)

NOP

WAP

NOP

CK, CK

Command

DQS

RAS

(min)

NOP

T10

(min)

Begin Autoprecharge

V58C365164S Rev. 2.0 January 2003

MOSEL VITELIC

V58C365164S

Precharge Timing During Write Operation

Precharge timing for Write operations in DRAMs requires enough time to satisfy the write recovery require-

ment. This is the time required by a DRAM sense amp to fully store the voltage level. For DDR SDRAMs, a
timing parameter (t

) is used to indicate the required amount of time between the last valid write operation

and a Precharge command to the same bank.

The "write recovery" operation begins on the rising clock edge after the last DQS edge that is used to strobe

in the last valid write data. "Write recovery" is complete on the next rising clock edge that is used to strobe in
the Precharge command.

For the earliest possible Precharge command following a Write burst without interrupting the burst, the

minimum time for "write recovery" is 1.25 clock cycles. Maximum "write recovery" time is 1.75 clock cycles.

Write with Precharge Timing

(CAS Latency = Any; Burst Length = 4)

NOP

Write

NOP

Pre

NOP

CK, CK

Command

DQS

RAS

(min)

NOP

T10

(min)

DQS

(max)

V58C365164S Rev. 2.0 January 2003

MOSEL VITELIC

V58C365164S

Data Mask Function

The DDR SDRAM has a Data Mask function that is used in conjunction with the Write cycle, but not the

Read cycle. When the Data Mask is activated (DM high) during a Write operation, the Write is blocked (Mask
to Data Latency = 0).

When issued, the Data Mask must be referenced to both the rising and falling edges of Data Strobe.

Data Mask Timing

Burst Interruption

Read Interrupted by a Read

A Burst Read can be interrupted before completion of the burst by issuing a new Read command to any

bank. When the previous burst is interrupted, the remaining addresses are overridden with a full burst length
starting with the new address. The data from the first Read command continues to appear on the outputs until
the CAS latency from the interrupting Read command is satisfied. At this point, the data from the interrupting
Read command appears on the bus. Read commands can be issued on each rising edge of the system clock.
It is illegal to interrupt a Read with autoprecharge command with a Read command.

Read Interrupted by a Read Command Timing

(CAS Latency = Any; Burst Length = 8)

NOP

Write

CK, CK

Command

DQS

DMDQSS

DMDQSH

(CAS Latency = 2; Burst Length = 4)

Read

NOP

DA0 DA1 DB0 DB1

Read

DB2 DB3

CK, CK

Command

DQS

V58C365164S Rev. 2.0 January 2003

MOSEL VITELIC

V58C365164S

Read Interrupted by a Write

To interrupt a Burst Read with a Write command, a Burst Stop command must be asserted to stop the burst

read operation and 3-state the DQ bus. Additionally, control of the DQS bus must be turned around to allow
the memory controller to drive the data strobe signal (DQS) into the DDR SDRAM for the write cycles. Once
the Burst Stop command has been issued, a Write command can not be issued until a minimum delay or
latency (L

BST

) has been satisfied. This latency is measured from the Burst Stop command and is equivalent

to the CAS latency programmed into the mode register. In instances where CAS latency is measured in half
clock cycles, the minimum delay (L

BST

) is rounded up to the next full clock cycle (i.e., if CL=2 then L

BST

=2, if

CL=2.5 then L

BST

=3). It is illegal to interrupt a Read with autoprecharge command with a Write command.

Read Interrupted by Burst Stop Command Followed by a Write Command Timing

Write Interrupted by a Write

A Burst Write can be interrupted before completion by a new Write command to any bank. When the pre-

vious burst is interrupted, the remaining addresses are overridden with a full burst length starting with the new
address. The data from the first Write command continues to be input into the device until the Write Latency
of the interrupting Write command is satisfied (WL=1) At this point, the data from the interrupting Write com-
mand is input into the device. Write commands can be issued on each rising edge of the system clock. It is
illegal to interrupt a Write with autoprecharge command with a Write command.

Write Interrupted by a Write Command Timing

(CAS Latency = 2; Burst Length = 4)

BST

NOP

Write

NOP

Read

CK, CK

Command

DQS

BST

(CAS Latency = Any; Burst Length = 4)

Write

NOP

Write

NOP

DA0 DA1 DB0 DB1 DB2 DB3

CK, CK

Command

DQS

Write Latency

DM0 DM1 DM0 DM1 DM2 DM3

V58C365164S Rev. 2.0 January 2003

MOSEL VITELIC

V58C365164S

Write Interrupted by a Read

A Burst Write can be interrupted by a Read command to any bank. If a burst write operation is interrupted

prior to the end of the burst operation, then the last two pieces of input data prior to the Read command must
be masked off with the data mask (DM) input pin to prevent invalid data from being written into the memory
array. Any data that is present on the DQ pins coincident with or following the Read command will be masked
off by the Read command and will not be written to the array. The memory controller must give up control of
both the DQ bus and the DQS bus at least one clock cycle before the read data appears on the outputs in
order to avoid contention. In order to avoid data contention within the device, a delay is required (t

CDLR

) from

the last valid data input before a Read command can be issued to the device. It is illegal to interrupt a Write
with autoprecharge command with a Read command.

Write Interrupted by a Read Command Timing

Auto Refresh

The Auto Refresh command is issued by having CS, RAS, and CAS held low with CKE and WE high at the

rising edge of the clock. All banks must be precharged and idle for a t

(min) before the Auto Refresh com-

mand is applied. No control of the address pins is required once this cycle has started because of the internal
address counter. When the Auto Refresh cycle has completed, all banks will be in the idle state. A delay be-
tween the Auto Refresh command and the next Activate command or subsequent Auto Refresh command
must be greater than or equal to the t

RFC

(min). Commands may not be issued to the device once an Auto

Refresh cycle has begun. CS input must remain high during the refresh period or NOP commands must be
registered on each rising edge of the CK input until the refresh period is satisfied.

Auto Refresh Timing

(CAS Latency = 2; Burst Length = 8)

T10

T11

Write

NOP

Read

NOP

CK, CK

Command

DQS

T12

Data is masked

by Read command

Data is masked

by DM input

DQS input ignored

CDLR

T10

NOP

CK, CK

Command

CKE

T11

Auto Ref

ANY

High

Pre All

RFC

V58C365164S Rev. 2.0 January 2003

MOSEL VITELIC

V58C365164S

Self Refresh

A self refresh command is defined by having CS, RAS, CAS and CKE held low with WE high at the rising

edge of the clock (CK). Once the self refresh command is initiated, CKE must be held low to keep the device
in self refresh mode. During the self refresh operation, all inputs except CKE are ignored. The clock is inter-
nally disabled during self refresh operation to reduce power consumption. The self refresh is exited by sup-
plying stable clock input before returning CKE high, asserting deselect or NOP command and then asserting
CKE high for longer than t

SREX

for locking of DLL. The auto refresh is required before self refresh entry and

after self refresh exit.

Power Down Mode

The power down mode is entered when CKE is low and exited when CKE is high. Once the power down

mode is initiated, all of the receiver circuits except clock, CKE and DLL circuit tree are gated off to reduce
power consumption. All banks should be in idle state prior to entering the precharge power down mode and
CKE should be set high at least 1tck+tIS prior to row active command. During power down mode, refresh
operations cannot be performed, therefore the device cannot remain in power down mode longer than the
refresh period (t

REF

) of the device.

Command

CKE

Stable Clock

SREX

Auto

Refresh

NOP

Self

Refresh

· ·

CK, CK

· ·

CKE

Precharge

Active

Read

NOP

Active

power down

Exit

Active

Entry

power

Exit

down

power

Entry

down

Precharge

· ·

precharge

Command

CK, CK

V58C365164S Rev. 2.0 January 2003

MOSEL VITELIC

V58C365164S

SSTL_2 Input AC/DC Logic Levels

Note: 1. The relationship of the V

DDQ

of the driving device and the V

REF

of the receiving device is what determines noise margins.

However, in the case of V

(max) (input overdrive), it is the V

DDQ

of the receiving device that is referenced. In the case where

a device is implemented such that supports SSTL_2 inputs but has no SSTL_2 outputs (e.g., a translator), and therefore no
V

DDQ

supply voltage connection, inputs must tolerate input overdrive to 3.0V (High corner V

DDQ

+300mV.)

SSTL_2 AC Test Conditions

Notes: 1. Input waveform timing is referenced to the input signal crossing the V

REF

level applied to the device.

2. Compliant devices must still meet the V

(AC) and V

(AC) specifications under actual use conditions.

3. The 1 V/ns input signal minimum slew rate is to be maintained in the V

max (AC) to V

min (AC) range of the input

signal swing.

SSTL_2 Output Buffers

The input voltage provided to the receiver depends on three parameters:

DDQ

and current drive capabilities of the output buffer

Termination voltage

Termination resistance

DDQ

=2.5 + 0.2V

Class II SSTL_2 Output Buffer (Driver)

Symbol

Parameter

Min

Max

Units

Notes

(DC)

DC Input Logic High

REF

+0.18

DDQ

+0.3

(AC)

AC Input Logic High

REF

+0.35

(DC)

DC Input Logic Low

0.30

REF

0.18

(AC)

AC Input Logic Low

REF

0.35

Symbol

Parameter

Value

Units

Notes

REF

Input Reference Voltage

0.5*V

DDQ

SWING

(max)

Input Signal Maximum Peak to Peak Swing

1.5

1, 2

SLEW

Input Signal Minimum Slew Rate

1.0

V/ns

REF

= 0.5 *V

DDQ

LOAD

= 30pF

DDQ

SSQ

OUT

Receiver

RT=50

Output

Buffer

V58C365164S Rev. 2.0 January 2003

MOSEL VITELIC

V58C365164S

DC CHARACTERISTICS

Recommended operating conditions Unless Otherwise Noted, T

=0 to 70°C

Parameter

Symbol

Test Condition

CAS

Latency

Version

Unit

-36

Operating Current

(One Bank Active)

Burst Length=2 t

(min) I

=0mA

155

150

140

Precharge Standby Current

in Power-Down Mode

CC2

CKE=V

(max), t

=10ns

Precharge Standby Current

in Non Power-Down Mode

CC2

CKE=VIH(min), CS=VIH(min), tCC=10ns

Input signals are changed once during 20ns

Active Standby Current in Power-

Down Mode

CC3

CKE=V

(max), t

=10ns

Active Standby Current in Non-

Power-Down Mode

CC3

CKE=VIH(min), CS=VIH(min), tCC=10ns

Input signals are changed once during 20ns

Operating Current (Burst Mode)

CC4

=0mA

Page Burst
All Banks activated

CCD

=2CKs

165

160

150

Refresh Current

CC5

RFC

(min)

200

Self Refresh Current

CC6

CKE=0.2V

V58C365164S Rev. 2.0 January 2003

MOSEL VITELIC

V58C365164S

AC Characteristics (T

=0 to +70°C, V

=3.3 ± 0.3V)

Symbol

Parameter

-36

Unit

Min.

Max.

Min.

Max.

Min.

Max.

Clock Cycle

Clock Cycle

CL = 2.0

5.4

7.5

CL = 2.5

4.3

4.8

CL = 3.0

3.6

Clock Duty Cycle

0.45

0.55

0.45

0.55

0.45

0.55

0.45

0.55

0.45

0.55

0.45

0.55

Command Cycle

RAS

Row Active Time (ACT->PRE)

100K

Row Precharge (PRE->ACT)

Row Cycle (ACT->ACT)

RCD

RAS->CAS Delay (ACT->WR/RD)

RRD

RAS->RAS Delay (ACTa->ACTb)

7.2

RFC

Auto-Refresh (REF->REF/ACT)

REF

Refresh Cycle

SREX(DLL)

Self-Refresh Exit Delay

200

cycles

SREX

CMD, ADDR->CLK Setup

0.9

1.0

CMD, ADDR->CLK Hold

0.9

1.0

CCD

CAS->CAS Delay (Cola->Colb)

MRD

Mode Register Set Delay

PDENT

Power Down Entry Delay

PDEX(DLL)

Power Down Exit Delay

PDEX

Read Cycle

CLK->DQ Skew

-0.1

0.2

-0.2

0.125

-0.2

0.1

DQSCK

CLK->DQS Skew

-0.1

0.2

-0.2

0.125

-0.2

0.1

DQSQ

DQS->DQ Skew

-0.075

0.1

-0.075

0.1

-0.075

0.08

DQ/DQS Valid Window

0.3

RPRE

Read DQS Preamble

0.9

1.1

0.9

1.1

0.9

1.1

RPST

Read DQS Postamble

0.4

0.6

0.4

0.6

0.4

0.6

V58C365164S Rev. 2.0 January 2003

MOSEL VITELIC

V58C365164S

Write Cycle

WPRES

Write Preamble DQS Setup

WPREH

Write Preamble DQS Hold

0.42

0.375

0.3

DQSS

Write Preamble CLK->DQS (first)

0.8

1.25

0.8

1.25

0.75

1.25

DSH

Write DQS High Width

0.4

0.6

0.4

0.6

0.4

0.6

DSL

Write DQS Low Width

0.4

0.6

0.4

0.6

0.4

0.6

WPST

Write Postamble DQS (last) -> Hi-Z

0.4

0.6

0.4

0.6

0.4

0.6

DQSR

Write (last DIN) -> READ Command

Write (last DIN) -> PRE Command

DQ/DM -> DQS Setup (Data Setup)

0.25

DQ/DM -> DQS Hold (Data Hold)

0.25

QDQSS

Date Input to Data Strobe Setup Time

0.075

QDQSH

Date Input to Data Strobe Hold Time

0.075

DMDSQS

Date Mask to Data Strobe Setup Time

0.075

DMDQSH

Date Mask to Data Strobe Hold Time

0.075

AC Characteristics (Continued) (T

=0 to +70°C, V

=3.3 ± 0.3V)

Symbol

Parameter

-36

Unit

Min.

Max.

Min.

Max.

Min.

Max.

V58C365164S Rev. 2.0 January 2003

MOSEL VITELIC

V58C365164S

Command

CKEn-1

CKEn

RAS

CAS

ADDR

A10/

Note

OP code

1,2

Device Deselect

Bank Active

Read

Read with Autoprecharge

1,3

Write

Write with Autoprecharge

1,4

Precharge All Banks

1,5

Precharge selected Bank

Read Burst Stop

Auto

Self Refresh

Entry

Exit

Precharge Power

Down Mode

Entry

Exit

Active Power

Down Mode

Entry

Exit

Note :
1. LDM/UDM states are Don't Care. Refer to below Write Mask Truth Table.
2. OP Code(Operand Code) consists of A0~A11 and BA0~BA1 used for Mode Register setting duing Extended MRS or MRS.
Before entering Mode Register Set mode, all banks must be in a precharge state and MRS command can be issued after tRP
period from Prechagre command.
3. If a Read with Autoprecharge command is detected by memory component in CK(n), then there will be no command presented
to activated bank until CK(n+BL/2+tRP).
4. If a Write with Autoprecharge command is detected by memory component in CK(n), then there will be no command presented
to activated bank until CK(n+BL/2+1+tDPL+tRP). Last Data-In to Prechage delay(tDPL) which is also called Write Recovery Time
(tWR) is needed to guarantee that the last data has been completely written.
5. If A10/AP is High when Precharge command being issued, BA0/BA1 are ignored and all banks are selected to be
precharged.

( H=Logic High Level, L=Logic Low Level, X=Don't Care, V=Valid Data Input, OP Code=Operand Code, NOP=No Operation )

OP code

Refresh

Operation

Mode Register Set

Extended Mode Register Set

DDR SDRAM SIMPLIFIED COMMAND TRUTH TABLE

V58C365164S Rev. 2.0 January 2003

MOSEL VITELIC

V58C365164S

Complete List of Operation Commands

DDR SDRAM Function Truth Table

CURRENT

STATE

RAS

CAS

Addr

ACTION

Idle

L
L

H
H

BS
BS

Op-

RA
AP

Code

NOP or Power Down

NOP

ILLEGAL

Row (&Bank) Active; Latch Row Address
NOP

Auto-Refresh or Self-Refresh

Mode reg. Access

Row Active

L
L

H
H

L
L

BS
BS

CA,AP
CA,AP

NOP

Begin Read; Latch CA; DetermineAP
Begin Write; Latch CA; DetermineAP

ILLEGAL

Precharge

ILLEGAL

Read

L
L

H
H

X
X

CA,AP

NOP (Continue Burst to End;>Row Active)

NOP (Continue Burst to End;>Row Active)
Term Burst

Term Burst, New Read, DetermineAP

ILLEGAL (Need Term Burst before Write)

ILLEGAL to Same Bank, other Bank 0K if tRRD is Satisfied

Term Burst, Precharge

ILLEGAL

Write

L
L

H
H

BS
BS

CA,AP

NOP (Continue Burst to End;>Row Active)

NOP

Term Burst, Start Read, DetermineAP

Term Burst, New Write, DetermineAP

ILLEGAL

Term Burst, Precharge

ILLEGAL

Read

with

Auto

Precharge

L
L

H
H

L
L

X
X

NOP (Continue Burst to End;> Precharge)

ILLEGAL

V58C365164S Rev. 2.0 January 2003

MOSEL VITELIC

V58C365164S

DDR SDRAM Function Truth Table (continued)

CURRENT

STATE

RAS

CAS

Addr

ACTION

Write

with

Auto

Precharge

L
L

X
X

NOP (Continue Burst to End;> Precharge)

ILLEGAL

ILLEGAL
ILLEGAL

ILLEGAL

Precharging

L
L

H
H

BS
BS

X
X

NOP;> Idle after tRP

NOP
ILLEGAL

(0K Provided tRP Satisfied) ACT

NOP

ILLEGAL

Row

Activating

L
L

H
H

X
X

NOP;> Row Active after tRCD

NOP;> Row Active after tRCD
ILLEGAL

(0K if tRCD satisfied) Read/Write

(0K to other Bank if tRRD Satisfied) ACT

Precharge

ILLEGAL

Write
Recovering

X
H

X
X

NOP
NOP

ILLEGAL

Refreshing

NOP;> Idle after tRC

ILLEGAL

Mode
Register

Accessing

X
H

X
X

NOP
NOP

ILLEGAL

V58C365164S Rev. 2.0 January 2003

MOSEL VITELIC

V58C365164S

Clock Enable (CKE) Truth Table

Abbreviations:

RA = Row Address BS = Bank Select Address

CA = Column Address AP = Auto Precharge

Notes for SDRAM function truth table:

1. Current State is state of the bank determined by BS. All entries assume that CKE was active (HIGH) during the preceding clock cycle.
2. Illegal to bank in specified state; Function may be legal in the bank indicated by BS, depending on the state of that bank.
3. Must satisfy bus contention, bus turn around, and/or write recovery requirements.
4. NOP to bank precharging or in Idle state. The precharge bank(s) indicated by BS and AP.
5. Illegal if any bank is not Idle.
6. CKE Low to High transition will re-enable CLK and other inputs asynchronously. A minimum setup time must be satisfied before any

command other than EXIT.

7. Power-Down and Self-Refresh can be entered only from the All Banks Idle State.
8. Must be legal command as defined in the SDRAM function truth table.

STATE(n)

CKE

n-1

CKE

RAS

CAS

Addr

ACTION

Self-Refresh

L
L

H
H

L
L

X
X

INVALID

EXIT Self-Refresh, Idle after tRC

ILLEGAL

ILLEGAL
ILLEGAL

NOP (Maintain Self-Refresh)

Power-Down

L
L

H
H

L
L

H
H

L
X

X
X

INVALID

EXIT Power-Down, > Idle.

ILLEGAL
ILLEGAL

ILLEGAL

NOP (Maintain Low-Power Mode)

All. Banks

Idle

H
H

L
L

H
H

X
X

Refer to the function truth table

Enter Power- Down

Enter Power- Down
ILLEGAL

ILLEGAL

Enter Self-Refresh

ILLEGAL

NOP

Any State

other than

listed above

Refer to the function truth table

Begin Clock Suspend next cycle

Exit Clock Suspend next cycle

Maintain Clock Suspend.

V58C365164S Rev. 2.0 January 2003

MOSEL VITELIC

V58C365164S

Package Diagram
66-Pin TSOP-II (400 mil)

Units : Millimeters

0.30 0.08

0.65TYP

(0.71)

22.22 0.10

0.125

(
0

.
80)

.
1

6 0

.
1

0 ~8

#33

#66

#34

(1.50)

.
5

)

0.65 0.08

.
5

)

.
5

)

(
10.

)

.
7

6 0

.
2

(10· )

(10·)

+0.075

-0.035

.
8

)

0.10 MAX

0.075 MAX

[

]

(10· )

(R0

.15

)

0 0.

5 0.

(R0.

15)

)

0.2

.
7

0.25TYP

NOTE
1. ( ) IS REFERENCE

V58C365164S Rev. 2.0 January 2003

MOSEL VITELIC

V58C365164S

WORLDWIDE OFFICES

Printed in U.S.A.

The information in this document is subject to change without
notice.

MOSEL VITELIC makes no commitment to update or keep cur-
rent the information contained in this document. No part of this
document may be copied or reproduced in any form or by any
means without the prior written consent of MOSEL-VITELIC.

MOSEL VITELIC subjects its products to normal quality control
sampling techniques which are intended to provide an assurance
of high quality products suitable for usual commercial applica-
tions. MOSEL VITELIC does not do testing appropriate to provide
100% product quality assurance and does not assume any liabil-
ity for consequential or incidental arising from any use of its prod-
ucts. If such products are to be used in applications in which
personal injury might occur from failure, purchaser must do its
own quality assurance testing appropriate to such applications.

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