Memory Array
1024 X 1024
Row Select
I/O Circuit
Pre-Charge Circuit
Column Select
Data
Cont
Data
Cont
Vcc
Vss
A10 A11 A12 A13 A14 A15
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
I/O1 - I/O8
I/O9 - I/O16
WE
OE
BHE
BLE
CE
1
2
3
12
10
11
8
39
13
9
7
6
4
5
26
25
24
23
22
21
14
15
16
17
18
19
20
40
41
42
43
44
38
37
36
35
34
33
32
31
30
29
28
27
A9
A8
A7
A6
A5
A4
A3
A2
A1
WE
I/O8
I/O7
I/O6
I/O5
I/O4
I/O3
I/O2
I/O1
A0
CE
Vss
Vcc
NC
A15
A14
A13
A12
A11
A10
I/O16
I/O15
I/O14
I/O13
I/O12
I/O11
I/O10
I/O9
NC
NC
Vss
Vcc
BHE
BLE
OE
V62C1161024L(L)
Ultra Low Power
64K x 16 CMOS SRAM
Features
Ultra Low-power consumption
- Active: 30mA I
CC
at 70ns
- Stand-by: 5
A
(CMOS input/output)
1
A
(
CMOS input/output,
L
version)
70/85/100/120 ns access time
Equal access and cycle time
Single +1.8V to 2.2V Power Supply
Tri-state output
Automatic power-down when deselected
Multiple center power and ground pins for
improved noise immunity
Individual byte controls for both Read and
Write cycles
Available in 44 pin TSOP (II) Package
Functional Description
The V62C1161024L is a Low Power CMOS Static RAM
organized as 65,536 words by 16 bits. Easy memory exp-
ansion is provided by an active LOW (CE) and (OE) pin.
This device has an automatic power-down mode feature
when deselected. Separate Byte Enable controls (BLE
and BHE) allow individual bytes to be accessed. BLE
controls the lower bits I/O1 - I/O8. BHE controls the
upper bits I/O9 - I/O16.
Writing to these devices is performed by taking Chip
Enable (CE) with Write Enable (WE) and Byte Enable
(BLE/BHE) LOW.
Reading from the device is performed by taking Chip
Enable (CE) with Output Enable (OE) and Byte Enable
(BLE/BHE) LOW while Write Enable (WE) is held
HIGH.
TSOP(II)
Logic Block Diagram
REV. 1.
1 April 2001 V62C1161024L(L)
1
V62C1161024L(L)
Absolute Maximum Ratings *
* Note: Stresses greater than those listed above Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rat-
ing only and function operation of the device at these or any other conditions outside those indicated in the operational sections of this spec-
ification is not implied. Exposure to Absolute Maximum Rating conditions for extended periods may affect reliability.
Parameter
Symbol
Minimum
Maximum
Unit
Voltage on Any Pin Relative to Gnd
Vt
-0.5
+4.0
V
Power Dissipation
PT
-
1.0
W
Storage Temperature (Plastic)
Tstg
-55
+150
0
C
Temperature Under Bias
Tbias
-40
+85
0
C
Truth Table
* Key: X = Don't Care, L = Low, H = High
CE
OE
WE
BLE
BHE I/O1-I/O8 I/O9-I/O16
Power
Mode
H
X
X
X
X
High-Z
High-Z
Standby
Standby
L
L
H
L
H
Data Out
High-Z
Active
Low Byte Read
L
L
H
H
L
High-Z
Data Out
Active
High Byte Read
L
L
H
L
L
Data Out
Data Out
Active
Word Read
L
X
L
L
L
Data In
Data In
Active
Word Write
L
X
L
L
H
Data In
High-Z
Active
Low Byte Write
L
X
L
H
L
High-Z
Data In
Active
High Byte Write
L
H
H
X
X
High-Z
High-Z
Active
Output Disable
L
X
X
H
H
High-Z
High-Z
Active
Output Disable
2
Recommended Operating Conditions
(T
A
= 0
o
C to +70
o
C / -40
o
C to 85
o
C**)
* V
IL
min = -2.0V for pulse width less than t
RC
/2.
** For Industrial Temperature
Parameter
Symbol
Min
Typ
Max
Unit
V
CC
1.8
2.0
2.2
V
Gnd
0.0
0.0
0.0
V
V
IH
1.6
-
V
CC
+ 0.2
V
V
IL
-0.5*
-
0.4
V
Supply Voltage
Input Voltage
REV. 1.
1 April 2001 V62C1161024L(L)
AC Test Conditions
Input Pulse Level
0.4V to 1.6V
Input Rise and Fall Time
5ns
Input and Output Timing
Reference Level 1.0V
Output Load Condition
70ns/85ns
C
L
= 30pf + 1TTL Load
Load for 100ns/120ns
C
L
= 100pf + 1TTL Load
C
L
*
Figure A. * Including Scope and Jig Capacitance
TTL
V62C1161024L(L)
DC Operating Characteristics
(V
cc
= 2V+10%, Gnd = 0V, T
A
= 0
0
C to +70
0
C / -40
0
C to 85
0
C)
Input Leakage Current
I
I
LI
V
cc
= Max,
V
in
= Gnd to V
cc
- 1 - 1 - 1 - 1
A
Output Leakage
Current
I
I
LO
CE = V
IH
or V
cc
=
Max,
V
OUT
=
Gnd to V
cc
- 1 - 1 - 1 - 1
A
Operating Power
Supply Current
I
CC
CE = V
IL
, V
IN
= V
IH
or
V
IL
,
I
OUT
=
0
-
3
-
3
-
3
-
3
mA
Average Operating
Current
I
CC1
I
OUT
=
0mA,
Min Cycle, 100% Duty
-
30
-
25
-
20
-
20
mA
I
CC2
CE < 0.2V
I
OUT
=
0mA,
Cycle Time=1
s, Duty=100%
- 3 - 3 - 3 - 3 mA
Standby Power Supply
Current (TTL Level)
I
SB
CE = V
IH
- 0.5 - 0.5 - 0.5 - 0.5 mA
Standby Power Supply
Current (CMOS Level)
I
SB1
CE > V
cc
- 0.2V
L
V
IN
< 0.2V or
V
IN
> V
cc
- 0.2V
LL
-
5
1
-
5
1
-
5
1
-
5
1
A
A
Output Low Voltage
V
OL
I
OL
= 2 mA - 0.4 - 0.4 - 0.4 - 0.4 V
Output High Voltage
V
OH
I
OH
= -1 mA
1.6
-
1.6
-
1.6
-
1.6
-
V
-70
-100
-120
Unit
Parameter
Sym
Test Conditions
Min Max Min Max Min Max Min Max
-85
3
Capacitance
(f = 1MHz, T
A
= 25
0
C)
Parameter*
Symbol
Test Condition
Max
Unit
Input Capacitance C
in
V
in
= 0V
7
pF
I/O Capacitance C
I/O
V
in
= V
out
= 0V
8
pF
* This parameter is guaranteed by device characterization and is not production tested.
REV. 1.
1 April 2001 V62C1161024L(L)
- -
-
-
V62C1161024L(L)
Parameter
Sym
Unit
Note
Read Cycle Time t
RC
70 - 85 - 100 - 120 - ns
Address Access Time t
AA
- 70 - 85 - 100 - 120 ns
Chip Enable Access Time t
ACE
- 70 - 85 - 100 - 120 ns
Output Enable Access Time t
OE
- 40 - 40 - 50 - 60 ns
Output
Hold from
Address Change t
OH
10 - 10 - 10 - 10 - ns
Chip Enable to Output in Low-Z t
LZ
10 - 10 - 10 - 10 - ns 4,5
Chip Disable to Output in High-Z t
HZ
- 30 - 35 - 40 - 40 ns 3,4,5
Output Enable to Output in Low-Z t
OLZ
5 - 5 - 5 - 5 - ns
Output
Disable to
Output in High-Z t
OHZ
- 25 - 30 - 35 - 40 ns
BLE, BHE Enable to Output in Low-Z t
BLZ
5 - 5 - 5 - 5 - ns 4,5
BLE, BHE Disable to Output in High-Z t
BHZ
- 25 - 30 - 35 - 40 ns 3,4,5
BLE, BHE Access Time t
BA
- 40 - 40 - 50 - 60 ns
Read Cycle
(9)
(V
cc
= 2V+0.2V, Gnd = 0V, T
A
= 0
0
C to +70
0
C / -40
0
C to +85
0
C)
Write Cycle
(11)
(V
cc
=2V+0.2V, Gnd = 0V, T
A
= 0
0
C to +70
0
C / -40
0
C to +85
0
C)
Parameter
Symbol
Unit
Note
Write Cycle Time t
WC
70
-
85
-
100
-
120
-
ns
Chip Enable to Write End t
CW
60
-
70
-
80
-
90
-
ns
Address Setup to Write End t
AW
60
-
70
-
80
-
40
-
ns
Address Setup Time t
AS
0
-
0
-
0
-
0
-
ns
Write Pulse Width t
WP
50
-
60
-
70
-
80
-
ns
Write Recovery Time t
WR
0 - 0 - 0 - 0 - ns
Data Valid to Write End t
DW
30
-
35
-
40
-
45
-
ns
Data Hold Time t
DH
0 - 0 - 0 - 0 - ns
Write Enable to Output in High-Z t
WHZ
-
30
-
35
-
40
-
40
ns
Output Active from Write End t
OW
5
-
5
-
5
-
5
-
ns
BLE, BHE Setup to Write End t
BW
60 - 70 - 80 - 90 - ns
Min Max Min Max Min Max Min Max
-70
-85
-100
-120
4
Min Max Min Max Min Max Min Max
-70
-85
-100
-120
REV. 1.
1 April 2001 V62C1161024L(L)
Timing Waveform of Read Cycle 1 (Address Controlled)
t
RC
t
AA
t
OH
Data Valid
Address
Data Out
Timing Waveform of Read Cycle 2
t
OHZ
t
RC
t
OLZ
t
ACE
t
LZ(4,5)
CE
Previous Data Valid
Address
t
OH
t
AA
t
OE
t
BA
t
BLZ(4,5)
t
BHZ(3,4,5)
t
HZ(3,4,5)
(BLE/BHE)
OE
Data Out
Data Valid
High-Z
V62C1161024L(L)
5
Notes (Read Cycle)
1. WE are high for read cycle.
2. All read cycle timing is referenced from the last valid address to the first transition address.
3.
t
HZ
and
t
OHZ
are defined as the time at which the outputs achieve the open circuit condition referenced to V
OH
or V
OL
levels.
4. At any given temperature and voltage condition
t
HZ
(max.) is less than
t
LZ
(min.) both for a given device and from device to
device.
5. Transition is measured + 200mV from steady state voltage with load. This parameter is sampled and not 100% tested.
6. Device is continuously selected with CE = V
IL
.
7. Address valid prior to coincident with CE transition Low.
8. For common I/O applications, minimization or elimination of bus contention conditions is necessary during read and write
cycle.
9. For test conditions, see AC Test Condition, Figure A.
REV. 1.
1 April 2001 V62C1161024L(L)
V62C1161024L(L)
Timing Waveform of Write Cycle 1 (Address Controlled)
Timing Waveform of Write Cycle 2 (CE Controlled)
Timing Waveform of Write Cycle 3 (BLE/BHE Controlled)
Address
High-Z
t
DW
t
DH
t
WP (2)
t
WC
t
CW (3)
t
AW
t
WR (5)
t
AS (4)
Address
Address
Data In
Data In
Data In
Data Out
Data Out
Data Out
CE
CE
CE
BLE/BHE
BLE/BHE
BLE/BHE
WE
WE
WE
t
BW
t
LZ
t
BLZ
t
WHZ (6)
High-Z (8)
High-Z
t
WHZ (6)
High-Z (8)
High-Z
High-Z
t
DW
t
DH
t
WP (2)
t
BW
t
AS (4)
t
WR (5)
t
CW (3)
t
AW
t
WC
High-Z
High-Z (8)
t
OW
t
OHZ (6)
t
DW
t
DH
t
WP (2)
t
BW
t
AS (4)
t
CW (3)
t
AW
t
WC
t
WR (5)
6
REV. 1.
1 April 2001 V62C1161024L(L)
V62C1161024L(L)
7
Notes (Write Cycle)
1.
All write timing is referenced from the last valid address to the first transition address.
2.
A write occurs during the overlap of a low CE and WE. A write begins at the latest transition among CE and WE going
low: A write ends at the earliest transition among CE going high and WE going high.
t
WP
is measured from the beginning
of write to the end of write.
3.
t
CW
is measured from the later of CE going low to end of write.
4.
t
AS
is measured from the address valid to the beginning of write.
5.
t
WR
is measured from the end of write to the address change.
6.
If OE, CE and WE are in the Read Mode during this period, the I/O pins are in the output Low-Z state.
Inputs of opposite phase of the output must not be applied because bus contention can occur.
7.
For common I/O applications, minimization or elimination of bus contention conditions is necessary during read and
write cycle.
8.
If CE goes low simultaneously with WE going low or after WE going low, the outputs remain high impedance state.
9.
D
OUT
is the read data of the new address.
10. When CE is low: I/O pins are in the outputs state. The input signals in the opposite phase leading to the output should
not be applied.
11. For test conditions, see AC Test Condition, Figure A & B.
REV. 1.
1 April 2001 V62C1161024L(L)
V62C1161024L(L)
8
Notes
1.
L-version includes this feature.
2. This Parameter is sampled and not 100% tested.
3.
For test conditions, see AC Test Condition, Figure A.
4.
This parameter is tested with CL = 5pF as shown in Figure B. Transition is measured + 500mV from steady-state voltage.
5.
This parameter is guaranteed, but is not tested.
6.
WE is High for read cycle.
7.
CE and OE are LOW for read cycle.
8.
Address valid prior to or coincident with CE transition LOW.
9.
All read cycle timings are referenced from the last valid address to the first transtion address.
10. CE or WE must be HIGH during address transition.
11. All write cycle timings are referenced from the last valid address to the first transition address.
Data Retention Mode
V
DR
> 1.0V
Vcc_typ
V
IH
V
IH
V
DR
V
CC
CE
t
R
t
CDR
Vcc_typ
Data Retention Waveform
(L Version Only) (T
A
= 0
0
C to +70
0
C / -40
0
C to +85
0
C)
Data Retention Characteristics
(L Version Only)
(1)
Parameter
Symbol
Test Condition
Min
Max
Unit
V
CC
for Data Retention V
DR
CE > V
CC
- 0.2V 1.0
-
V
Data Retention Current I
CCDR
L
-
5
1
A
Chip Deselect to Data Retention Time t
CDR
V
IN
> V
CC
- 0.2V or
0
-
ns
Operation Recovery Time
(2)
R
V
IN
< 0.2V
t
RC
-
ns
REV. 1.
1 April 2001 V62C1161024L(L)
t
Ordering Information
Device Type*
Speed
Package
V62C1161024L-70T 70 ns 44-pin TSOP Type 2
V62C1161024L-85T 85 ns
V62C1161024L-100T 100 ns
V62C1161024L-120T 120 ns
V62C1161024LL-70T 70 ns
V62C1161024LL-85T 85 ns
V62C1161024LL-100T 100 ns
V62C1161024LL-120 T 120 ns
9
*
For Industrial temperature tested devices, an "I" designator will be added to the end of the device number.
REV. 1.
1 April 2001 V62C1161024L(L)
V62C1161024L(L)
MOSEL VITELIC
WORLDWIDE OFFICES
Copyright 2001, MOSEL VITELIC Inc.
4/01
Printed in U.S.A.
MOSEL VITELIC
3910 N. First Street, San Jose, CA 95134-1501 Ph: (408) 433-6000 Fax: (408) 433-0952 Tlx: 371-9461
The information in this document is subject to change without
notice.
MOSEL VITELIC makes no commitment to update or keep cur-
rent the information contained in this document. No part of this
document may be copied or reproduced in any form or by any
means without the prior written consent of MOSEL-VITELIC.
MOSEL VITELIC subjects its products to normal quality control
sampling techniques which are intended to provide an assurance
of high quality products suitable for usual commercial applica-
tions. MOSEL VITELIC does not do testing appropriate to provide
100% product quality assurance and does not assume any liabil-
ity for consequential or incidental arising from any use of its prod-
ucts. If such products are to be used in applications in which
personal injury might occur from failure, purchaser must do its
own quality assurance testing appropriate to such applications.
U.S. SALES OFFICES
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V62C1161024L(L)
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