MOSEL VITELIC
1
V62C2182048
256K X 8 LOW POWER,
LOW VOLTAGE SRAM
PRELIMINARY
V62C2182048 Rev. 1.0 November 1999
Features
s
High-speed: 55, 70 ns
s
Ultra low standby current of 2
A (max.)
s
Fully static operation
s
All inputs and outputs directly compatible
s
Three state outputs
s
Ultra low data retention current (V
CC
= 2V)
s
Extended operating voltage: 2.3V3.6V
s
Packages
32-Pin TSOP
48-Ball CSP BGA
Description
The V62C2182048 is a very low power CMOS
static RAM organized as 131,072 words by 8 bits.
Easy memory expansion is provided by an active
LOW CE1, and active HIGH CE2, an active LOW
OE, and three static I/O's. This device has an
automatic power-down mode feature when
deselected.
Device Usage Chart
Operating
Temperature
Range
Package Outline
Access Time (ns)
Power
Temperature
Mark
T
B
55
70
L
LL
0
C to 70
C
Blank
40
C to +85
C
I
Functional Block Diagram
Row Decoder
SAense Amp
1024
x
2048
Column Decoder
Input Buffer
Control
Circuit
A
0
A
1
A
2
A
3
A
4
A
5
A
6
A
7
A
8
A
9
A
10
A
11
A
12
A
13
A
14
A
15
A
16
2182048 01
I/O
0
I/O
7
OE
WE
CE1
CE2
A
17
2
V62C2182048 Rev. 1.0 November 1999
MOSEL VITELIC
V62C2182048
Pin Descriptions
A
0
A
17
Address Inputs
These 18 address inputs select one of the 256K x 8
bit segments in the RAM.
CE
1
, CE
2
Chip Enable Inputs
CE
1
is active LOW and CE
2
is active HIGH. Both
chip enables must be active to read from or write to
the device. If either chip enable is not active, the
device is deselected and is in a standby power
mode. The I/O pins will be in the high-impedance
state when deselected.
OE
Output Enable Input
The Output Enable input is active LOW. When OE
is LOW with CE LOW and WE HIGH, data of the
selected memory location will be available on the
I/O pins. When OE is HIGH, the I/O pins will be in
the high impedance state.
WE
Write Enable Input
An active LOW input, WE input controls read and
write operations. When CE and WE inputs are both
LOW, the data present on the I/O pins will be
written into the selected memory location.
I/O
0
I/O
7
Data Input and Data Output Ports
These 8 bidirectional ports are used to read data
from and write data into the RAM.
V
CC
Power Supply
GND
Ground
Pin Configurations (Top View)
32-Pin TSOP (Standard)
48 BGA
A11
A9
A8
A13
WE
CE2
A15
VCC
A17
A16
A14
A12
A7
A6
A5
A4
OE
A10
CE1
I/O7
I/O6
I/O5
I/O4
I/O3
GND
I/O2
I/O1
I/O0
A0
A1
A2
A3
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
2182048 02
2182048-03
A
1
2
3
4
5
6
1
Note: NC means no connect.
2
TOP VIEW
TOP VIEW
3
4
5
6
B
C
D
E
F
G
H
A
A0
I/O4
I/O5
B
C
D
E
F
G
H
VSS
VCC
I/O6
I/O7
A9
A1
A2
NC
NC
NC
NC
OE
A10
CE2
WE
NC
NC
NC
NC
CE1
A11
A3
A4
A5
NC
NC
A17
A16
A12
A6
A7
NC
NC
NC
NC
A15
A13
A8
I/O0
I/O1
VCC
VSS
I/O2
I/O3
A14
MOSEL VITELIC
V62C2182048
3
V62C2182048 Rev. 1.0 November 1999
Part Number Information
Absolute Maximum Ratings
(1)
NOTE:
1.
Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress
rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections
of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
Symbol
Parameter
Commercial
Industrial
Units
V
CC
Supply Voltage
-0.5 to + V
CC
+ 0.5
-0.5 to + V
CC
+ 0.5
V
V
N
Input Voltage
-0.5 to + V
CC
+ 0.5
-0.5 to + V
CC
+ 0.5
V
V
DQ
Input/Output Voltage Applied
V
CC
+ 0.3
V
CC
+ 0.3
V
T
BIAS
Temperature Under Bias
-10 to +125
-65 to +135
C
T
STG
Storage Temperature
-55 to +125
-65 to +150
C
SRAM
FAMILY
C = CMOS PROCESS
62 = STANDARD
21 = 2.3V3.6V
OPERATING
VOLTAGE
2048K
ORGANIZATION
PKG
SPEED
2182048 04
62
C
8
21
2048
MOSEL-VITELIC
MANUFACTURED
V
8 = 8-bit
55 ns
70 ns
TEMP.
BLANK = 0
C to 70
C
I = -40
C to +85
C
L = LOW POWER
LL = LOW LOW POWER
T = TSOP STANDARD
B = BGA
DENSITY
PWR.
Capacitance*
T
A
= 25
C, f = 1.0MHz
NOTE:
1.
This parameter is guaranteed and not tested.
Truth Table
NOTE:
X = Don't Care, L = LOW, H = HIGH
Symbol
Parameter Conditions
Max.
Unit
C
IN
Input Capacitance
V
IN
= 0V
6
pF
C
OUT
Output Capacitance
V
I/O
= 0V
8
pF
Mode
CE
1
CE
2
OE
WE
I/O
Operation
Standby
H
X
X
X
High Z
Standby
X
L
X
X
High Z
Output Disable
L
H
H
H
High Z
Read
L
H
L
H
D
OUT
Write
L
H
X
L
D
IN
4
V62C2182048 Rev. 1.0 November 1999
MOSEL VITELIC
V62C2182048
DC Electrical Characteristics
(over all temperature ranges, V
CC
= 2.3V3.6V)
NOTES:
1.
These are absolute values with respect to device ground and all overshoots due to system or tester noise are included.
2.
V
IL
(Min.) = -3.0V for pulse width < t
RC
/2.
3.
f
MAX
= 1/t
RC
.
Symbol
Parameter
Test Conditions
Min.
Typ.
Max.
Units
V
IL
Input LOW Voltage
(1,2)
-0.5
--
0.4
V
V
IH
Input HIGH Voltage
(1)
2.2
--
V
CC
+0.3
V
I
IL
Input Leakage Current
V
CC
= Max, V
IN
= 0V to V
CC
--
--
1
A
I
OL
Output Leakage Current
V
CC
= Max, CE
1
= V
IH
, V
OUT
= 0V to V
CC
--
--
1
A
V
OL
Output LOW Voltage
V
CC
= Min, I
OL
= 2mA
--
--
0.4
V
V
OH
Output HIGH Voltage
V
CC
= Min, I
OH
= -1mA
2.4
--
--
V
Symbol
Parameter
Comm.
Ind.
Units
I
CC
Operating Power Supply Current, CE
1
= V
IL
, CE
2
= V
IH
,
Output Open, V
CC
= Max., f = 0
L
5
6
mA
LL
4
5
I
CC1
Average Operating Current, CE
1
= V
IL
, CE
2
= V
CC
0.2, Output Open,
V
CC
= Max., f = f
MAX
(3)
50
60
mA
I
SB
TTL Standby Current
CE
1
V
IH
, CE
2
V
IL
, V
CC
= Max.
L
0.5
1
mA
LL
0.2
1
I
SB1
CMOS Standby Current, CE
1
V
CC
0.2V, CE
2
0.2V,
V
IN
V
CC
0.2V or V
IN
0.2V, V
CC
= Max.
L
10
20
A
LL
2
5
AC Test Conditions
AC Test Loads and Waveforms
Input Pulse Levels
0 to 3V
Input Rise and Fall Times
5 ns
Timing Reference Levels
1.4V
Output Load
see below
* Includes scope and jig capacitance
C
L
= 30pF + 1TTL Load
C
L
*
TTL
2182048 05
MOSEL VITELIC
V62C2182048
5
V62C2182048 Rev. 1.0 November 1999
Data Retention Characteristics
NOTES:
1.
t
RC
= Read Cycle Time
Low V
CC
Data Retention Waveform (1) (CE
1
Controlled)
Key to Switching Waveforms
Symbol
Parameter
Min.
Max.
Units
V
DR
V
CC
for Data Retention
CE
1
V
CC
0.2V, CE
2
0.2V,
V
IN
V
CC
0.2V, or V
IN
0.2V
2.0
--
V
I
CCDR
Data Retention Current
CE
1
V
DR
0.2V, CE
2
0.2V,
V
IN
V
CC
0.2V, or V
IN
0.2V
L
--
2
A
LL
--
1
t
CDR
Chip Deselect to Data Retention Time
0
--
ns
t
R
Operation Recovery Time (see Retention Waveform)
t
RC
(1)
--
ns
V
CC
2182048 06
Data Retention Mode
CE
1
V
CC
0.2V
CE
1
2.2V
2.2V
2.7V
t
CDR
t
R
V
DR
2V
2.7V
WAVEFORM
INPUTS
OUTPUTS
MUST BE
STEADY
WILL BE
STEADY
MAY CHANGE
FROM H TO L
WILL BE
CHANGING
FROM H TO L
MAY CHANGE
FROM L TO H
WILL BE
CHANGING
FROM L TO H
DON'T CARE:
ANY CHANGE
PERMITTED
CHANGING:
STATE
UNKNOWN
DOES NOT
APPLY
CENTER
LINE IS HIGH
IMPEDANCE
"OFF" STATE
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