MOSEL VITELIC

V62C31864
2.7 VOLT 8K X 8 STATIC RAM

PRELIMINARY

V62C31864 Rev. 1.6 August 1998

Features

High-speed: 35, 70 ns

Ultra low DC operating current of 2mA (Max.)

Low Power Dissipation:
TTL Standby: 1 mA (Max.)
CMOS Standby: 10

A (Max.)

Fully static operation

All inputs and outputs directly compatible

Three state outputs

Ultra low data retention current (V

= 2V)

Extended operating voltage: 2.7V3.6V

Packages
28-pin TSOP (Standard)
28-pin 300 mil SOP (450 mil pin-to-pin)

Description

The V62C31864 is a 65,536-bit static random

access memory organized as 8,192 words by 8
bits. It is built with MOSEL VITELIC's high
performance CMOS process. Inputs and three-
state outputs are TTL compatible and allow for
direct interfacing with common system bus
structures.

Device Usage Chart

Operating

Temperature

Range

Package Outline

Access Time (ns)

Power

Temperature

Mark

C to 70

Blank

C to +85

Functional Block Diagram

Row

Decoder

512 x 128

Memory Array

Input

Data

Circuit

Column I/O

Column Decoder

Control

Circuit

GND

31864 01

I/O

V62C31864 Rev. 1.6 August 1998

MOSEL VITELIC

V62C31864

Pin Descriptions

Address Inputs

These 13 address inputs select one of the 8,192 x 8
bit segments in the RAM.

, CE

Chip Enable Inputs

is active LOW and CE

is active HIGH. Both

chip enables must be active to read from or write to
the device. If either chip enable is not active, the
device is deselected and is in a standby power
mode. The I/O pins will be in the high-impedance
state when deselected.

Output Enable Input

The Output Enable input is active LOW. When OE
is LOW with CE

LOW, CE

HIGH, and WE HIGH,

data of the selected memory location will be
available on the I/O pins. When OE is HIGH, the I/O
pins will be in the high impedance state.

Write Enable Input

An active LOW input, WE input controls read and
write operations. When CE

and WE inputs are

both LOW with CE

HIGH, the data present on the

I/O pins will be written into the selected memory
location.

I/O

Data Input and Data Output Ports

These 8 bidirectional ports are used to read data
from and write data into the RAM.

Power Supply

GND

Ground

Pin Configurations (Top View)

28-Pin SOP

28-Pin TSOP (Standard)

I/O

GND

I/O

51864 02

I/O

A11

A9
A8

CE2

VCC

A12

A7
A6
A5
A4
A3

A10
CE1
I/O7
I/O6
I/O5
I/O4
I/O3
GND
I/O2
I/O1
I/O0
A0
A1
A2

22
23
24
25
26
27
28
1
2
3
4
5
6
7

21
20
19
18
17
16
15
14
13
12
11
10

9
8

51864 03

MOSEL VITELIC

V62C31864

V62C31864 Rev. 1.6 August 1998

Part Number Information

Absolute Maximum Ratings

(1)

NOTE:

Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress
rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections
of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect
reliability.

Symbol

Parameter

Commercial

Industrial

Units

Supply Voltage

-0.5 to V

+0.5

-0.5 to V

+0.5

Input Voltage

-0.5 to V

+0.5

-0.5 to V

+0.5

Input/Output Voltage Applied

+ 0.3

BIAS

Temperature Under Bias

-10 to +125

-65 to +135

STG

Storage Temperature

-55 to +125

-65 to +150

SRAM

FAMILY

C = CMOS PROCESS

62 = ASYNCHRONOUS, SLOW

31 = 2.7V 3.6V

OPERATING

VOLTAGE

64K

ORGANIZATION

PKG

SPEED

31864 05

PWR.

MOSEL-VITELIC

MANUFACTURED

8 = 8-bit

35 ns
70 ns

TEMP.

BLANK = 0

C to 70

I = -40

C to +85

L = LOW POWER
LL =DOUBLE LOW POWER

F = 330 mil SOP
T = TSOP standard

DENSITY

Capacitance*

= 25

C, f = 1.0MHz

NOTE:

* This parameter is guaranteed and not tested.

Truth Table

NOTE:

X = Don't Care, L = LOW, H = HIGH

Symbol

Parameter Conditions

Max.

Unit

Input Capacitance

= 0V

OUT

Output Capacitance

I/O

= 0V

Mode

I/O

Operation

Standby

High Z

Standby

High Z

Output Disable

High Z

Read

OUT

Write

V62C31864 Rev. 1.6 August 1998

MOSEL VITELIC

V62C31864

DC Electrical Characteristics

(over all temperature ranges, V

= 2.7V 3.6V)

NOTES:

These are absolute values with respect to device ground and all overshoots due to system or tester noise are included.

(Min.) = -3.0V for pulse width < 20ns.

MAX

= 1/t

Maximum values.

Symbol

Parameter

Test Conditions

Min.

Typ.

Max.

Units

Power Supply Voltage

2.7

3.6

Input LOW Voltage

(1,2)

-0.3

0.4

Input HIGH Voltage

(1)

2.2

+0.3

Input Leakage Current

= Max, V

= 0V to V

-2

Output Leakage Current

= Max, CE = V

, V

OUT

= 0V to V

-2

Output LOW Voltage

= Min, I

= 2.1mA

0.4

Output HIGH Voltage

= Min, I

= -1mA

2.4

Symbol

Parameter

Com.

(4)

Ind.

(4)

Units

Operating Power Supply Current, CE

= V

, CE

= V

Output Open, V

= Max., f = 0

CC1

Average Operating Current, CE

= V

, CE

= V

Output Open, V

= Max., f = f

MAX

(3)

TTL Standby Current
CE

, CE

, V

= Max.

SB1

CMOS Standby Current, CE

0.2V, CE

0.2V,

0.2V or V

0.2V, V

= Max.

AC Test Conditions

AC Test Loads and Waveforms

Key to Switching Waveforms

Input Pulse Levels

0 to 3V

Input Rise and Fall Times

5 ns

Timing Reference Levels

1.5V

Output Load

see below

+3V

1103

1554

* Includes scope and jig capacitance

I/O Pins

= 30 pF*

51864 06

WAVEFORM

INPUTS

OUTPUTS

MUST BE
STEADY

WILL BE
STEADY

MAY CHANGE
FROM H TO L

WILL BE
CHANGING
FROM H TO L

MAY CHANGE
FROM L TO H

WILL BE
CHANGING
FROM L TO H

DON'T CARE:
ANY CHANGE
PERMITTED

CHANGING:
STATE
UNKNOWN

DOES NOT
APPLY

CENTER
LINE IS HIGH
IMPEDANCE
"OFF" STATE

MOSEL VITELIC

V62C31864

V62C31864 Rev. 1.6 August 1998

Data Retention Characteristics

NOTES:
1.

= Read Cycle Time

= +25

Low V

Data Retention Waveform (1) (CE

Controlled)

Low V

Data Retention Waveform (2) (CE

Controlled)

Symbol

Parameter

Min.

Typ.

(2)

Max.

Units

for Data Retention

0.2V, CE

0.2V,

0.2V, or V

0.2V

2.0

3.6

CCDR

Data Retention Current
CE

0.2V, CE

0.2V,

0.2V, or V

0.2V

Com'l

0.5

Ind.

CDR

Chip Deselect to Data Retention Time

Operation Recovery Time (see Retention Waveform)

(1)

31864 14

Data Retention Mode

0.2V

2.2V

2.7V

CDR

2.7V

31864 15

Data Retention Mode

0.2V

2.2V

2.7V

CDR

2.7V

V62C31864 Rev. 1.6 August 1998

MOSEL VITELIC

V62C31864

AC Electrical Characteristics

(over all temperature ranges, V

= 2.7V 3.6V)

Read Cycle

Write Cycle

Parameter

Name

Parameter

-35

-70

Unit

Min.

Max.

Min.

Max.

Read Cycle Time

Address Access Time

ACS1

Chip Enable Access Time

ACS2

Chip Enable Access Time

Output Enable to Output Valid

CLZ1

Chip Enable to Output in Low Z

CLZ2

Chip Enable to Output in Low Z

OLZ

Output Enable to Output in Low Z

CHZ

Chip Disable to Output in High Z

OHZ

Output Disable to Output in High Z

Output Hold from Address Change

Parameter

Name

Parameter

-35

-70

Unit

Min.

Max.

Min.

Max.

Write Cycle Time

CW1

Chip Enable to End of Write

CW2

Chip Enable to End of Write

Address Setup Time

Address Valid to End of Write

Write Pulse Width

Write Recovery Time

WHZ

Write to Output High-Z

Data Setup to End of Write

Data Hold from End of Write

Output Active from End of Write

MOSEL VITELIC

V62C31864

V62C31864 Rev. 1.6 August 1998

Switching Waveforms (Read Cycle)

Read Cycle 1

(1, 2)

Read Cycle 2

(1, 2, 4)

Read Cycle 3

(1, 3, 4)

NOTES:
1.

WE = V

= V

and CE

= V

Address valid prior to or coincident with CE

transition LOW and/or CE

transition HIGH.

OE = V

Transition is measured

500mV from steady state with C

= 5pF. This parameter is guaranteed and not 100% tested.

ADDRESS

51864 11

I/O

OLZ

OHZ

(5)

ADDRESS

I/O

51864 09

51864 10

I/O

ADDRESS

ACS1

ACS2

CLZ1

(5)

CLZ2

(5)

CHZ

(5)

V62C31864 Rev. 1.6 August 1998

MOSEL VITELIC

V62C31864

Switching Waveforms (Write Cycle)

Write Cycle 1 (WE Controlled)

(4)

Write Cycle 2 (CE Controlled)

(4)

NOTES:
1.

The internal write time of the memory is defined by the overlap of CE

and CE

active and WE low. Both signals must be active to

initiate and any one signal can terminate a write by going inactive. The data input setup and hold timing should be referenced to
the second transition edge of the signal that terminates the write.

is measured from the earlier of CE

or WE going HIGH, or CE

going LOW at the end of the write cycle.

During this period, I/O pins are in the output state so that the input signals of opposite phase to the outputs must not be applied.

OE = V

or V

. However it is recommended to keep OE at V

during write cycle to avoid bus contention.

If CE

is LOW and CE

is HIGH during this period, I/O pins are in the output state. Then the data input signals of opposite phase

to the outputs must not be applied to them.

6. t

is measured from CE

going LOW or CE

going HIGH to the end of write.

ADDRESS

OUTPUT

INPUT

51864 12

(6)

(2)

WHZ

(1)

ADDRESS

OUTPUT

High-Z

INPUT

51864 13

(6)

(2)

(4)

(5)

MOSEL VITELIC

V62C31864

V62C31864 Rev. 1.6 August 1998

Package Diagrams

28-pin 330 mil SOP

0.465

0.012

[11.81

0.305]

0.008 [0.203]

0.402

0.012

[10.21

0.203]

0.713 [18.11] TYP

0.050 [1.27] TYP

0.018

0.004

[0.457

0.102]

0.006

0.002

[0.152

0.051]

INDEX

0.339

0.008

[8.61

0.203]

"A"

0 MIN
(STAND OFF)

0.031

0.008

[0.787

0.203]

0.112 [0.285] MAX

0.024 [0.610]

0.008 [0.203] MAX

0.027 [0.686] MAX

View "A"

0.098

0.005

[2.49

0.127]

Units in inches [mm]

MOSEL VITELIC

WORLDWIDE OFFICES

V62C31864

8/98
Printed in U.S.A.

MOSEL VITELIC

3910 N. First Street, San Jose, CA 95134-1501 Ph: (408) 433-6000 Fax: (408) 433-0952 Tlx: 371-9461

The information in this document is subject to change without
notice.

MOSEL VITELIC makes no commitment to update or keep cur-
rent the information contained in this document. No part of this
document may be copied or reproduced in any form or by any
means without the prior written consent of MOSEL-VITELIC.

MOSEL VITELIC subjects its products to normal quality control
sampling techniques which are intended to provide an assurance
of high quality products suitable for usual commercial applica-
tions. MOSEL VITELIC does not do testing appropriate to provide
100% product quality assurance and does not assume any liabil-
ity for consequential or incidental arising from any use of its prod-
ucts. If such products are to be used in applications in which
personal injury might occur from failure, purchaser must do its
own quality assurance testing appropriate to such applications.

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