MOSEL VITELIC
1
V62C5181024
128K X 8 STATIC RAM
PRELIMINARY
V62C5181024 Rev. 2.2 February 2000
Features
s
High-speed: 35, 70 ns
s
Ultra low DC operating current of 5mA (max.)
TTL Standby: 5 mA (Max.)
CMOS Standby: 60
A (Max.)
s
Fully static operation
s
All inputs and outputs directly compatible
s
Three state outputs
s
Ultra low data retention current (V
CC
= 2V)
s
Single 5V
10% Power Supply
s
Packages
32-pin TSOP (Standard)
32-pin 600 mil PDIP
32-pin 440 mil SOP (525 mil pin-to-pin)
Description
The V62C5181024 is a 1,048,576-bit static
random-access memory organized as 131,072
words by 8 bits. It is built with MOSEL VITELIC's
high performance CMOS process. Inputs and
three-state outputs are TTL compatible and allow
for direct interfacing with common system bus
structures.
Device Usage Chart
Operating
Temperature
Range
Package Outline
Access Time (ns)
Power
Temperature
Mark
T
W
P
35
70
L
LL
0
C to 70
C
Blank
40
C to +85
C
I
Functional Block Diagram
Row
Decoder
1024 x 1024
Memory Array
Input
Data
Circuit
Column I/O
Column Decoder
Control
Circuit
V
CC
GND
A
0
5181024 01
A
9
I/O
0
I/O
7
CE
2
OE
WE
CE
1
A
10
A
16
2
V62C5181024 Rev. 2.2 February 2000
MOSEL VITELIC
V62C5181024
Pin Descriptions
A
0
A
16
Address Inputs
These 17 address inputs select one of the 128K x 8
bit segments in the RAM.
CE
1
, CE
2
Chip Enable Inputs
CE
1
is active LOW and CE
2
is active HIGH. Both
chip enables must be active to read from or write to
the device. If either chip enable is not active, the
device is deselected and is in a standby power
mode. The I/O pins will be in the high-impedance
state when deselected.
OE
Output Enable Input
The Output Enable input is active LOW. When OE
is LOW with CE LOW and WE HIGH, data of the
selected memory location will be available on the
I/O pins. When OE is HIGH, the I/O pins will be in
the high impedance state.
WE
Write Enable Input
An active LOW input, WE input controls read and
write operations. When CE and WE inputs are both
LOW, the data present on the I/O pins will be
written into the selected memory location.
I/O
0
I/O
7
Data Input and Data Output Ports
These 8 bidirectional ports are used to read data
from and write data into the RAM.
V
CC
Power Supply
GND
Ground
Pin Configurations (Top View)
32-Pin DIP/SOP
32-Pin TSOP (Standard)
1
32
5181024 02
2
31
3
30
4
29
5
28
6
27
7
26
8
25
9
24
10
23
11
22
12
21
13
20
14
19
15
18
16
17
A
16
A
14
A
12
A
7
A
6
A
5
A
4
A
3
A
2
A
1
A
0
I/O
0
I/O
1
I/O
2
GND
NC
A
15
CE
2
WE
A
13
A
8
A
9
A
11
OE
A
10
CE
1
I/O
7
I/O
6
I/O
5
I/O
4
I/O
3
V
CC
A11
A9
A8
A13
WE
CE2
A15
VCC
NC
A16
A14
A12
A7
A6
A5
A4
OE
A10
CE1
I/O7
I/O6
I/O5
I/O4
I/O3
GND
I/O2
I/O1
I/O0
A0
A1
A2
A3
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
5181024 03
MOSEL VITELIC
V62C5181024
3
V62C5181024 Rev. 2.2 February 2000
Part Number Information
Absolute Maximum Ratings
(1)
NOTE:
1.
Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress
rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections
of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
Symbol
Parameter
Commercial
Industrial
Units
V
CC
Supply Voltage
-0.5 to +7
-0.5 to +7
V
V
N
Input Voltage
-0.5 to +7
-0.5 to +7
V
V
DQ
Input/Output Voltage Applied
V
CC
+ 0.5
V
CC
+ 0.5
V
T
BIAS
Temperature Under Bias
-10 to +125
-65 to +135
C
T
STG
Storage Temperature
-55 to +125
-65 to +150
C
SRAM
FAMILY
C = CMOS PROCESS
62 = STANDARD
51 = 5V
OPERATING
VOLTAGE
1024K
ORGANIZATION
PKG
SPEED
5181024 05
62
C
8
51
1024
MOSEL-VITELIC
MANUFACTURED
V
8 = 8-bit
35 ns
70 ns
TEMP.
BLANK = 0
C to 70
C
I = -40
C to +85
C
L = LOW POWER
LL = LOW LOW POWER
T = TSOP STANDARD
P = 600 mil PDIP
W = 440 mil SOP (525 mil pin-to-pin)
DENSITY
PWR.
Capacitance*
T
A
= 25
C, f = 1.0MHz
NOTE:
1.
This parameter is guaranteed and not tested.
Truth Table
NOTE:
X = Don't Care, L = LOW, H = HIGH
Symbol
Parameter
Conditions
Max.
Unit
C
IN
Input Capacitance
V
IN
= 0V
6
pF
C
OUT
Output Capacitance
V
I/O
= 0V
8
pF
Mode
CE
1
CE
2
OE
WE
I/O
Operation
Standby
H
X
X
X
High Z
Standby
X
L
X
X
High Z
Output Disable
L
H
H
H
High Z
Read
L
H
L
H
D
OUT
Write
L
H
X
L
D
IN
4
V62C5181024 Rev. 2.2 February 2000
MOSEL VITELIC
V62C5181024
DC Electrical Characteristics
(over all temperature ranges, V
CC
= 5V
10%)
NOTES:
1.
These are absolute values with respect to device ground and all overshoots due to system or tester noise are included.
2.
V
IL
(Min.) = -3.0V for pulse width < 20ns.
3.
f
MAX
= 1/t
RC
.
4.
Maximum values.
Symbol
Parameter
Test Conditions
Min.
Typ.
Max.
Units
V
IL
Input LOW Voltage
(1,2)
-0.5
--
0.8
V
V
IH
Input HIGH Voltage
(1)
2.2
--
6
V
I
IL
Input Leakage Current
V
CC
= Max, V
IN
= 0V to V
CC
-5
--
5
A
I
OL
Output Leakage Current
V
CC
= Max, CE
1
= V
IH
, V
OUT
= 0V to V
CC
-5
--
5
A
V
OL
Output LOW Voltage
V
CC
= Min, I
OL
= 2.1mA
--
--
0.4
V
V
OH
Output HIGH Voltage
V
CC
= Min, I
OH
= -1mA
2.4
--
--
V
Symbol
Parameter
Power
Com.
(4)
Ind.
(4)
Units
I
CC
Operating Power Supply Current, CE
1
= V
IL
, CE
2
= V
IH
,
Output Open, V
CC
= Max., f = 0
Read
L
4
6
mA
LL
3
5
Write
L
30
35
LL
25
30
I
CC1
Average Operating Current, CE
1
= V
IL
, CE
2
= V
IH
, Output Open,
V
CC
= Max., f = f
MAX
(3)
35ns
80
90
mA
70ns
75
85
I
SB
TTL Standby Current
CE
1
V
IH
, CE
2
V
IL
, V
CC
= Max.
L
4
6
mA
LL
3
5
I
SB1
CMOS Standby Current, CE
1
V
CC
0.2V, CE
2
0.2V,
V
IN
V
CC
0.2V or V
IN
0.2V, V
CC
= Max.
L
60
80
A
LL
50
60
AC Test Conditions
AC Test Loads and Waveforms
Key to Switching Waveforms
Input Pulse Levels
0 to 3V
Input Rise and Fall Times
5 ns
Timing Reference Levels
1.5V
Output Load
see below
+5V
1800
990
* Includes scope and jig capacitance
I/O Pins
C
L
= 30 pF*
5181024 06
WAVEFORM
INPUTS
OUTPUTS
MUST BE
STEADY
WILL BE
STEADY
MAY CHANGE
FROM H TO L
WILL BE
CHANGING
FROM H TO L
MAY CHANGE
FROM L TO H
WILL BE
CHANGING
FROM L TO H
DON'T CARE:
ANY CHANGE
PERMITTED
CHANGING:
STATE
UNKNOWN
DOES NOT
APPLY
CENTER
LINE IS HIGH
IMPEDANCE
"OFF" STATE
MOSEL VITELIC
V62C5181024
5
V62C5181024 Rev. 2.2 February 2000
Data Retention Characteristics
NOTES:
1.
t
RC
= Read Cycle Time
2.
T
A
= +25
C.
Low V
CC
Data Retention Waveform (1) (CE
1
Controlled)
Low V
CC
Data Retention Waveform (2) (CE
2
Controlled)
Symbol
Parameter
Power
Min.
Typ.
(2)
Max.
Units
V
DR
V
CC
for Data Retention
CE
1
V
CC
0.2V, CE
2
0.2V,
V
IN
V
CC
0.2V, or V
IN
0.2V
2.0
--
5.5
V
I
CCDR
Data Retention Current
CE
1
V
DR
0.2V, CE
2
0.2V,
V
IN
V
CC
0.2V, or V
IN
0.2V
Com'l
L
--
2
50
A
LL
--
2
40
Ind.
L
--
--
100
LL
--
4
60
t
CDR
Chip Deselect to Data Retention Time
0
--
--
ns
t
R
Operation Recovery Time (see Retention Waveform)
t
RC
(1)
--
--
ns
V
CC
5181024 07
Data Retention Mode
CE
1
V
CC
0.2V
CE
1
2.2V
2.2V
4.5V
t
CDR
t
R
V
DR
2V
4.5V
V
CC
5181024 08
Data Retention Mode
CE
2
0.2V
CE
2
2.2V
2.2V
4.5V
t
CDR
t
R
V
DR
2V
4.5V
PDF 
ZIP