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Электронный компонент: V62C518256F70

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MOSEL VITELIC
1
V62C518256
32K X 8 STATIC RAM
PRELIMINARY
V62C518256 Rev. 2.3 November 1998
Features
s
High-speed: 35, 70 ns
s
Ultra low DC operating current of 5mA (max.)
s
Low Power Dissipation:
TTL Standby: 3 mA (Max.)
CMOS Standby: 20
A (Max.)
s
Fully static operation
s
All inputs and outputs directly compatible
s
Three state outputs
s
Ultra low data retention current (V
CC
= 2V)
s
Single 5V
10% Power Supply
s
Packages
28-pin TSOP (Standard)
28-pin 600 mil PDIP
28-pin 330 mil SOP (450 mil pin-to-pin)
Description
The V62C518256 is a 262,144-bit static random
access memory organized as 32,768 words by 8
bits. It is built with MOSEL VITELIC's high
performance CMOS process. Inputs and three-
state outputs are TTL compatible and allow for
direct interfacing with common system bus
structures.
Device Usage Chart
Operating
Temperature
Range
Package Outline
Access Time (ns)
Power
Temperature
Mark
T
P
F
35
70
L
LL
0
C to 70
C
Blank
40
C to +85
C
I
Functional Block Diagram
Row
Decoder
512 x 512
Memory Array
Input
Data
Circuit
Column I/O
Column Decoder
Control
Circuit
V
CC
GND
A
0
518256-01
A
8
I/O
0
I/O
7
CE
OE
WE
A
9
A
14
2
V62C518256 Rev. 2.3 November 1998
MOSEL VITELIC
V62C518256
Pin Descriptions
A
0
A
14
Address Inputs
These 15 address inputs select one of the 32,768 x
8 bit segments in the RAM.
CE
Chip Enable Inputs
CE is an active LOW input. Chip Enable must be
LOW when reading from or writing to the device.
When HIGH, the device is in standby mode with I/O
pins in the high impedance state.
OE
Output Enable Input
The Output Enable input is active LOW. When OE
is LOW with CE LOW and WE HIGH, data of the
selected memory location will be available on the
I/O pins. When OE is HIGH, the I/O pins will be in
the high impedance state.
WE
Write Enable Input
An active LOW input, WE input controls read and
write operations. When CE and WE inputs are both
LOW, the data present on the I/O pins will be
written into the selected memory location.
I/O
0
I/O
7
Data Input and Data Output Ports
These 8 bidirectional ports are used to read data
from and write data into the RAM.
V
CC
Power Supply
GND
Ground
Pin Configurations (Top View)
28-Pin DIP/SOP
28-Pin TSOP (Standard)
V
CC
A
8
A
9
A
11
A
10
OE
I/O
0
I/O
1
I/O
2
GND
A
0
A
1
A
2
A
3
A
4
A
5
I/O
7
I/O
6
I/O
5
I/O
4
518256-01
A
13
WE
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
A
14
A
12
A
6
A
7
I/O
3
CE
OE
A11
A9
A8
A13
WE
VCC
A14
A12
A7
A6
A5
A4
A3
A10
CE
I/O7
I/O6
I/O5
I/O4
I/O3
GND
I/O2
I/O1
I/O0
A0
A1
A2
22
23
24
25
26
27
28
1
2
3
4
5
6
7
21
20
19
18
17
16
15
14
13
12
11
10
9
8
518256-03
MOSEL VITELIC
V62C518256
3
V62C518256 Rev. 2.3 November 1998
Part Number Information
Absolute Maximum Ratings
(1)
NOTE:
1.
Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress
rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections
of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
Symbol
Parameter
Commercial
Industrial
Units
V
CC
Supply Voltage
-0.5 to +7
-0.5 to +7
V
V
N
Input Voltage
-0.5 to +7
-0.5 to +7
V
V
DQ
Input/Output Voltage Applied
V
CC
+ 0.5
V
CC
+ 0.5
V
T
BIAS
Temperature Under Bias
-10 to +125
-65 to +135
C
T
STG
Storage Temperature
-65 to +150
-65 to +150
C
SRAM
FAMILY
C = CMOS PROCESS
62 = STANDARD
51 = 5V
OPERATING
VOLTAGE
256K
ORGANIZATION
PKG
SPEED
518256-05
PWR.
62
C
8
51
256
MOSEL-VITELIC
MANUFACTURED
V
8 = 8-bit
35 ns
70 ns
TEMP.
BLANK = 0
C to 70
C
I = -40
C to +85
C
L = LOW POWER
LL = DOUBLE LOW POWER
T = TSOP STANDARD
P = 600 mil PDIP
F = 330 mil SOP (450 mil Pin-to-Pin)
DENSITY
Capacitance*
T
A
= 25
C, f = 1.0MHz
NOTE:
* This parameter is guaranteed and not tested.
Truth Table
NOTE:
X = Don't Care, L = LOW, H = HIGH
Symbol
Parameter Conditions
Max.
Unit
C
IN
Input Capacitance
V
IN
= 0V
6
pF
C
OUT
Output Capacitance
V
I/O
= 0V
8
pF
Mode
CE
OE
WE
I/O
Operation
Standby
H
X
X
High Z
Read
L
L
H
D
OUT
Read
L
H
H
High Z
Write
L
X
L
D
IN
4
V62C518256 Rev. 2.3 November 1998
MOSEL VITELIC
V62C518256
DC Electrical Characteristics
(over all temperature ranges, V
CC
= 5V
10%)
NOTES:
1.
These are absolute values with respect to device ground and all overshoots due to system or tester noise are included.
2.
V
IL
(Min.) = -3.0V for pulse width < 20ns.
3.
f
MAX
= 1/t
RC
.
4.
Maximum values.
Symbol
Parameter
Test Conditions
Min.
Typ.
Max.
Units
V
IL
Input LOW Voltage
(1,2)
-0.5
--
0.8
V
V
IH
Input HIGH Voltage
(1)
2.2
--
6
V
I
IL
Input Leakage Current
V
CC
= Max, V
IN
= 0V to V
CC
-2
--
2
A
I
OL
Output Leakage Current
V
CC
= Max, CE = V
IH
, V
OUT
= 0V to V
CC
-2
--
2
A
V
OL
Output LOW Voltage
V
CC
= Min, I
OL
= 2.1mA
--
--
0.4
V
V
OH
Output HIGH Voltage
V
CC
= Min, I
OH
= -1mA
2.4
--
--
V
Symbol
Parameter
Power Com.
(4)
Ind.
(4)
Units
I
CC
Operating Power Supply Current, CE = V
IL
Output Open, V
CC
= Max., f = 0
READ
5
6
mA
WRITE
40
50
I
CC1
Average Operating Current, CE
V
IL
Output Open,
V
CC
= Max., f = f
MAX
(3)
60
70
mA
I
SB
TTL Standby Current
CE
V
IH
, V
CC
= Max.
L
4
5
mA
LL
3
4
I
SB1
CMOS Standby Current, CE
V
CC
0.2V,
V
IN
V
CC
0.2V or V
IN
0.2V, V
CC
= Max.
L
60
70
A
LL
20
30
AC Test Conditions
AC Test Loads and Waveforms
Key to Switching Waveforms
Input Pulse Levels
0 to 3V
Input Rise and Fall Times
5 ns
Timing Reference Levels
1.5V
Output Load
see below
+5V
1800
990
* Includes scope and jig capacitance
I/O Pins
C
L
= 30 pF*
518256-06
WAVEFORM
INPUTS
OUTPUTS
MUST BE
STEADY
WILL BE
STEADY
MAY CHANGE
FROM H TO L
WILL BE
CHANGING
FROM H TO L
MAY CHANGE
FROM L TO H
WILL BE
CHANGING
FROM L TO H
DON'T CARE:
ANY CHANGE
PERMITTED
CHANGING:
STATE
UNKNOWN
DOES NOT
APPLY
CENTER
LINE IS HIGH
IMPEDANCE
"OFF" STATE
MOSEL VITELIC
V62C518256
5
V62C518256 Rev. 2.3 November 1998
Data Retention Characteristics
NOTES:
1.
t
RC
= Read Cycle Time
2.
T
A
= +25
C.
Low V
CC
Data Retention Waveform
Symbol
Parameter
Power
Min.
Typ.
(2)
Max.
Units
V
DR
V
CC
for Data Retention
CE
V
CC
0.2V
2.0
--
5.5
V
I
CCDR
Data Retention Current
V
DR
= 3.0V, CE
V
DR
0.2V
Com'l
L
--
0.5
50
A
LL
--
0.5
15
Ind.
L
--
--
70
LL
--
--
20
t
CDR
Chip Deselect to Data Retention Time
0
--
--
ns
t
R
Operation Recovery Time (see Retention Waveform)
t
RC
(1)
--
--
ns
V
CC
518256-07
Data Retention Mode
CE
V
CC
0.2V
CE
2.2V
2.2V
4.5V
t
CDR
t
R
V
DR
2V
4.5V
6
V62C518256 Rev. 2.3 November 1998
MOSEL VITELIC
V62C518256
AC Electrical Characteristics
(over all temperature ranges)
Read Cycle
Write Cycle
Parameter
Name
Parameter
-35
-70
Unit
Min.
Max.
Min.
Max.
t
RC
Read Cycle Time
35
--
70
--
ns
t
AA
Address Access Time
--
35
--
70
ns
t
ACS
Chip Enable Access Time
--
35
--
70
ns
t
OE
Output Enable to Output Valid
--
15
--
30
ns
t
CLZ
Chip Enable to Output in Low Z
5
--
5
--
ns
t
OLZ
Output Enable to Output in Low Z
5
--
5
--
ns
t
CHZ
Chip Disable to Output in High Z
0
20
0
20
ns
t
OHZ
Output Disable to Output in High Z
0
20
0
20
ns
t
OH
Output Hold from Address Change
5
--
5
--
ns
Parameter
Name
Parameter
-35
-70
Unit
Min.
Max.
Min.
Max.
t
WC
Write Cycle Time
35
--
70
--
ns
t
CW
Chip Enable to End of Write
35
--
60
--
ns
t
AS
Address Setup Time
0
--
0
--
ns
t
AW
Address Valid to End of Write
35
--
60
--
ns
t
WP
Write Pulse Width
25
--
50
--
ns
t
WR
Write Recovery Time
0
--
0
--
ns
t
WHZ
Write to Output High-Z
0
20
0
25
ns
t
DW
Data Setup to End of Write
25
--
30
--
ns
t
DH
Data Hold from End of Write
0
--
0
--
ns
t
OHZ
Output Disable to Output in High Z
0
25
0
30
ns
t
OW
Output Active from End of Write
5
--
5
--
ns
MOSEL VITELIC
V62C518256
7
V62C518256 Rev. 2.3 November 1998
Switching Waveforms (Read Cycle)
Read Cycle 1
(1, 2)
Read Cycle 2
(1, 2, 4)
Read Cycle 3
(1, 3, 4)
NOTES:
1.
WE = V
IH
.
2.
CE = V
IL
.
3.
Address valid prior to or coincident with CE transition LOW.
4.
OE = V
IL
.
5.
Transition is measured
500mV from steady state with C
L
= 5pF. This parameter is guaranteed and not 100% tested.
ADDRESS
518256-08
OE
I/O
t
RC
t
AA
t
OE
t
OLZ
t
OHZ
(5)
ADDRESS
I/O
518256-09
t
RC
t
AA
t
OH
t
OH
ADDRESS
518256-10
I/O
CE
t
ACS
t
CLZ
(5)
t
CHZ
(5)
8
V62C518256 Rev. 2.3 November 1998
MOSEL VITELIC
V62C518256
Switching Waveforms (Write Cycle)
Write Cycle 1 (WE Controlled)
(4)
Write Cycle 2 (CE Controlled)
(4)
NOTES:
1.
The internal write time of the memory is defined by the overlap of CE active and WE low. Both signals must be active to initiate and
any one signal can terminate a write by going inactive. The data input setup and hold timing should be referenced to the second
transition edge of the signal that terminates the write.
2.
t
WR
is measured from the earlier of CE or WE going HIGH.
3.
During this period, I/O pins are in the output state so that the input signals of opposite phase to the outputs must not be applied.
4.
OE = V
IL
or V
IH
. However it is recommended to keep OE at V
IH
during write cycle to avoid bus contention.
5. If
CE is LOW during this period, I/O pins are in the output state. Then the data input signals of opposite phase to the outputs must
not be applied to them.
6. t
CW
is measured from CE going LOW to the end of write.
ADDRESS
OUTPUT
INPUT
CE
WE
518256-11
t
WC
t
CW
(6)
t
DW
t
DH
t
AW
t
WR
(2)
t
WHZ
(3)
t
WP
(1)
t
AS
ADDRESS
OUTPUT
INPUT
CE
WE
518256-12
t
WC
t
DW
t
DH
t
AW
t
WR
(2)
Hi-Z
t
AS
(5)
t
CW
(6)
MOSEL VITELIC
V62C518256
9
V62C518256 Rev. 2.3 November 1998
Package Diagrams
28-pin 600 mil Plastic DIP
28-pin 330 mil SOP
15
MAX
0.543
0.010
[13.79
0.254]
INDEX
0.062 [1.57] MAX
0.100 [2.54] TYP.
0.018
0.003
[0.457
0.076]
0.060 +0.020
0.022
0.152 +0.508
0.559
0.195 [4.95] MAX
0.118 [3.00] MIN
0.020 [0.508] MIN
1.470
+0.008
0.012
37.33
+0.203
0.305
0.600 [15.24] TYP
0.010
0.002
[0.254
0.51]
0.991
+0.508
0.559
0.039
+0.020
0.022
Units in inches [mm]
0.465
0.012
[11.81
0.305]
0.008 [0.203]
0.402
0.012
[10.21
0.203]
0.713 [18.11] TYP
0.050 [1.27] TYP
0.018
0.004
[0.457
0.102]
0.006
0.002
[0.152
0.051]
INDEX
0.339
0.008
[8.61
0.203]
"A"
0 MIN
(STAND OFF)
0.031
0.008
[0.787
0.203]
0.112 [0.285] MAX
0.024 [0.610]
0.008 [0.203] MAX
0.027 [0.686] MAX
View "A"
0.098
0.005
[2.49
0.127]
Units in inches [mm]
10
V62C518256 Rev. 2.3 November 1998
MOSEL VITELIC
V62C518256
Package Diagrams
(Cont'd)
28-Pin TSOP
0.528
0.008
[13.41
0.203]
0.020
+0.007
0.008
0.508
+0.178
0.305
0.006
0.002
[0.152
0.051]
0.315
0.004
[8.00
0.102]
0.046
0.004
[1.17
0.102]
0.006
0.004
[0.152
0.102]
Unit in inches [mm]
0.022 [0.559] BSC
0.463
0.003
[11.76
0.076]
MOSEL VITELIC
V62C518256
11
V62C518256 Rev. 2.3 November 1998
MOSEL VITELIC
WORLDWIDE OFFICES
V62C518256
Copyright 1998, MOSEL VITELIC Inc.
11/98
Printed in U.S.A.
MOSEL VITELIC
3910 N. First Street, San Jose, CA 95134-1501 Ph: (408) 433-6000 Fax: (408) 433-0952 Tlx: 371-9461
The information in this document is subject to change without
notice.
MOSEL VITELIC makes no commitment to update or keep cur-
rent the information contained in this document. No part of this
document may be copied or reproduced in any form or by any
means without the prior written consent of MOSEL-VITELIC.
MOSEL VITELIC subjects its products to normal quality control
sampling techniques which are intended to provide an assurance
of high quality products suitable for usual commercial applica-
tions. MOSEL VITELIC does not do testing appropriate to provide
100% product quality assurance and does not assume any liabil-
ity for consequential or incidental arising from any use of its prod-
ucts. If such products are to be used in applications in which
personal injury might occur from failure, purchaser must do its
own quality assurance testing appropriate to such applications.
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